[mirror_ubuntu-jammy-kernel.git] / arch / arm / mach-orion5x / common.c

/*
 * arch/arm/mach-orion5x/common.c
 *
 * Core functions for Marvell Orion 5x SoCs
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <linux/spi/orion_spi.h>
#include <net/dsa.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/timex.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/orion5x.h>
#include <plat/ehci-orion.h>
#include <plat/mv_xor.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
#include "common.h"

/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc orion5x_io_desc[] __initdata = {
	{
		.virtual	= ORION5X_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
		.length		= ORION5X_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= ORION5X_PCIE_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
		.length		= ORION5X_PCIE_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= ORION5X_PCI_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
		.length		= ORION5X_PCI_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= ORION5X_PCIE_WA_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
		.length		= ORION5X_PCIE_WA_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init orion5x_map_io(void)
{
	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
}


/*****************************************************************************
 * EHCI
 ****************************************************************************/
static struct orion_ehci_data orion5x_ehci_data = {
	.dram		= &orion5x_mbus_dram_info,
	.phy_version	= EHCI_PHY_ORION,
};

static u64 ehci_dmamask = 0xffffffffUL;


/*****************************************************************************
 * EHCI0
 ****************************************************************************/
static struct resource orion5x_ehci0_resources[] = {
	{
		.start	= ORION5X_USB0_PHYS_BASE,
		.end	= ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_ORION5X_USB0_CTRL,
		.end	= IRQ_ORION5X_USB0_CTRL,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_ehci0 = {
	.name		= "orion-ehci",
	.id		= 0,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &orion5x_ehci_data,
	},
	.resource	= orion5x_ehci0_resources,
	.num_resources	= ARRAY_SIZE(orion5x_ehci0_resources),
};

void __init orion5x_ehci0_init(void)
{
	platform_device_register(&orion5x_ehci0);
}


/*****************************************************************************
 * EHCI1
 ****************************************************************************/
static struct resource orion5x_ehci1_resources[] = {
	{
		.start	= ORION5X_USB1_PHYS_BASE,
		.end	= ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_ORION5X_USB1_CTRL,
		.end	= IRQ_ORION5X_USB1_CTRL,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_ehci1 = {
	.name		= "orion-ehci",
	.id		= 1,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &orion5x_ehci_data,
	},
	.resource	= orion5x_ehci1_resources,
	.num_resources	= ARRAY_SIZE(orion5x_ehci1_resources),
};

void __init orion5x_ehci1_init(void)
{
	platform_device_register(&orion5x_ehci1);
}


/*****************************************************************************
 * GigE
 ****************************************************************************/
struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
	.dram		= &orion5x_mbus_dram_info,
};

static struct resource orion5x_eth_shared_resources[] = {
	{
		.start	= ORION5X_ETH_PHYS_BASE + 0x2000,
		.end	= ORION5X_ETH_PHYS_BASE + 0x3fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_ORION5X_ETH_ERR,
		.end	= IRQ_ORION5X_ETH_ERR,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_eth_shared = {
	.name		= MV643XX_ETH_SHARED_NAME,
	.id		= 0,
	.dev		= {
		.platform_data	= &orion5x_eth_shared_data,
	},
	.num_resources	= ARRAY_SIZE(orion5x_eth_shared_resources),
	.resource	= orion5x_eth_shared_resources,
};

static struct resource orion5x_eth_resources[] = {
	{
		.name	= "eth irq",
		.start	= IRQ_ORION5X_ETH_SUM,
		.end	= IRQ_ORION5X_ETH_SUM,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_eth = {
	.name		= MV643XX_ETH_NAME,
	.id		= 0,
	.num_resources	= 1,
	.resource	= orion5x_eth_resources,
};

void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
{
	eth_data->shared = &orion5x_eth_shared;
	orion5x_eth.dev.platform_data = eth_data;

	platform_device_register(&orion5x_eth_shared);
	platform_device_register(&orion5x_eth);
}


/*****************************************************************************
 * Ethernet switch
 ****************************************************************************/
static struct resource orion5x_switch_resources[] = {
	{
		.start	= 0,
		.end	= 0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_switch_device = {
	.name		= "dsa",
	.id		= 0,
	.num_resources	= 0,
	.resource	= orion5x_switch_resources,
};

void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
{
	int i;

	if (irq != NO_IRQ) {
		orion5x_switch_resources[0].start = irq;
		orion5x_switch_resources[0].end = irq;
		orion5x_switch_device.num_resources = 1;
	}

	d->netdev = &orion5x_eth.dev;
	for (i = 0; i < d->nr_chips; i++)
		d->chip[i].mii_bus = &orion5x_eth_shared.dev;
	orion5x_switch_device.dev.platform_data = d;

	platform_device_register(&orion5x_switch_device);
}


/*****************************************************************************
 * I2C
 ****************************************************************************/
static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
	.freq_m		= 8, /* assumes 166 MHz TCLK */
	.freq_n		= 3,
	.timeout	= 1000, /* Default timeout of 1 second */
};

static struct resource orion5x_i2c_resources[] = {
	{
		.name	= "i2c base",
		.start	= I2C_PHYS_BASE,
		.end	= I2C_PHYS_BASE + 0x1f,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "i2c irq",
		.start	= IRQ_ORION5X_I2C,
		.end	= IRQ_ORION5X_I2C,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_i2c = {
	.name		= MV64XXX_I2C_CTLR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(orion5x_i2c_resources),
	.resource	= orion5x_i2c_resources,
	.dev		= {
		.platform_data	= &orion5x_i2c_pdata,
	},
};

void __init orion5x_i2c_init(void)
{
	platform_device_register(&orion5x_i2c);
}


/*****************************************************************************
 * SATA
 ****************************************************************************/
static struct resource orion5x_sata_resources[] = {
	{
		.name	= "sata base",
		.start	= ORION5X_SATA_PHYS_BASE,
		.end	= ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "sata irq",
		.start	= IRQ_ORION5X_SATA,
		.end	= IRQ_ORION5X_SATA,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_sata = {
	.name		= "sata_mv",
	.id		= 0,
	.dev		= {
		.coherent_dma_mask	= 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(orion5x_sata_resources),
	.resource	= orion5x_sata_resources,
};

void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
{
	sata_data->dram = &orion5x_mbus_dram_info;
	orion5x_sata.dev.platform_data = sata_data;
	platform_device_register(&orion5x_sata);
}


/*****************************************************************************
 * SPI
 ****************************************************************************/
static struct orion_spi_info orion5x_spi_plat_data = {
	.tclk			= 0,
	.enable_clock_fix	= 1,
};

static struct resource orion5x_spi_resources[] = {
	{
		.name	= "spi base",
		.start	= SPI_PHYS_BASE,
		.end	= SPI_PHYS_BASE + 0x1f,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device orion5x_spi = {
	.name		= "orion_spi",
	.id		= 0,
	.dev		= {
		.platform_data	= &orion5x_spi_plat_data,
	},
	.num_resources	= ARRAY_SIZE(orion5x_spi_resources),
	.resource	= orion5x_spi_resources,
};

void __init orion5x_spi_init()
{
	platform_device_register(&orion5x_spi);
}


/*****************************************************************************
 * UART0
 ****************************************************************************/
static struct plat_serial8250_port orion5x_uart0_data[] = {
	{
		.mapbase	= UART0_PHYS_BASE,
		.membase	= (char *)UART0_VIRT_BASE,
		.irq		= IRQ_ORION5X_UART0,
		.flags		= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= 0,
	}, {
	},
};

static struct resource orion5x_uart0_resources[] = {
	{
		.start		= UART0_PHYS_BASE,
		.end		= UART0_PHYS_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= IRQ_ORION5X_UART0,
		.end		= IRQ_ORION5X_UART0,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_uart0 = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= orion5x_uart0_data,
	},
	.resource		= orion5x_uart0_resources,
	.num_resources		= ARRAY_SIZE(orion5x_uart0_resources),
};

void __init orion5x_uart0_init(void)
{
	platform_device_register(&orion5x_uart0);
}


/*****************************************************************************
 * UART1
 ****************************************************************************/
static struct plat_serial8250_port orion5x_uart1_data[] = {
	{
		.mapbase	= UART1_PHYS_BASE,
		.membase	= (char *)UART1_VIRT_BASE,
		.irq		= IRQ_ORION5X_UART1,
		.flags		= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= 0,
	}, {
	},
};

static struct resource orion5x_uart1_resources[] = {
	{
		.start		= UART1_PHYS_BASE,
		.end		= UART1_PHYS_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= IRQ_ORION5X_UART1,
		.end		= IRQ_ORION5X_UART1,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_uart1 = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM1,
	.dev			= {
		.platform_data	= orion5x_uart1_data,
	},
	.resource		= orion5x_uart1_resources,
	.num_resources		= ARRAY_SIZE(orion5x_uart1_resources),
};

void __init orion5x_uart1_init(void)
{
	platform_device_register(&orion5x_uart1);
}


/*****************************************************************************
 * XOR engine
 ****************************************************************************/
static struct resource orion5x_xor_shared_resources[] = {
	{
		.name	= "xor low",
		.start	= ORION5X_XOR_PHYS_BASE,
		.end	= ORION5X_XOR_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "xor high",
		.start	= ORION5X_XOR_PHYS_BASE + 0x200,
		.end	= ORION5X_XOR_PHYS_BASE + 0x2ff,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device orion5x_xor_shared = {
	.name		= MV_XOR_SHARED_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(orion5x_xor_shared_resources),
	.resource	= orion5x_xor_shared_resources,
};

static u64 orion5x_xor_dmamask = DMA_32BIT_MASK;

static struct resource orion5x_xor0_resources[] = {
	[0] = {
		.start	= IRQ_ORION5X_XOR0,
		.end	= IRQ_ORION5X_XOR0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data orion5x_xor0_data = {
	.shared		= &orion5x_xor_shared,
	.hw_id		= 0,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device orion5x_xor0_channel = {
	.name		= MV_XOR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(orion5x_xor0_resources),
	.resource	= orion5x_xor0_resources,
	.dev		= {
		.dma_mask		= &orion5x_xor_dmamask,
		.coherent_dma_mask	= DMA_64BIT_MASK,
		.platform_data		= (void *)&orion5x_xor0_data,
	},
};

static struct resource orion5x_xor1_resources[] = {
	[0] = {
		.start	= IRQ_ORION5X_XOR1,
		.end	= IRQ_ORION5X_XOR1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data orion5x_xor1_data = {
	.shared		= &orion5x_xor_shared,
	.hw_id		= 1,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device orion5x_xor1_channel = {
	.name		= MV_XOR_NAME,
	.id		= 1,
	.num_resources	= ARRAY_SIZE(orion5x_xor1_resources),
	.resource	= orion5x_xor1_resources,
	.dev		= {
		.dma_mask		= &orion5x_xor_dmamask,
		.coherent_dma_mask	= DMA_64BIT_MASK,
		.platform_data		= (void *)&orion5x_xor1_data,
	},
};

void __init orion5x_xor_init(void)
{
	platform_device_register(&orion5x_xor_shared);

	/*
	 * two engines can't do memset simultaneously, this limitation
	 * satisfied by removing memset support from one of the engines.
	 */
	dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
	dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
	platform_device_register(&orion5x_xor0_channel);

	dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
	dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
	dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
	platform_device_register(&orion5x_xor1_channel);
}


/*****************************************************************************
 * Time handling
 ****************************************************************************/
int orion5x_tclk;

int __init orion5x_find_tclk(void)
{
	u32 dev, rev;

	orion5x_pcie_id(&dev, &rev);
	if (dev == MV88F6183_DEV_ID &&
	    (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
		return 133333333;

	return 166666667;
}

static void orion5x_timer_init(void)
{
	orion5x_tclk = orion5x_find_tclk();
	orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
}

struct sys_timer orion5x_timer = {
	.init = orion5x_timer_init,
};


/*****************************************************************************
 * General
 ****************************************************************************/
/*
 * Identify device ID and rev from PCIe configuration header space '0'.
 */
static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
{
	orion5x_pcie_id(dev, rev);

	if (*dev == MV88F5281_DEV_ID) {
		if (*rev == MV88F5281_REV_D2) {
			*dev_name = "MV88F5281-D2";
		} else if (*rev == MV88F5281_REV_D1) {
			*dev_name = "MV88F5281-D1";
		} else if (*rev == MV88F5281_REV_D0) {
			*dev_name = "MV88F5281-D0";
		} else {
			*dev_name = "MV88F5281-Rev-Unsupported";
		}
	} else if (*dev == MV88F5182_DEV_ID) {
		if (*rev == MV88F5182_REV_A2) {
			*dev_name = "MV88F5182-A2";
		} else {
			*dev_name = "MV88F5182-Rev-Unsupported";
		}
	} else if (*dev == MV88F5181_DEV_ID) {
		if (*rev == MV88F5181_REV_B1) {
			*dev_name = "MV88F5181-Rev-B1";
		} else if (*rev == MV88F5181L_REV_A1) {
			*dev_name = "MV88F5181L-Rev-A1";
		} else {
			*dev_name = "MV88F5181(L)-Rev-Unsupported";
		}
	} else if (*dev == MV88F6183_DEV_ID) {
		if (*rev == MV88F6183_REV_B0) {
			*dev_name = "MV88F6183-Rev-B0";
		} else {
			*dev_name = "MV88F6183-Rev-Unsupported";
		}
	} else {
		*dev_name = "Device-Unknown";
	}
}

void __init orion5x_init(void)
{
	char *dev_name;
	u32 dev, rev;

	orion5x_id(&dev, &rev, &dev_name);
	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);

	orion5x_eth_shared_data.t_clk = orion5x_tclk;
	orion5x_spi_plat_data.tclk = orion5x_tclk;
	orion5x_uart0_data[0].uartclk = orion5x_tclk;
	orion5x_uart1_data[0].uartclk = orion5x_tclk;

	/*
	 * Setup Orion address map
	 */
	orion5x_setup_cpu_mbus_bridge();

	/*
	 * Don't issue "Wait for Interrupt" instruction if we are
	 * running on D0 5281 silicon.
	 */
	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
		printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
		disable_hlt();
	}
}

/*
 * Many orion-based systems have buggy bootloader implementations.
 * This is a common fixup for bogus memory tags.
 */
void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t,
			    char **from, struct meminfo *meminfo)
{
	for (; t->hdr.size; t = tag_next(t))
		if (t->hdr.tag == ATAG_MEM &&
		    (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
		     t->u.mem.start & ~PAGE_MASK)) {
			printk(KERN_WARNING
			       "Clearing invalid memory bank %dKB@0x%08x\n",
			       t->u.mem.size / 1024, t->u.mem.start);
			t->hdr.tag = 0;
		}
}
Commit	Line	Data
585cf175	1	/*
9dd0b194	2	* arch/arm/mach-orion5x/common.c
585cf175	3	*
9dd0b194	4	* Core functions for Marvell Orion 5x SoCs
585cf175 TP	5	*
	6	* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
	7	*
159ffb3a LB	8	* This file is licensed under the terms of the GNU General Public
159ffb3a LB	9	* License version 2. This program is licensed "as is" without any
585cf175 TP	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
ca26f7d3 TP	15	#include <linux/platform_device.h>
ca26f7d3 TP	16	#include <linux/serial_8250.h>
83b6d822	17	#include <linux/mbus.h>
e07c9d85	18	#include <linux/mv643xx_eth.h>
144aa3db	19	#include <linux/mv643xx_i2c.h>
15a32632	20	#include <linux/ata_platform.h>
d323ade1	21	#include <linux/spi/orion_spi.h>
dcf1cece	22	#include <net/dsa.h>
585cf175	23	#include <asm/page.h>
be73a347	24	#include <asm/setup.h>
c67de5b3	25	#include <asm/timex.h>
be73a347	26	#include <asm/mach/arch.h>
585cf175	27	#include <asm/mach/map.h>
2bac1de2	28	#include <asm/mach/time.h>
a09e64fb RK	29	#include <mach/hardware.h>
a09e64fb RK	30	#include <mach/orion5x.h>
6f088f1d	31	#include <plat/ehci-orion.h>
1d5a1a6e	32	#include <plat/mv_xor.h>
6f088f1d LB	33	#include <plat/orion_nand.h>
6f088f1d LB	34	#include <plat/time.h>
585cf175 TP	35	#include "common.h"
	36
	37	/*****************************************************************************
	38	* I/O Address Mapping
	39	****************************************************************************/
9dd0b194	40	static struct map_desc orion5x_io_desc[] __initdata = {
585cf175	41	{
9dd0b194 LB	42	.virtual = ORION5X_REGS_VIRT_BASE,
	43	.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
	44	.length = ORION5X_REGS_SIZE,
e7068ad3 LB	45	.type = MT_DEVICE,
e7068ad3 LB	46	}, {
9dd0b194 LB	47	.virtual = ORION5X_PCIE_IO_VIRT_BASE,
	48	.pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
	49	.length = ORION5X_PCIE_IO_SIZE,
e7068ad3 LB	50	.type = MT_DEVICE,
e7068ad3 LB	51	}, {
9dd0b194 LB	52	.virtual = ORION5X_PCI_IO_VIRT_BASE,
	53	.pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
	54	.length = ORION5X_PCI_IO_SIZE,
e7068ad3 LB	55	.type = MT_DEVICE,
e7068ad3 LB	56	}, {
9dd0b194 LB	57	.virtual = ORION5X_PCIE_WA_VIRT_BASE,
	58	.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
	59	.length = ORION5X_PCIE_WA_SIZE,
e7068ad3	60	.type = MT_DEVICE,
585cf175 TP	61	},
	62	};
	63
9dd0b194	64	void __init orion5x_map_io(void)
585cf175	65	{
9dd0b194	66	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
585cf175	67	}
c67de5b3	68
044f6c7c	69
ca26f7d3	70	/*****************************************************************************
044f6c7c	71	* EHCI
ca26f7d3	72	****************************************************************************/
044f6c7c LB	73	static struct orion_ehci_data orion5x_ehci_data = {
044f6c7c LB	74	.dram = &orion5x_mbus_dram_info,
fb6f5529	75	.phy_version = EHCI_PHY_ORION,
ca26f7d3 TP	76	};
ca26f7d3 TP	77
044f6c7c	78	static u64 ehci_dmamask = 0xffffffffUL;
ca26f7d3	79
ca26f7d3	80
044f6c7c LB	81	/*****************************************************************************
	82	* EHCI0
	83	****************************************************************************/
9dd0b194	84	static struct resource orion5x_ehci0_resources[] = {
ca26f7d3	85	{
9dd0b194	86	.start = ORION5X_USB0_PHYS_BASE,
994cab84	87	.end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
ca26f7d3	88	.flags = IORESOURCE_MEM,
e7068ad3	89	}, {
9dd0b194 LB	90	.start = IRQ_ORION5X_USB0_CTRL,
9dd0b194 LB	91	.end = IRQ_ORION5X_USB0_CTRL,
ca26f7d3 TP	92	.flags = IORESOURCE_IRQ,
	93	},
	94	};
	95
9dd0b194	96	static struct platform_device orion5x_ehci0 = {
ca26f7d3 TP	97	.name = "orion-ehci",
	98	.id = 0,
	99	.dev = {
	100	.dma_mask = &ehci_dmamask,
	101	.coherent_dma_mask = 0xffffffff,
9dd0b194	102	.platform_data = &orion5x_ehci_data,
ca26f7d3	103	},
9dd0b194 LB	104	.resource = orion5x_ehci0_resources,
9dd0b194 LB	105	.num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
ca26f7d3 TP	106	};
ca26f7d3 TP	107
044f6c7c LB	108	void __init orion5x_ehci0_init(void)
	109	{
	110	platform_device_register(&orion5x_ehci0);
	111	}
	112
	113
	114	/*****************************************************************************
	115	* EHCI1
	116	****************************************************************************/
	117	static struct resource orion5x_ehci1_resources[] = {
	118	{
	119	.start = ORION5X_USB1_PHYS_BASE,
	120	.end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
	121	.flags = IORESOURCE_MEM,
	122	}, {
	123	.start = IRQ_ORION5X_USB1_CTRL,
	124	.end = IRQ_ORION5X_USB1_CTRL,
	125	.flags = IORESOURCE_IRQ,
	126	},
	127	};
	128
9dd0b194	129	static struct platform_device orion5x_ehci1 = {
ca26f7d3 TP	130	.name = "orion-ehci",
	131	.id = 1,
	132	.dev = {
	133	.dma_mask = &ehci_dmamask,
	134	.coherent_dma_mask = 0xffffffff,
9dd0b194	135	.platform_data = &orion5x_ehci_data,
ca26f7d3	136	},
9dd0b194 LB	137	.resource = orion5x_ehci1_resources,
9dd0b194 LB	138	.num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
ca26f7d3 TP	139	};
ca26f7d3 TP	140
044f6c7c LB	141	void __init orion5x_ehci1_init(void)
	142	{
	143	platform_device_register(&orion5x_ehci1);
	144	}
	145
	146
e07c9d85	147	/*****************************************************************************
044f6c7c	148	* GigE
e07c9d85	149	****************************************************************************/
d236f5a5 LB	150	struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
	151	.dram = &orion5x_mbus_dram_info,
	152	};
	153
9dd0b194	154	static struct resource orion5x_eth_shared_resources[] = {
e07c9d85	155	{
9dd0b194 LB	156	.start = ORION5X_ETH_PHYS_BASE + 0x2000,
9dd0b194 LB	157	.end = ORION5X_ETH_PHYS_BASE + 0x3fff,
e07c9d85	158	.flags = IORESOURCE_MEM,
eeff6d86 LB	159	}, {
	160	.start = IRQ_ORION5X_ETH_ERR,
	161	.end = IRQ_ORION5X_ETH_ERR,
	162	.flags = IORESOURCE_IRQ,
e07c9d85 TP	163	},
	164	};
	165
9dd0b194	166	static struct platform_device orion5x_eth_shared = {
e07c9d85 TP	167	.name = MV643XX_ETH_SHARED_NAME,
e07c9d85 TP	168	.id = 0,
d236f5a5 LB	169	.dev = {
	170	.platform_data = &orion5x_eth_shared_data,
	171	},
eeff6d86	172	.num_resources = ARRAY_SIZE(orion5x_eth_shared_resources),
9dd0b194	173	.resource = orion5x_eth_shared_resources,
e07c9d85 TP	174	};
e07c9d85 TP	175
9dd0b194	176	static struct resource orion5x_eth_resources[] = {
e07c9d85 TP	177	{
e07c9d85 TP	178	.name = "eth irq",
9dd0b194 LB	179	.start = IRQ_ORION5X_ETH_SUM,
9dd0b194 LB	180	.end = IRQ_ORION5X_ETH_SUM,
e07c9d85	181	.flags = IORESOURCE_IRQ,
e7068ad3	182	},
e07c9d85 TP	183	};
e07c9d85 TP	184
9dd0b194	185	static struct platform_device orion5x_eth = {
e07c9d85 TP	186	.name = MV643XX_ETH_NAME,
	187	.id = 0,
	188	.num_resources = 1,
9dd0b194	189	.resource = orion5x_eth_resources,
e07c9d85 TP	190	};
e07c9d85 TP	191
9dd0b194	192	void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
e07c9d85	193	{
fa3959f4	194	eth_data->shared = &orion5x_eth_shared;
9dd0b194	195	orion5x_eth.dev.platform_data = eth_data;
fa3959f4	196
9dd0b194 LB	197	platform_device_register(&orion5x_eth_shared);
9dd0b194 LB	198	platform_device_register(&orion5x_eth);
e07c9d85 TP	199	}
e07c9d85 TP	200
044f6c7c	201
dcf1cece LB	202	/*****************************************************************************
	203	* Ethernet switch
	204	****************************************************************************/
	205	static struct resource orion5x_switch_resources[] = {
	206	{
	207	.start = 0,
	208	.end = 0,
	209	.flags = IORESOURCE_IRQ,
	210	},
	211	};
	212
	213	static struct platform_device orion5x_switch_device = {
	214	.name = "dsa",
	215	.id = 0,
	216	.num_resources = 0,
	217	.resource = orion5x_switch_resources,
	218	};
	219
	220	void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
	221	{
e84665c9 LB	222	int i;
e84665c9 LB	223
dcf1cece LB	224	if (irq != NO_IRQ) {
	225	orion5x_switch_resources[0].start = irq;
	226	orion5x_switch_resources[0].end = irq;
	227	orion5x_switch_device.num_resources = 1;
	228	}
	229
dcf1cece	230	d->netdev = &orion5x_eth.dev;
e84665c9 LB	231	for (i = 0; i < d->nr_chips; i++)
e84665c9 LB	232	d->chip[i].mii_bus = &orion5x_eth_shared.dev;
dcf1cece LB	233	orion5x_switch_device.dev.platform_data = d;
	234
	235	platform_device_register(&orion5x_switch_device);
	236	}
	237
	238
144aa3db	239	/*****************************************************************************
044f6c7c	240	* I2C
144aa3db	241	****************************************************************************/
9dd0b194	242	static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
144aa3db HVR	243	.freq_m = 8, /* assumes 166 MHz TCLK */
	244	.freq_n = 3,
	245	.timeout = 1000, /* Default timeout of 1 second */
	246	};
	247
9dd0b194	248	static struct resource orion5x_i2c_resources[] = {
144aa3db	249	{
e7068ad3 LB	250	.name = "i2c base",
e7068ad3 LB	251	.start = I2C_PHYS_BASE,
044f6c7c	252	.end = I2C_PHYS_BASE + 0x1f,
e7068ad3 LB	253	.flags = IORESOURCE_MEM,
	254	}, {
	255	.name = "i2c irq",
	256	.start = IRQ_ORION5X_I2C,
	257	.end = IRQ_ORION5X_I2C,
	258	.flags = IORESOURCE_IRQ,
144aa3db HVR	259	},
	260	};
	261
9dd0b194	262	static struct platform_device orion5x_i2c = {
144aa3db HVR	263	.name = MV64XXX_I2C_CTLR_NAME,
144aa3db HVR	264	.id = 0,
9dd0b194 LB	265	.num_resources = ARRAY_SIZE(orion5x_i2c_resources),
9dd0b194 LB	266	.resource = orion5x_i2c_resources,
144aa3db	267	.dev = {
e7068ad3	268	.platform_data = &orion5x_i2c_pdata,
144aa3db HVR	269	},
	270	};
	271
044f6c7c LB	272	void __init orion5x_i2c_init(void)
	273	{
	274	platform_device_register(&orion5x_i2c);
	275	}
	276
	277
f244baa3	278	/*****************************************************************************
044f6c7c	279	* SATA
f244baa3	280	****************************************************************************/
9dd0b194	281	static struct resource orion5x_sata_resources[] = {
f244baa3	282	{
e7068ad3 LB	283	.name = "sata base",
	284	.start = ORION5X_SATA_PHYS_BASE,
	285	.end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
	286	.flags = IORESOURCE_MEM,
	287	}, {
	288	.name = "sata irq",
	289	.start = IRQ_ORION5X_SATA,
	290	.end = IRQ_ORION5X_SATA,
	291	.flags = IORESOURCE_IRQ,
	292	},
f244baa3 SB	293	};
f244baa3 SB	294
9dd0b194	295	static struct platform_device orion5x_sata = {
e7068ad3 LB	296	.name = "sata_mv",
e7068ad3 LB	297	.id = 0,
f244baa3 SB	298	.dev = {
	299	.coherent_dma_mask = 0xffffffff,
	300	},
e7068ad3 LB	301	.num_resources = ARRAY_SIZE(orion5x_sata_resources),
e7068ad3 LB	302	.resource = orion5x_sata_resources,
f244baa3 SB	303	};
f244baa3 SB	304
9dd0b194	305	void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
f244baa3	306	{
9dd0b194 LB	307	sata_data->dram = &orion5x_mbus_dram_info;
	308	orion5x_sata.dev.platform_data = sata_data;
	309	platform_device_register(&orion5x_sata);
f244baa3 SB	310	}
f244baa3 SB	311
044f6c7c	312
d323ade1 LB	313	/*****************************************************************************
	314	* SPI
	315	****************************************************************************/
	316	static struct orion_spi_info orion5x_spi_plat_data = {
c0e19363 NP	317	.tclk = 0,
c0e19363 NP	318	.enable_clock_fix = 1,
d323ade1 LB	319	};
	320
	321	static struct resource orion5x_spi_resources[] = {
	322	{
	323	.name = "spi base",
	324	.start = SPI_PHYS_BASE,
	325	.end = SPI_PHYS_BASE + 0x1f,
	326	.flags = IORESOURCE_MEM,
	327	},
	328	};
	329
	330	static struct platform_device orion5x_spi = {
	331	.name = "orion_spi",
	332	.id = 0,
	333	.dev = {
	334	.platform_data = &orion5x_spi_plat_data,
	335	},
	336	.num_resources = ARRAY_SIZE(orion5x_spi_resources),
	337	.resource = orion5x_spi_resources,
	338	};
	339
	340	void __init orion5x_spi_init()
	341	{
	342	platform_device_register(&orion5x_spi);
	343	}
	344
	345
2bac1de2	346	/*****************************************************************************
044f6c7c LB	347	* UART0
	348	****************************************************************************/
	349	static struct plat_serial8250_port orion5x_uart0_data[] = {
	350	{
	351	.mapbase = UART0_PHYS_BASE,
	352	.membase = (char *)UART0_VIRT_BASE,
	353	.irq = IRQ_ORION5X_UART0,
	354	.flags = UPF_SKIP_TEST \| UPF_BOOT_AUTOCONF,
	355	.iotype = UPIO_MEM,
	356	.regshift = 2,
ebe35aff	357	.uartclk = 0,
044f6c7c LB	358	}, {
	359	},
	360	};
	361
	362	static struct resource orion5x_uart0_resources[] = {
	363	{
	364	.start = UART0_PHYS_BASE,
	365	.end = UART0_PHYS_BASE + 0xff,
	366	.flags = IORESOURCE_MEM,
	367	}, {
	368	.start = IRQ_ORION5X_UART0,
	369	.end = IRQ_ORION5X_UART0,
	370	.flags = IORESOURCE_IRQ,
	371	},
	372	};
	373
	374	static struct platform_device orion5x_uart0 = {
	375	.name = "serial8250",
	376	.id = PLAT8250_DEV_PLATFORM,
	377	.dev = {
	378	.platform_data = orion5x_uart0_data,
	379	},
	380	.resource = orion5x_uart0_resources,
	381	.num_resources = ARRAY_SIZE(orion5x_uart0_resources),
	382	};
	383
	384	void __init orion5x_uart0_init(void)
	385	{
	386	platform_device_register(&orion5x_uart0);
	387	}
	388
	389
	390	/*****************************************************************************
	391	* UART1
2bac1de2	392	****************************************************************************/
044f6c7c LB	393	static struct plat_serial8250_port orion5x_uart1_data[] = {
	394	{
	395	.mapbase = UART1_PHYS_BASE,
	396	.membase = (char *)UART1_VIRT_BASE,
	397	.irq = IRQ_ORION5X_UART1,
	398	.flags = UPF_SKIP_TEST \| UPF_BOOT_AUTOCONF,
	399	.iotype = UPIO_MEM,
	400	.regshift = 2,
ebe35aff	401	.uartclk = 0,
044f6c7c LB	402	}, {
	403	},
	404	};
	405
	406	static struct resource orion5x_uart1_resources[] = {
	407	{
	408	.start = UART1_PHYS_BASE,
	409	.end = UART1_PHYS_BASE + 0xff,
	410	.flags = IORESOURCE_MEM,
	411	}, {
	412	.start = IRQ_ORION5X_UART1,
	413	.end = IRQ_ORION5X_UART1,
	414	.flags = IORESOURCE_IRQ,
	415	},
	416	};
	417
	418	static struct platform_device orion5x_uart1 = {
	419	.name = "serial8250",
	420	.id = PLAT8250_DEV_PLATFORM1,
	421	.dev = {
	422	.platform_data = orion5x_uart1_data,
	423	},
	424	.resource = orion5x_uart1_resources,
	425	.num_resources = ARRAY_SIZE(orion5x_uart1_resources),
	426	};
	427
	428	void __init orion5x_uart1_init(void)
	429	{
	430	platform_device_register(&orion5x_uart1);
	431	}
2bac1de2	432
044f6c7c	433
1d5a1a6e SB	434	/*****************************************************************************
	435	* XOR engine
	436	****************************************************************************/
	437	static struct resource orion5x_xor_shared_resources[] = {
	438	{
	439	.name = "xor low",
	440	.start = ORION5X_XOR_PHYS_BASE,
	441	.end = ORION5X_XOR_PHYS_BASE + 0xff,
	442	.flags = IORESOURCE_MEM,
	443	}, {
	444	.name = "xor high",
	445	.start = ORION5X_XOR_PHYS_BASE + 0x200,
	446	.end = ORION5X_XOR_PHYS_BASE + 0x2ff,
	447	.flags = IORESOURCE_MEM,
	448	},
	449	};
	450
	451	static struct platform_device orion5x_xor_shared = {
	452	.name = MV_XOR_SHARED_NAME,
	453	.id = 0,
	454	.num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
	455	.resource = orion5x_xor_shared_resources,
	456	};
	457
	458	static u64 orion5x_xor_dmamask = DMA_32BIT_MASK;
	459
	460	static struct resource orion5x_xor0_resources[] = {
	461	[0] = {
	462	.start = IRQ_ORION5X_XOR0,
	463	.end = IRQ_ORION5X_XOR0,
	464	.flags = IORESOURCE_IRQ,
	465	},
	466	};
	467
	468	static struct mv_xor_platform_data orion5x_xor0_data = {
	469	.shared = &orion5x_xor_shared,
	470	.hw_id = 0,
	471	.pool_size = PAGE_SIZE,
	472	};
	473
	474	static struct platform_device orion5x_xor0_channel = {
	475	.name = MV_XOR_NAME,
	476	.id = 0,
	477	.num_resources = ARRAY_SIZE(orion5x_xor0_resources),
	478	.resource = orion5x_xor0_resources,
	479	.dev = {
	480	.dma_mask = &orion5x_xor_dmamask,
	481	.coherent_dma_mask = DMA_64BIT_MASK,
	482	.platform_data = (void *)&orion5x_xor0_data,
	483	},
	484	};
	485
	486	static struct resource orion5x_xor1_resources[] = {
	487	[0] = {
	488	.start = IRQ_ORION5X_XOR1,
	489	.end = IRQ_ORION5X_XOR1,
	490	.flags = IORESOURCE_IRQ,
	491	},
	492	};
	493
	494	static struct mv_xor_platform_data orion5x_xor1_data = {
	495	.shared = &orion5x_xor_shared,
	496	.hw_id = 1,
	497	.pool_size = PAGE_SIZE,
498	};
499
500	static struct platform_device orion5x_xor1_channel = {
501	.name = MV_XOR_NAME,
502	.id = 1,
503	.num_resources = ARRAY_SIZE(orion5x_xor1_resources),
504	.resource = orion5x_xor1_resources,
505	.dev = {
506	.dma_mask = &orion5x_xor_dmamask,
507	.coherent_dma_mask = DMA_64BIT_MASK,
508	.platform_data = (void *)&orion5x_xor1_data,
509	},
510	};
511
512	void __init orion5x_xor_init(void)
513	{
514	platform_device_register(&orion5x_xor_shared);
515
516	/*
517	* two engines can't do memset simultaneously, this limitation
518	* satisfied by removing memset support from one of the engines.
519	*/
520	dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
521	dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
522	platform_device_register(&orion5x_xor0_channel);
523
524	dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
525	dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
526	dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
527	platform_device_register(&orion5x_xor1_channel);
528	}
529
530
044f6c7c LB	531	/*****************************************************************************
	532	* Time handling
	533	****************************************************************************/
ebe35aff LB	534	int orion5x_tclk;
	535
	536	int __init orion5x_find_tclk(void)
	537	{
d323ade1 LB	538	u32 dev, rev;
	539
	540	orion5x_pcie_id(&dev, &rev);
	541	if (dev == MV88F6183_DEV_ID &&
	542	(readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
	543	return 133333333;
	544
ebe35aff LB	545	return 166666667;
	546	}
	547
9dd0b194	548	static void orion5x_timer_init(void)
2bac1de2	549	{
ebe35aff LB	550	orion5x_tclk = orion5x_find_tclk();
ebe35aff LB	551	orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
2bac1de2 LB	552	}
2bac1de2 LB	553
9dd0b194	554	struct sys_timer orion5x_timer = {
e7068ad3	555	.init = orion5x_timer_init,
2bac1de2 LB	556	};
2bac1de2 LB	557
044f6c7c	558
c67de5b3 TP	559	/*****************************************************************************
	560	* General
	561	****************************************************************************/
c67de5b3	562	/*
b46926bb	563	* Identify device ID and rev from PCIe configuration header space '0'.
c67de5b3	564	*/
9dd0b194	565	static void __init orion5x_id(u32 dev, u32 rev, char **dev_name)
c67de5b3	566	{
9dd0b194	567	orion5x_pcie_id(dev, rev);
c67de5b3 TP	568
	569	if (*dev == MV88F5281_DEV_ID) {
	570	if (*rev == MV88F5281_REV_D2) {
	571	*dev_name = "MV88F5281-D2";
	572	} else if (*rev == MV88F5281_REV_D1) {
	573	*dev_name = "MV88F5281-D1";
ce72e36e LB	574	} else if (*rev == MV88F5281_REV_D0) {
ce72e36e LB	575	*dev_name = "MV88F5281-D0";
c67de5b3 TP	576	} else {
	577	*dev_name = "MV88F5281-Rev-Unsupported";
	578	}
	579	} else if (*dev == MV88F5182_DEV_ID) {
	580	if (*rev == MV88F5182_REV_A2) {
	581	*dev_name = "MV88F5182-A2";
	582	} else {
	583	*dev_name = "MV88F5182-Rev-Unsupported";
	584	}
c9e3de94 HVR	585	} else if (*dev == MV88F5181_DEV_ID) {
	586	if (*rev == MV88F5181_REV_B1) {
	587	*dev_name = "MV88F5181-Rev-B1";
d2b2a6bb LB	588	} else if (*rev == MV88F5181L_REV_A1) {
d2b2a6bb LB	589	*dev_name = "MV88F5181L-Rev-A1";
c9e3de94	590	} else {
d2b2a6bb	591	*dev_name = "MV88F5181(L)-Rev-Unsupported";
c9e3de94	592	}
d323ade1 LB	593	} else if (*dev == MV88F6183_DEV_ID) {
	594	if (*rev == MV88F6183_REV_B0) {
	595	*dev_name = "MV88F6183-Rev-B0";
	596	} else {
	597	*dev_name = "MV88F6183-Rev-Unsupported";
	598	}
c67de5b3 TP	599	} else {
	600	*dev_name = "Device-Unknown";
	601	}
	602	}
	603
9dd0b194	604	void __init orion5x_init(void)
c67de5b3 TP	605	{
	606	char *dev_name;
	607	u32 dev, rev;
	608
9dd0b194	609	orion5x_id(&dev, &rev, &dev_name);
ebe35aff LB	610	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
	611
	612	orion5x_eth_shared_data.t_clk = orion5x_tclk;
d323ade1	613	orion5x_spi_plat_data.tclk = orion5x_tclk;
ebe35aff LB	614	orion5x_uart0_data[0].uartclk = orion5x_tclk;
ebe35aff LB	615	orion5x_uart1_data[0].uartclk = orion5x_tclk;
c67de5b3 TP	616
	617	/*
	618	* Setup Orion address map
	619	*/
9dd0b194	620	orion5x_setup_cpu_mbus_bridge();
ce72e36e LB	621
	622	/*
	623	* Don't issue "Wait for Interrupt" instruction if we are
	624	* running on D0 5281 silicon.
	625	*/
	626	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
	627	printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
	628	disable_hlt();
	629	}
c67de5b3	630	}
be73a347 GL	631
	632	/*
	633	* Many orion-based systems have buggy bootloader implementations.
	634	* This is a common fixup for bogus memory tags.
	635	*/
	636	void __init tag_fixup_mem32(struct machine_desc mdesc, struct tag t,
	637	char *from, struct meminfo meminfo)
	638	{
	639	for (; t->hdr.size; t = tag_next(t))
	640	if (t->hdr.tag == ATAG_MEM &&
	641	(!t->u.mem.size \|\| t->u.mem.size & ~PAGE_MASK \|\|
	642	t->u.mem.start & ~PAGE_MASK)) {
	643	printk(KERN_WARNING
	644	"Clearing invalid memory bank %dKB@0x%08x\n",
	645	t->u.mem.size / 1024, t->u.mem.start);
	646	t->hdr.tag = 0;
	647	}
	648	}