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Commit | Line | Data |
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585cf175 | 1 | /* |
9dd0b194 | 2 | * arch/arm/mach-orion5x/common.c |
585cf175 | 3 | * |
9dd0b194 | 4 | * Core functions for Marvell Orion 5x SoCs |
585cf175 TP |
5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
159ffb3a LB |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any | |
585cf175 TP |
10 | * warranty of any kind, whether express or implied. |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
ca26f7d3 TP |
15 | #include <linux/platform_device.h> |
16 | #include <linux/serial_8250.h> | |
83b6d822 | 17 | #include <linux/mbus.h> |
e07c9d85 | 18 | #include <linux/mv643xx_eth.h> |
144aa3db | 19 | #include <linux/mv643xx_i2c.h> |
15a32632 | 20 | #include <linux/ata_platform.h> |
585cf175 | 21 | #include <asm/page.h> |
be73a347 | 22 | #include <asm/setup.h> |
c67de5b3 | 23 | #include <asm/timex.h> |
be73a347 | 24 | #include <asm/mach/arch.h> |
585cf175 | 25 | #include <asm/mach/map.h> |
2bac1de2 | 26 | #include <asm/mach/time.h> |
f244baa3 | 27 | #include <asm/arch/hardware.h> |
9dd0b194 | 28 | #include <asm/arch/orion5x.h> |
705a7521 | 29 | #include <asm/plat-orion/ehci-orion.h> |
5d4294c5 | 30 | #include <asm/plat-orion/orion_nand.h> |
2bac1de2 | 31 | #include <asm/plat-orion/time.h> |
585cf175 TP |
32 | #include "common.h" |
33 | ||
34 | /***************************************************************************** | |
35 | * I/O Address Mapping | |
36 | ****************************************************************************/ | |
9dd0b194 | 37 | static struct map_desc orion5x_io_desc[] __initdata = { |
585cf175 | 38 | { |
9dd0b194 LB |
39 | .virtual = ORION5X_REGS_VIRT_BASE, |
40 | .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), | |
41 | .length = ORION5X_REGS_SIZE, | |
585cf175 TP |
42 | .type = MT_DEVICE |
43 | }, | |
44 | { | |
9dd0b194 LB |
45 | .virtual = ORION5X_PCIE_IO_VIRT_BASE, |
46 | .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), | |
47 | .length = ORION5X_PCIE_IO_SIZE, | |
585cf175 TP |
48 | .type = MT_DEVICE |
49 | }, | |
50 | { | |
9dd0b194 LB |
51 | .virtual = ORION5X_PCI_IO_VIRT_BASE, |
52 | .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), | |
53 | .length = ORION5X_PCI_IO_SIZE, | |
585cf175 TP |
54 | .type = MT_DEVICE |
55 | }, | |
56 | { | |
9dd0b194 LB |
57 | .virtual = ORION5X_PCIE_WA_VIRT_BASE, |
58 | .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), | |
59 | .length = ORION5X_PCIE_WA_SIZE, | |
585cf175 TP |
60 | .type = MT_DEVICE |
61 | }, | |
62 | }; | |
63 | ||
9dd0b194 | 64 | void __init orion5x_map_io(void) |
585cf175 | 65 | { |
9dd0b194 | 66 | iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); |
585cf175 | 67 | } |
c67de5b3 | 68 | |
ca26f7d3 TP |
69 | /***************************************************************************** |
70 | * UART | |
71 | ****************************************************************************/ | |
72 | ||
9dd0b194 | 73 | static struct resource orion5x_uart_resources[] = { |
ca26f7d3 | 74 | { |
7f74c2c7 LB |
75 | .start = UART0_PHYS_BASE, |
76 | .end = UART0_PHYS_BASE + 0xff, | |
ca26f7d3 TP |
77 | .flags = IORESOURCE_MEM, |
78 | }, | |
79 | { | |
9dd0b194 LB |
80 | .start = IRQ_ORION5X_UART0, |
81 | .end = IRQ_ORION5X_UART0, | |
ca26f7d3 TP |
82 | .flags = IORESOURCE_IRQ, |
83 | }, | |
84 | { | |
7f74c2c7 LB |
85 | .start = UART1_PHYS_BASE, |
86 | .end = UART1_PHYS_BASE + 0xff, | |
ca26f7d3 TP |
87 | .flags = IORESOURCE_MEM, |
88 | }, | |
89 | { | |
9dd0b194 LB |
90 | .start = IRQ_ORION5X_UART1, |
91 | .end = IRQ_ORION5X_UART1, | |
ca26f7d3 TP |
92 | .flags = IORESOURCE_IRQ, |
93 | }, | |
94 | }; | |
95 | ||
9dd0b194 | 96 | static struct plat_serial8250_port orion5x_uart_data[] = { |
ca26f7d3 | 97 | { |
7f74c2c7 LB |
98 | .mapbase = UART0_PHYS_BASE, |
99 | .membase = (char *)UART0_VIRT_BASE, | |
9dd0b194 | 100 | .irq = IRQ_ORION5X_UART0, |
ca26f7d3 TP |
101 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, |
102 | .iotype = UPIO_MEM, | |
103 | .regshift = 2, | |
9dd0b194 | 104 | .uartclk = ORION5X_TCLK, |
ca26f7d3 TP |
105 | }, |
106 | { | |
7f74c2c7 LB |
107 | .mapbase = UART1_PHYS_BASE, |
108 | .membase = (char *)UART1_VIRT_BASE, | |
9dd0b194 | 109 | .irq = IRQ_ORION5X_UART1, |
ca26f7d3 TP |
110 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, |
111 | .iotype = UPIO_MEM, | |
112 | .regshift = 2, | |
9dd0b194 | 113 | .uartclk = ORION5X_TCLK, |
ca26f7d3 TP |
114 | }, |
115 | { }, | |
116 | }; | |
117 | ||
9dd0b194 | 118 | static struct platform_device orion5x_uart = { |
ca26f7d3 TP |
119 | .name = "serial8250", |
120 | .id = PLAT8250_DEV_PLATFORM, | |
121 | .dev = { | |
9dd0b194 | 122 | .platform_data = orion5x_uart_data, |
ca26f7d3 | 123 | }, |
9dd0b194 LB |
124 | .resource = orion5x_uart_resources, |
125 | .num_resources = ARRAY_SIZE(orion5x_uart_resources), | |
ca26f7d3 TP |
126 | }; |
127 | ||
128 | /******************************************************************************* | |
129 | * USB Controller - 2 interfaces | |
130 | ******************************************************************************/ | |
131 | ||
9dd0b194 | 132 | static struct resource orion5x_ehci0_resources[] = { |
ca26f7d3 | 133 | { |
9dd0b194 | 134 | .start = ORION5X_USB0_PHYS_BASE, |
994cab84 | 135 | .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1, |
ca26f7d3 TP |
136 | .flags = IORESOURCE_MEM, |
137 | }, | |
138 | { | |
9dd0b194 LB |
139 | .start = IRQ_ORION5X_USB0_CTRL, |
140 | .end = IRQ_ORION5X_USB0_CTRL, | |
ca26f7d3 TP |
141 | .flags = IORESOURCE_IRQ, |
142 | }, | |
143 | }; | |
144 | ||
9dd0b194 | 145 | static struct resource orion5x_ehci1_resources[] = { |
ca26f7d3 | 146 | { |
9dd0b194 | 147 | .start = ORION5X_USB1_PHYS_BASE, |
994cab84 | 148 | .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1, |
ca26f7d3 TP |
149 | .flags = IORESOURCE_MEM, |
150 | }, | |
151 | { | |
9dd0b194 LB |
152 | .start = IRQ_ORION5X_USB1_CTRL, |
153 | .end = IRQ_ORION5X_USB1_CTRL, | |
ca26f7d3 TP |
154 | .flags = IORESOURCE_IRQ, |
155 | }, | |
156 | }; | |
157 | ||
9dd0b194 LB |
158 | static struct orion_ehci_data orion5x_ehci_data = { |
159 | .dram = &orion5x_mbus_dram_info, | |
92aecfa9 LB |
160 | }; |
161 | ||
ca26f7d3 TP |
162 | static u64 ehci_dmamask = 0xffffffffUL; |
163 | ||
9dd0b194 | 164 | static struct platform_device orion5x_ehci0 = { |
ca26f7d3 TP |
165 | .name = "orion-ehci", |
166 | .id = 0, | |
167 | .dev = { | |
168 | .dma_mask = &ehci_dmamask, | |
169 | .coherent_dma_mask = 0xffffffff, | |
9dd0b194 | 170 | .platform_data = &orion5x_ehci_data, |
ca26f7d3 | 171 | }, |
9dd0b194 LB |
172 | .resource = orion5x_ehci0_resources, |
173 | .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), | |
ca26f7d3 TP |
174 | }; |
175 | ||
9dd0b194 | 176 | static struct platform_device orion5x_ehci1 = { |
ca26f7d3 TP |
177 | .name = "orion-ehci", |
178 | .id = 1, | |
179 | .dev = { | |
180 | .dma_mask = &ehci_dmamask, | |
181 | .coherent_dma_mask = 0xffffffff, | |
9dd0b194 | 182 | .platform_data = &orion5x_ehci_data, |
ca26f7d3 | 183 | }, |
9dd0b194 LB |
184 | .resource = orion5x_ehci1_resources, |
185 | .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), | |
ca26f7d3 TP |
186 | }; |
187 | ||
e07c9d85 TP |
188 | /***************************************************************************** |
189 | * Gigabit Ethernet port | |
190 | * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) | |
191 | ****************************************************************************/ | |
192 | ||
d236f5a5 LB |
193 | struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = { |
194 | .dram = &orion5x_mbus_dram_info, | |
b8c15a60 | 195 | .t_clk = ORION5X_TCLK, |
d236f5a5 LB |
196 | }; |
197 | ||
9dd0b194 | 198 | static struct resource orion5x_eth_shared_resources[] = { |
e07c9d85 | 199 | { |
9dd0b194 LB |
200 | .start = ORION5X_ETH_PHYS_BASE + 0x2000, |
201 | .end = ORION5X_ETH_PHYS_BASE + 0x3fff, | |
e07c9d85 TP |
202 | .flags = IORESOURCE_MEM, |
203 | }, | |
204 | }; | |
205 | ||
9dd0b194 | 206 | static struct platform_device orion5x_eth_shared = { |
e07c9d85 TP |
207 | .name = MV643XX_ETH_SHARED_NAME, |
208 | .id = 0, | |
d236f5a5 LB |
209 | .dev = { |
210 | .platform_data = &orion5x_eth_shared_data, | |
211 | }, | |
e07c9d85 | 212 | .num_resources = 1, |
9dd0b194 | 213 | .resource = orion5x_eth_shared_resources, |
e07c9d85 TP |
214 | }; |
215 | ||
9dd0b194 | 216 | static struct resource orion5x_eth_resources[] = { |
e07c9d85 TP |
217 | { |
218 | .name = "eth irq", | |
9dd0b194 LB |
219 | .start = IRQ_ORION5X_ETH_SUM, |
220 | .end = IRQ_ORION5X_ETH_SUM, | |
e07c9d85 TP |
221 | .flags = IORESOURCE_IRQ, |
222 | } | |
223 | }; | |
224 | ||
9dd0b194 | 225 | static struct platform_device orion5x_eth = { |
e07c9d85 TP |
226 | .name = MV643XX_ETH_NAME, |
227 | .id = 0, | |
228 | .num_resources = 1, | |
9dd0b194 | 229 | .resource = orion5x_eth_resources, |
e07c9d85 TP |
230 | }; |
231 | ||
9dd0b194 | 232 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
e07c9d85 | 233 | { |
fa3959f4 | 234 | eth_data->shared = &orion5x_eth_shared; |
9dd0b194 | 235 | orion5x_eth.dev.platform_data = eth_data; |
fa3959f4 | 236 | |
9dd0b194 LB |
237 | platform_device_register(&orion5x_eth_shared); |
238 | platform_device_register(&orion5x_eth); | |
e07c9d85 TP |
239 | } |
240 | ||
144aa3db HVR |
241 | /***************************************************************************** |
242 | * I2C controller | |
243 | * (The Orion and Discovery (MV643xx) families share the same I2C controller) | |
244 | ****************************************************************************/ | |
245 | ||
9dd0b194 | 246 | static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { |
144aa3db HVR |
247 | .freq_m = 8, /* assumes 166 MHz TCLK */ |
248 | .freq_n = 3, | |
249 | .timeout = 1000, /* Default timeout of 1 second */ | |
250 | }; | |
251 | ||
9dd0b194 | 252 | static struct resource orion5x_i2c_resources[] = { |
144aa3db HVR |
253 | { |
254 | .name = "i2c base", | |
7f74c2c7 LB |
255 | .start = I2C_PHYS_BASE, |
256 | .end = I2C_PHYS_BASE + 0x20 -1, | |
144aa3db HVR |
257 | .flags = IORESOURCE_MEM, |
258 | }, | |
259 | { | |
260 | .name = "i2c irq", | |
9dd0b194 LB |
261 | .start = IRQ_ORION5X_I2C, |
262 | .end = IRQ_ORION5X_I2C, | |
144aa3db HVR |
263 | .flags = IORESOURCE_IRQ, |
264 | }, | |
265 | }; | |
266 | ||
9dd0b194 | 267 | static struct platform_device orion5x_i2c = { |
144aa3db HVR |
268 | .name = MV64XXX_I2C_CTLR_NAME, |
269 | .id = 0, | |
9dd0b194 LB |
270 | .num_resources = ARRAY_SIZE(orion5x_i2c_resources), |
271 | .resource = orion5x_i2c_resources, | |
144aa3db | 272 | .dev = { |
9dd0b194 | 273 | .platform_data = &orion5x_i2c_pdata, |
144aa3db HVR |
274 | }, |
275 | }; | |
276 | ||
f244baa3 SB |
277 | /***************************************************************************** |
278 | * Sata port | |
279 | ****************************************************************************/ | |
9dd0b194 | 280 | static struct resource orion5x_sata_resources[] = { |
f244baa3 SB |
281 | { |
282 | .name = "sata base", | |
9dd0b194 LB |
283 | .start = ORION5X_SATA_PHYS_BASE, |
284 | .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, | |
f244baa3 SB |
285 | .flags = IORESOURCE_MEM, |
286 | }, | |
287 | { | |
288 | .name = "sata irq", | |
9dd0b194 LB |
289 | .start = IRQ_ORION5X_SATA, |
290 | .end = IRQ_ORION5X_SATA, | |
f244baa3 SB |
291 | .flags = IORESOURCE_IRQ, |
292 | }, | |
293 | }; | |
294 | ||
9dd0b194 | 295 | static struct platform_device orion5x_sata = { |
f244baa3 SB |
296 | .name = "sata_mv", |
297 | .id = 0, | |
298 | .dev = { | |
299 | .coherent_dma_mask = 0xffffffff, | |
300 | }, | |
9dd0b194 LB |
301 | .num_resources = ARRAY_SIZE(orion5x_sata_resources), |
302 | .resource = orion5x_sata_resources, | |
f244baa3 SB |
303 | }; |
304 | ||
9dd0b194 | 305 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
f244baa3 | 306 | { |
9dd0b194 LB |
307 | sata_data->dram = &orion5x_mbus_dram_info; |
308 | orion5x_sata.dev.platform_data = sata_data; | |
309 | platform_device_register(&orion5x_sata); | |
f244baa3 SB |
310 | } |
311 | ||
2bac1de2 LB |
312 | /***************************************************************************** |
313 | * Time handling | |
314 | ****************************************************************************/ | |
315 | ||
9dd0b194 | 316 | static void orion5x_timer_init(void) |
2bac1de2 | 317 | { |
9dd0b194 | 318 | orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK); |
2bac1de2 LB |
319 | } |
320 | ||
9dd0b194 LB |
321 | struct sys_timer orion5x_timer = { |
322 | .init = orion5x_timer_init, | |
2bac1de2 LB |
323 | }; |
324 | ||
c67de5b3 TP |
325 | /***************************************************************************** |
326 | * General | |
327 | ****************************************************************************/ | |
328 | ||
329 | /* | |
b46926bb | 330 | * Identify device ID and rev from PCIe configuration header space '0'. |
c67de5b3 | 331 | */ |
9dd0b194 | 332 | static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) |
c67de5b3 | 333 | { |
9dd0b194 | 334 | orion5x_pcie_id(dev, rev); |
c67de5b3 TP |
335 | |
336 | if (*dev == MV88F5281_DEV_ID) { | |
337 | if (*rev == MV88F5281_REV_D2) { | |
338 | *dev_name = "MV88F5281-D2"; | |
339 | } else if (*rev == MV88F5281_REV_D1) { | |
340 | *dev_name = "MV88F5281-D1"; | |
341 | } else { | |
342 | *dev_name = "MV88F5281-Rev-Unsupported"; | |
343 | } | |
344 | } else if (*dev == MV88F5182_DEV_ID) { | |
345 | if (*rev == MV88F5182_REV_A2) { | |
346 | *dev_name = "MV88F5182-A2"; | |
347 | } else { | |
348 | *dev_name = "MV88F5182-Rev-Unsupported"; | |
349 | } | |
c9e3de94 HVR |
350 | } else if (*dev == MV88F5181_DEV_ID) { |
351 | if (*rev == MV88F5181_REV_B1) { | |
352 | *dev_name = "MV88F5181-Rev-B1"; | |
353 | } else { | |
354 | *dev_name = "MV88F5181-Rev-Unsupported"; | |
355 | } | |
c67de5b3 TP |
356 | } else { |
357 | *dev_name = "Device-Unknown"; | |
358 | } | |
359 | } | |
360 | ||
9dd0b194 | 361 | void __init orion5x_init(void) |
c67de5b3 TP |
362 | { |
363 | char *dev_name; | |
364 | u32 dev, rev; | |
365 | ||
9dd0b194 LB |
366 | orion5x_id(&dev, &rev, &dev_name); |
367 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK); | |
c67de5b3 TP |
368 | |
369 | /* | |
370 | * Setup Orion address map | |
371 | */ | |
9dd0b194 | 372 | orion5x_setup_cpu_mbus_bridge(); |
ca26f7d3 TP |
373 | |
374 | /* | |
159ffb3a | 375 | * Register devices. |
ca26f7d3 | 376 | */ |
9dd0b194 LB |
377 | platform_device_register(&orion5x_uart); |
378 | platform_device_register(&orion5x_ehci0); | |
ca26f7d3 | 379 | if (dev == MV88F5182_DEV_ID) |
9dd0b194 LB |
380 | platform_device_register(&orion5x_ehci1); |
381 | platform_device_register(&orion5x_i2c); | |
c67de5b3 | 382 | } |
be73a347 GL |
383 | |
384 | /* | |
385 | * Many orion-based systems have buggy bootloader implementations. | |
386 | * This is a common fixup for bogus memory tags. | |
387 | */ | |
388 | void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t, | |
389 | char **from, struct meminfo *meminfo) | |
390 | { | |
391 | for (; t->hdr.size; t = tag_next(t)) | |
392 | if (t->hdr.tag == ATAG_MEM && | |
393 | (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || | |
394 | t->u.mem.start & ~PAGE_MASK)) { | |
395 | printk(KERN_WARNING | |
396 | "Clearing invalid memory bank %dKB@0x%08x\n", | |
397 | t->u.mem.size / 1024, t->u.mem.start); | |
398 | t->hdr.tag = 0; | |
399 | } | |
400 | } |