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21278aea 1menuconfig ARCH_SIRF
cf82e0e4 2 bool "CSR SiRF" if ARCH_MULTI_V7
e7eda91f 3 select ARCH_HAS_RESET_CONTROLLER
cf82e0e4 4 select ARCH_REQUIRE_GPIOLIB
cf82e0e4 5 select GENERIC_IRQ_CHIP
ce816fa8 6 select NO_IOPORT_MAP
cf82e0e4
AB
7 select PINCTRL
8 select PINCTRL_SIRF
9 help
10 Support for CSR SiRFprimaII/Marco/Polo platforms
11
156a0997
BS
12if ARCH_SIRF
13
21278aea 14comment "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
d4fe49e5
BS
15
16config ARCH_ATLAS6
17 bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
18 default y
d4fe49e5
BS
19 select SIRF_IRQ
20 help
21 Support for CSR SiRFSoC ARM Cortex A9 Platform
156a0997
BS
22
23config ARCH_PRIMA2
24 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
25 default y
c1e3c119 26 select SIRF_IRQ
b1b3f49c 27 select ZONE_DMA
156a0997
BS
28 help
29 Support for CSR SiRFSoC ARM Cortex A9 Platform
30
4898de3d
BS
31config ARCH_MARCO
32 bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
33 default y
34 select ARM_GIC
4c3ffffd 35 select HAVE_ARM_SCU if SMP
cb0c480a 36 select SMP_ON_UP if SMP
4898de3d
BS
37 help
38 Support for CSR SiRFSoC ARM Cortex A9 Platform
39
c1e3c119
BS
40config SIRF_IRQ
41 bool
42
156a0997 43endif