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Commit | Line | Data |
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ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
21278aea | 2 | menuconfig ARCH_SIRF |
e3246542 MY |
3 | bool "CSR SiRF" |
4 | depends on ARCH_MULTI_V7 | |
e7eda91f | 5 | select ARCH_HAS_RESET_CONTROLLER |
ef2b1d77 | 6 | select RESET_CONTROLLER |
cf82e0e4 | 7 | select GENERIC_IRQ_CHIP |
5c34a4e8 | 8 | select GPIOLIB |
ce816fa8 | 9 | select NO_IOPORT_MAP |
b1999477 | 10 | select REGMAP |
cf82e0e4 AB |
11 | select PINCTRL |
12 | select PINCTRL_SIRF | |
13 | help | |
14 | Support for CSR SiRFprimaII/Marco/Polo platforms | |
15 | ||
156a0997 BS |
16 | if ARCH_SIRF |
17 | ||
4cba0585 | 18 | comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features" |
d4fe49e5 BS |
19 | |
20 | config ARCH_ATLAS6 | |
21 | bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform" | |
22 | default y | |
d4fe49e5 BS |
23 | select SIRF_IRQ |
24 | help | |
25 | Support for CSR SiRFSoC ARM Cortex A9 Platform | |
156a0997 | 26 | |
4cba0585 ZS |
27 | config ARCH_ATLAS7 |
28 | bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform" | |
29 | default y | |
30 | select ARM_GIC | |
b56d5d21 | 31 | select ATLAS7_TIMER |
4cba0585 ZS |
32 | select HAVE_ARM_SCU if SMP |
33 | select HAVE_SMP | |
4cba0585 ZS |
34 | help |
35 | Support for CSR SiRFSoC ARM Cortex A7 Platform | |
36 | ||
156a0997 BS |
37 | config ARCH_PRIMA2 |
38 | bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" | |
39 | default y | |
c1e3c119 | 40 | select SIRF_IRQ |
b1b3f49c | 41 | select ZONE_DMA |
f3550d49 | 42 | select PRIMA2_TIMER |
156a0997 BS |
43 | help |
44 | Support for CSR SiRFSoC ARM Cortex A9 Platform | |
45 | ||
c1e3c119 BS |
46 | config SIRF_IRQ |
47 | bool | |
48 | ||
156a0997 | 49 | endif |