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9e2697ff | 1 | /* |
0d1bde9e | 2 | * linux/arch/arm/mach-pxa/cpufreq-pxa2xx.c |
9e2697ff RK |
3 | * |
4 | * Copyright (C) 2002,2003 Intrinsyc Software | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | * History: | |
21 | * 31-Jul-2002 : Initial version [FB] | |
22 | * 29-Jan-2003 : added PXA255 support [FB] | |
23 | * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.) | |
24 | * | |
25 | * Note: | |
26 | * This driver may change the memory bus clock rate, but will not do any | |
27 | * platform specific access timing changes... for example if you have flash | |
28 | * memory connected to CS0, you will need to register a platform specific | |
29 | * notifier which will adjust the memory access strobes to maintain a | |
30 | * minimum strobe width. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/sched.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/cpufreq.h> | |
39 | ||
a09e64fb RK |
40 | #include <mach/hardware.h> |
41 | #include <mach/pxa-regs.h> | |
42 | #include <mach/pxa2xx-regs.h> | |
9e2697ff RK |
43 | |
44 | #ifdef DEBUG | |
45 | static unsigned int freq_debug; | |
c710e39c | 46 | module_param(freq_debug, uint, 0); |
9e2697ff RK |
47 | MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0"); |
48 | #else | |
49 | #define freq_debug 0 | |
50 | #endif | |
51 | ||
592eb999 RJ |
52 | static unsigned int pxa27x_maxfreq; |
53 | module_param(pxa27x_maxfreq, uint, 0); | |
54 | MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz" | |
55 | "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)"); | |
56 | ||
9e2697ff RK |
57 | typedef struct { |
58 | unsigned int khz; | |
59 | unsigned int membus; | |
60 | unsigned int cccr; | |
61 | unsigned int div2; | |
592eb999 | 62 | unsigned int cclkcfg; |
9e2697ff RK |
63 | } pxa_freqs_t; |
64 | ||
65 | /* Define the refresh period in mSec for the SDRAM and the number of rows */ | |
3679389b RJ |
66 | #define SDRAM_TREF 64 /* standard 64ms SDRAM */ |
67 | #define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */ | |
9e2697ff | 68 | |
3679389b RJ |
69 | #define CCLKCFG_TURBO 0x1 |
70 | #define CCLKCFG_FCS 0x2 | |
592eb999 RJ |
71 | #define CCLKCFG_HALFTURBO 0x4 |
72 | #define CCLKCFG_FASTBUS 0x8 | |
3679389b RJ |
73 | #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) |
74 | #define MDREFR_DRI_MASK 0xFFF | |
9e2697ff | 75 | |
592eb999 RJ |
76 | /* |
77 | * PXA255 definitions | |
78 | */ | |
9e2697ff | 79 | /* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */ |
592eb999 RJ |
80 | #define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS |
81 | ||
9e2697ff RK |
82 | static pxa_freqs_t pxa255_run_freqs[] = |
83 | { | |
592eb999 RJ |
84 | /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */ |
85 | { 99500, 99500, 0x121, 1, CCLKCFG}, /* 99, 99, 50, 50 */ | |
86 | {132700, 132700, 0x123, 1, CCLKCFG}, /* 133, 133, 66, 66 */ | |
87 | {199100, 99500, 0x141, 0, CCLKCFG}, /* 199, 199, 99, 99 */ | |
88 | {265400, 132700, 0x143, 1, CCLKCFG}, /* 265, 265, 133, 66 */ | |
89 | {331800, 165900, 0x145, 1, CCLKCFG}, /* 331, 331, 166, 83 */ | |
90 | {398100, 99500, 0x161, 0, CCLKCFG}, /* 398, 398, 196, 99 */ | |
9e2697ff | 91 | }; |
9e2697ff RK |
92 | |
93 | /* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */ | |
94 | static pxa_freqs_t pxa255_turbo_freqs[] = | |
95 | { | |
592eb999 RJ |
96 | /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */ |
97 | { 99500, 99500, 0x121, 1, CCLKCFG}, /* 99, 99, 50, 50 */ | |
98 | {199100, 99500, 0x221, 0, CCLKCFG}, /* 99, 199, 50, 99 */ | |
99 | {298500, 99500, 0x321, 0, CCLKCFG}, /* 99, 287, 50, 99 */ | |
100 | {298600, 99500, 0x1c1, 0, CCLKCFG}, /* 199, 287, 99, 99 */ | |
101 | {398100, 99500, 0x241, 0, CCLKCFG}, /* 199, 398, 99, 99 */ | |
9e2697ff | 102 | }; |
9e2697ff | 103 | |
592eb999 RJ |
104 | #define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs) |
105 | #define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs) | |
106 | ||
107 | static struct cpufreq_frequency_table | |
108 | pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1]; | |
3679389b | 109 | static struct cpufreq_frequency_table |
592eb999 RJ |
110 | pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1]; |
111 | ||
112 | /* | |
113 | * PXA270 definitions | |
114 | * | |
115 | * For the PXA27x: | |
116 | * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG. | |
117 | * | |
118 | * A = 0 => memory controller clock from table 3-7, | |
119 | * A = 1 => memory controller clock = system bus clock | |
120 | * Run mode frequency = 13 MHz * L | |
121 | * Turbo mode frequency = 13 MHz * L * N | |
122 | * System bus frequency = 13 MHz * L / (B + 1) | |
123 | * | |
124 | * In CCCR: | |
125 | * A = 1 | |
126 | * L = 16 oscillator to run mode ratio | |
127 | * 2N = 6 2 * (turbo mode to run mode ratio) | |
128 | * | |
129 | * In CCLKCFG: | |
130 | * B = 1 Fast bus mode | |
131 | * HT = 0 Half-Turbo mode | |
132 | * T = 1 Turbo mode | |
133 | * | |
134 | * For now, just support some of the combinations in table 3-7 of | |
135 | * PXA27x Processor Family Developer's Manual to simplify frequency | |
136 | * change sequences. | |
137 | */ | |
138 | #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L) | |
139 | #define CCLKCFG2(B, HT, T) \ | |
140 | (CCLKCFG_FCS | \ | |
141 | ((B) ? CCLKCFG_FASTBUS : 0) | \ | |
142 | ((HT) ? CCLKCFG_HALFTURBO : 0) | \ | |
143 | ((T) ? CCLKCFG_TURBO : 0)) | |
144 | ||
145 | static pxa_freqs_t pxa27x_freqs[] = { | |
146 | {104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1)}, | |
147 | {156000, 104000, PXA27x_CCCR(1, 8, 6), 0, CCLKCFG2(1, 1, 1)}, | |
148 | {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1)}, | |
149 | {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1)}, | |
150 | {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1)}, | |
151 | {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1)}, | |
152 | {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1)} | |
153 | }; | |
154 | ||
155 | #define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs) | |
156 | static struct cpufreq_frequency_table | |
157 | pxa27x_freq_table[NUM_PXA27x_FREQS+1]; | |
9e2697ff RK |
158 | |
159 | extern unsigned get_clk_frequency_khz(int info); | |
160 | ||
592eb999 RJ |
161 | static void find_freq_tables(struct cpufreq_policy *policy, |
162 | struct cpufreq_frequency_table **freq_table, | |
163 | pxa_freqs_t **pxa_freqs) | |
164 | { | |
165 | if (cpu_is_pxa25x()) { | |
166 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { | |
167 | *pxa_freqs = pxa255_run_freqs; | |
168 | *freq_table = pxa255_run_freq_table; | |
169 | } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) { | |
170 | *pxa_freqs = pxa255_turbo_freqs; | |
171 | *freq_table = pxa255_turbo_freq_table; | |
172 | } else { | |
173 | printk("CPU PXA: Unknown policy found. " | |
174 | "Using CPUFREQ_POLICY_PERFORMANCE\n"); | |
175 | *pxa_freqs = pxa255_run_freqs; | |
176 | *freq_table = pxa255_run_freq_table; | |
177 | } | |
178 | } | |
179 | if (cpu_is_pxa27x()) { | |
180 | *pxa_freqs = pxa27x_freqs; | |
181 | *freq_table = pxa27x_freq_table; | |
182 | } | |
183 | } | |
184 | ||
185 | static void pxa27x_guess_max_freq(void) | |
186 | { | |
187 | if (!pxa27x_maxfreq) { | |
188 | pxa27x_maxfreq = 416000; | |
189 | printk(KERN_INFO "PXA CPU 27x max frequency not defined " | |
190 | "(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n", | |
191 | pxa27x_maxfreq); | |
192 | } else { | |
193 | pxa27x_maxfreq *= 1000; | |
194 | } | |
195 | } | |
196 | ||
197 | static u32 mdrefr_dri(unsigned int freq) | |
198 | { | |
199 | u32 dri = 0; | |
200 | ||
201 | if (cpu_is_pxa25x()) | |
202 | dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS * 32)); | |
203 | if (cpu_is_pxa27x()) | |
204 | dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS - 31)) / 32; | |
205 | return dri; | |
206 | } | |
207 | ||
9e2697ff RK |
208 | /* find a valid frequency point */ |
209 | static int pxa_verify_policy(struct cpufreq_policy *policy) | |
210 | { | |
211 | struct cpufreq_frequency_table *pxa_freqs_table; | |
592eb999 | 212 | pxa_freqs_t *pxa_freqs; |
9e2697ff RK |
213 | int ret; |
214 | ||
592eb999 | 215 | find_freq_tables(policy, &pxa_freqs_table, &pxa_freqs); |
9e2697ff RK |
216 | ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table); |
217 | ||
218 | if (freq_debug) | |
219 | pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n", | |
3679389b | 220 | policy->min, policy->max); |
9e2697ff RK |
221 | |
222 | return ret; | |
223 | } | |
224 | ||
592eb999 RJ |
225 | static unsigned int pxa_cpufreq_get(unsigned int cpu) |
226 | { | |
227 | return get_clk_frequency_khz(0); | |
228 | } | |
229 | ||
9e2697ff | 230 | static int pxa_set_target(struct cpufreq_policy *policy, |
3679389b RJ |
231 | unsigned int target_freq, |
232 | unsigned int relation) | |
9e2697ff RK |
233 | { |
234 | struct cpufreq_frequency_table *pxa_freqs_table; | |
235 | pxa_freqs_t *pxa_freq_settings; | |
236 | struct cpufreq_freqs freqs; | |
ea833f0b | 237 | unsigned int idx; |
9e2697ff | 238 | unsigned long flags; |
592eb999 RJ |
239 | unsigned int new_freq_cpu, new_freq_mem; |
240 | unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg; | |
9e2697ff RK |
241 | |
242 | /* Get the current policy */ | |
592eb999 | 243 | find_freq_tables(policy, &pxa_freqs_table, &pxa_freq_settings); |
9e2697ff RK |
244 | |
245 | /* Lookup the next frequency */ | |
246 | if (cpufreq_frequency_table_target(policy, pxa_freqs_table, | |
3679389b | 247 | target_freq, relation, &idx)) { |
9e2697ff RK |
248 | return -EINVAL; |
249 | } | |
250 | ||
592eb999 RJ |
251 | new_freq_cpu = pxa_freq_settings[idx].khz; |
252 | new_freq_mem = pxa_freq_settings[idx].membus; | |
9e2697ff | 253 | freqs.old = policy->cur; |
592eb999 | 254 | freqs.new = new_freq_cpu; |
9e2697ff RK |
255 | freqs.cpu = policy->cpu; |
256 | ||
257 | if (freq_debug) | |
3679389b RJ |
258 | pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, " |
259 | "(SDRAM %d Mhz)\n", | |
260 | freqs.new / 1000, (pxa_freq_settings[idx].div2) ? | |
592eb999 | 261 | (new_freq_mem / 2000) : (new_freq_mem / 1000)); |
9e2697ff RK |
262 | |
263 | /* | |
264 | * Tell everyone what we're about to do... | |
265 | * you should add a notify client with any platform specific | |
266 | * Vcc changing capability | |
267 | */ | |
268 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
269 | ||
270 | /* Calculate the next MDREFR. If we're slowing down the SDRAM clock | |
3679389b RJ |
271 | * we need to preset the smaller DRI before the change. If we're |
272 | * speeding up we need to set the larger DRI value after the change. | |
9e2697ff RK |
273 | */ |
274 | preset_mdrefr = postset_mdrefr = MDREFR; | |
592eb999 RJ |
275 | if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) { |
276 | preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK); | |
277 | preset_mdrefr |= mdrefr_dri(new_freq_mem); | |
9e2697ff | 278 | } |
592eb999 RJ |
279 | postset_mdrefr = |
280 | (postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem); | |
9e2697ff RK |
281 | |
282 | /* If we're dividing the memory clock by two for the SDRAM clock, this | |
283 | * must be set prior to the change. Clearing the divide must be done | |
284 | * after the change. | |
285 | */ | |
286 | if (pxa_freq_settings[idx].div2) { | |
287 | preset_mdrefr |= MDREFR_DB2_MASK; | |
288 | postset_mdrefr |= MDREFR_DB2_MASK; | |
289 | } else { | |
290 | postset_mdrefr &= ~MDREFR_DB2_MASK; | |
291 | } | |
292 | ||
293 | local_irq_save(flags); | |
294 | ||
592eb999 | 295 | /* Set new the CCCR and prepare CCLKCFG */ |
9e2697ff | 296 | CCCR = pxa_freq_settings[idx].cccr; |
592eb999 | 297 | cclkcfg = pxa_freq_settings[idx].cclkcfg; |
9e2697ff RK |
298 | |
299 | asm volatile(" \n\ | |
300 | ldr r4, [%1] /* load MDREFR */ \n\ | |
301 | b 2f \n\ | |
3679389b | 302 | .align 5 \n\ |
9e2697ff | 303 | 1: \n\ |
592eb999 | 304 | str %3, [%1] /* preset the MDREFR */ \n\ |
9e2697ff | 305 | mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\ |
592eb999 | 306 | str %4, [%1] /* postset the MDREFR */ \n\ |
9e2697ff RK |
307 | \n\ |
308 | b 3f \n\ | |
309 | 2: b 1b \n\ | |
310 | 3: nop \n\ | |
311 | " | |
3679389b | 312 | : "=&r" (unused) |
592eb999 RJ |
313 | : "r" (&MDREFR), "r" (cclkcfg), |
314 | "r" (preset_mdrefr), "r" (postset_mdrefr) | |
3679389b | 315 | : "r4", "r5"); |
9e2697ff RK |
316 | local_irq_restore(flags); |
317 | ||
318 | /* | |
319 | * Tell everyone what we've just done... | |
320 | * you should add a notify client with any platform specific | |
321 | * SDRAM refresh timer adjustments | |
322 | */ | |
323 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
592eb999 | 328 | static __init int pxa_cpufreq_init(struct cpufreq_policy *policy) |
9e2697ff RK |
329 | { |
330 | int i; | |
592eb999 RJ |
331 | unsigned int freq; |
332 | ||
333 | /* try to guess pxa27x cpu */ | |
334 | if (cpu_is_pxa27x()) | |
335 | pxa27x_guess_max_freq(); | |
9e2697ff RK |
336 | |
337 | /* set default policy and cpuinfo */ | |
9e2697ff | 338 | policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ |
3679389b | 339 | policy->cur = get_clk_frequency_khz(0); /* current freq */ |
9e2697ff RK |
340 | policy->min = policy->max = policy->cur; |
341 | ||
592eb999 RJ |
342 | /* Generate pxa25x the run cpufreq_frequency_table struct */ |
343 | for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) { | |
9e2697ff RK |
344 | pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz; |
345 | pxa255_run_freq_table[i].index = i; | |
346 | } | |
9e2697ff | 347 | pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END; |
592eb999 RJ |
348 | |
349 | /* Generate pxa25x the turbo cpufreq_frequency_table struct */ | |
350 | for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) { | |
3679389b RJ |
351 | pxa255_turbo_freq_table[i].frequency = |
352 | pxa255_turbo_freqs[i].khz; | |
9e2697ff RK |
353 | pxa255_turbo_freq_table[i].index = i; |
354 | } | |
355 | pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END; | |
356 | ||
592eb999 RJ |
357 | /* Generate the pxa27x cpufreq_frequency_table struct */ |
358 | for (i = 0; i < NUM_PXA27x_FREQS; i++) { | |
359 | freq = pxa27x_freqs[i].khz; | |
360 | if (freq > pxa27x_maxfreq) | |
361 | break; | |
362 | pxa27x_freq_table[i].frequency = freq; | |
363 | pxa27x_freq_table[i].index = i; | |
364 | } | |
365 | pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END; | |
366 | ||
367 | /* | |
368 | * Set the policy's minimum and maximum frequencies from the tables | |
369 | * just constructed. This sets cpuinfo.mxx_freq, min and max. | |
370 | */ | |
371 | if (cpu_is_pxa25x()) | |
372 | cpufreq_frequency_table_cpuinfo(policy, pxa255_run_freq_table); | |
373 | else if (cpu_is_pxa27x()) | |
374 | cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table); | |
375 | ||
9e2697ff RK |
376 | printk(KERN_INFO "PXA CPU frequency change support initialized\n"); |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | static struct cpufreq_driver pxa_cpufreq_driver = { | |
382 | .verify = pxa_verify_policy, | |
383 | .target = pxa_set_target, | |
384 | .init = pxa_cpufreq_init, | |
ea833f0b | 385 | .get = pxa_cpufreq_get, |
592eb999 | 386 | .name = "PXA2xx", |
9e2697ff RK |
387 | }; |
388 | ||
389 | static int __init pxa_cpu_init(void) | |
390 | { | |
391 | int ret = -ENODEV; | |
592eb999 | 392 | if (cpu_is_pxa25x() || cpu_is_pxa27x()) |
9e2697ff RK |
393 | ret = cpufreq_register_driver(&pxa_cpufreq_driver); |
394 | return ret; | |
395 | } | |
396 | ||
397 | static void __exit pxa_cpu_exit(void) | |
398 | { | |
592eb999 | 399 | cpufreq_unregister_driver(&pxa_cpufreq_driver); |
9e2697ff RK |
400 | } |
401 | ||
402 | ||
3679389b RJ |
403 | MODULE_AUTHOR("Intrinsyc Software Inc."); |
404 | MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture"); | |
9e2697ff RK |
405 | MODULE_LICENSE("GPL"); |
406 | module_init(pxa_cpu_init); | |
407 | module_exit(pxa_cpu_exit); |