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9e2697ff | 1 | /* |
0d1bde9e | 2 | * linux/arch/arm/mach-pxa/cpufreq-pxa2xx.c |
9e2697ff RK |
3 | * |
4 | * Copyright (C) 2002,2003 Intrinsyc Software | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | * History: | |
21 | * 31-Jul-2002 : Initial version [FB] | |
22 | * 29-Jan-2003 : added PXA255 support [FB] | |
23 | * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.) | |
24 | * | |
25 | * Note: | |
26 | * This driver may change the memory bus clock rate, but will not do any | |
27 | * platform specific access timing changes... for example if you have flash | |
28 | * memory connected to CS0, you will need to register a platform specific | |
29 | * notifier which will adjust the memory access strobes to maintain a | |
30 | * minimum strobe width. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/sched.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/cpufreq.h> | |
39 | ||
a09e64fb RK |
40 | #include <mach/hardware.h> |
41 | #include <mach/pxa-regs.h> | |
42 | #include <mach/pxa2xx-regs.h> | |
9e2697ff RK |
43 | |
44 | #ifdef DEBUG | |
45 | static unsigned int freq_debug; | |
c710e39c | 46 | module_param(freq_debug, uint, 0); |
9e2697ff RK |
47 | MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0"); |
48 | #else | |
49 | #define freq_debug 0 | |
50 | #endif | |
51 | ||
592eb999 RJ |
52 | static unsigned int pxa27x_maxfreq; |
53 | module_param(pxa27x_maxfreq, uint, 0); | |
54 | MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz" | |
55 | "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)"); | |
56 | ||
9e2697ff RK |
57 | typedef struct { |
58 | unsigned int khz; | |
59 | unsigned int membus; | |
60 | unsigned int cccr; | |
61 | unsigned int div2; | |
592eb999 | 62 | unsigned int cclkcfg; |
9e2697ff RK |
63 | } pxa_freqs_t; |
64 | ||
65 | /* Define the refresh period in mSec for the SDRAM and the number of rows */ | |
3679389b | 66 | #define SDRAM_TREF 64 /* standard 64ms SDRAM */ |
a10c287d | 67 | static unsigned int sdram_rows; |
9e2697ff | 68 | |
3679389b RJ |
69 | #define CCLKCFG_TURBO 0x1 |
70 | #define CCLKCFG_FCS 0x2 | |
592eb999 RJ |
71 | #define CCLKCFG_HALFTURBO 0x4 |
72 | #define CCLKCFG_FASTBUS 0x8 | |
3679389b RJ |
73 | #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) |
74 | #define MDREFR_DRI_MASK 0xFFF | |
9e2697ff | 75 | |
a10c287d PZ |
76 | #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3) |
77 | #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3) | |
78 | ||
592eb999 RJ |
79 | /* |
80 | * PXA255 definitions | |
81 | */ | |
9e2697ff | 82 | /* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */ |
592eb999 RJ |
83 | #define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS |
84 | ||
9e2697ff RK |
85 | static pxa_freqs_t pxa255_run_freqs[] = |
86 | { | |
592eb999 RJ |
87 | /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */ |
88 | { 99500, 99500, 0x121, 1, CCLKCFG}, /* 99, 99, 50, 50 */ | |
89 | {132700, 132700, 0x123, 1, CCLKCFG}, /* 133, 133, 66, 66 */ | |
90 | {199100, 99500, 0x141, 0, CCLKCFG}, /* 199, 199, 99, 99 */ | |
91 | {265400, 132700, 0x143, 1, CCLKCFG}, /* 265, 265, 133, 66 */ | |
92 | {331800, 165900, 0x145, 1, CCLKCFG}, /* 331, 331, 166, 83 */ | |
93 | {398100, 99500, 0x161, 0, CCLKCFG}, /* 398, 398, 196, 99 */ | |
9e2697ff | 94 | }; |
9e2697ff RK |
95 | |
96 | /* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */ | |
97 | static pxa_freqs_t pxa255_turbo_freqs[] = | |
98 | { | |
592eb999 RJ |
99 | /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */ |
100 | { 99500, 99500, 0x121, 1, CCLKCFG}, /* 99, 99, 50, 50 */ | |
101 | {199100, 99500, 0x221, 0, CCLKCFG}, /* 99, 199, 50, 99 */ | |
102 | {298500, 99500, 0x321, 0, CCLKCFG}, /* 99, 287, 50, 99 */ | |
103 | {298600, 99500, 0x1c1, 0, CCLKCFG}, /* 199, 287, 99, 99 */ | |
104 | {398100, 99500, 0x241, 0, CCLKCFG}, /* 199, 398, 99, 99 */ | |
9e2697ff | 105 | }; |
9e2697ff | 106 | |
592eb999 RJ |
107 | #define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs) |
108 | #define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs) | |
109 | ||
110 | static struct cpufreq_frequency_table | |
111 | pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1]; | |
3679389b | 112 | static struct cpufreq_frequency_table |
592eb999 RJ |
113 | pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1]; |
114 | ||
65587f7d MZ |
115 | static unsigned int pxa255_turbo_table; |
116 | module_param(pxa255_turbo_table, uint, 0); | |
117 | MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)"); | |
118 | ||
592eb999 RJ |
119 | /* |
120 | * PXA270 definitions | |
121 | * | |
122 | * For the PXA27x: | |
123 | * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG. | |
124 | * | |
125 | * A = 0 => memory controller clock from table 3-7, | |
126 | * A = 1 => memory controller clock = system bus clock | |
127 | * Run mode frequency = 13 MHz * L | |
128 | * Turbo mode frequency = 13 MHz * L * N | |
129 | * System bus frequency = 13 MHz * L / (B + 1) | |
130 | * | |
131 | * In CCCR: | |
132 | * A = 1 | |
133 | * L = 16 oscillator to run mode ratio | |
134 | * 2N = 6 2 * (turbo mode to run mode ratio) | |
135 | * | |
136 | * In CCLKCFG: | |
137 | * B = 1 Fast bus mode | |
138 | * HT = 0 Half-Turbo mode | |
139 | * T = 1 Turbo mode | |
140 | * | |
141 | * For now, just support some of the combinations in table 3-7 of | |
142 | * PXA27x Processor Family Developer's Manual to simplify frequency | |
143 | * change sequences. | |
144 | */ | |
145 | #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L) | |
146 | #define CCLKCFG2(B, HT, T) \ | |
147 | (CCLKCFG_FCS | \ | |
148 | ((B) ? CCLKCFG_FASTBUS : 0) | \ | |
149 | ((HT) ? CCLKCFG_HALFTURBO : 0) | \ | |
150 | ((T) ? CCLKCFG_TURBO : 0)) | |
151 | ||
152 | static pxa_freqs_t pxa27x_freqs[] = { | |
153 | {104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1)}, | |
154 | {156000, 104000, PXA27x_CCCR(1, 8, 6), 0, CCLKCFG2(1, 1, 1)}, | |
155 | {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1)}, | |
156 | {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1)}, | |
157 | {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1)}, | |
158 | {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1)}, | |
159 | {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1)} | |
160 | }; | |
161 | ||
162 | #define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs) | |
163 | static struct cpufreq_frequency_table | |
164 | pxa27x_freq_table[NUM_PXA27x_FREQS+1]; | |
9e2697ff RK |
165 | |
166 | extern unsigned get_clk_frequency_khz(int info); | |
167 | ||
65587f7d | 168 | static void find_freq_tables(struct cpufreq_frequency_table **freq_table, |
592eb999 RJ |
169 | pxa_freqs_t **pxa_freqs) |
170 | { | |
171 | if (cpu_is_pxa25x()) { | |
65587f7d | 172 | if (!pxa255_turbo_table) { |
592eb999 RJ |
173 | *pxa_freqs = pxa255_run_freqs; |
174 | *freq_table = pxa255_run_freq_table; | |
65587f7d | 175 | } else { |
592eb999 RJ |
176 | *pxa_freqs = pxa255_turbo_freqs; |
177 | *freq_table = pxa255_turbo_freq_table; | |
592eb999 RJ |
178 | } |
179 | } | |
180 | if (cpu_is_pxa27x()) { | |
181 | *pxa_freqs = pxa27x_freqs; | |
182 | *freq_table = pxa27x_freq_table; | |
183 | } | |
184 | } | |
185 | ||
186 | static void pxa27x_guess_max_freq(void) | |
187 | { | |
188 | if (!pxa27x_maxfreq) { | |
189 | pxa27x_maxfreq = 416000; | |
190 | printk(KERN_INFO "PXA CPU 27x max frequency not defined " | |
191 | "(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n", | |
192 | pxa27x_maxfreq); | |
193 | } else { | |
194 | pxa27x_maxfreq *= 1000; | |
195 | } | |
196 | } | |
197 | ||
a10c287d PZ |
198 | static void init_sdram_rows(void) |
199 | { | |
200 | uint32_t mdcnfg = MDCNFG; | |
201 | unsigned int drac2 = 0, drac0 = 0; | |
202 | ||
203 | if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3)) | |
204 | drac2 = MDCNFG_DRAC2(mdcnfg); | |
205 | ||
206 | if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1)) | |
207 | drac0 = MDCNFG_DRAC0(mdcnfg); | |
208 | ||
209 | sdram_rows = 1 << (11 + max(drac0, drac2)); | |
210 | } | |
211 | ||
592eb999 RJ |
212 | static u32 mdrefr_dri(unsigned int freq) |
213 | { | |
214 | u32 dri = 0; | |
215 | ||
216 | if (cpu_is_pxa25x()) | |
a10c287d | 217 | dri = ((freq * SDRAM_TREF) / (sdram_rows * 32)); |
592eb999 | 218 | if (cpu_is_pxa27x()) |
a10c287d | 219 | dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32; |
592eb999 RJ |
220 | return dri; |
221 | } | |
222 | ||
9e2697ff RK |
223 | /* find a valid frequency point */ |
224 | static int pxa_verify_policy(struct cpufreq_policy *policy) | |
225 | { | |
226 | struct cpufreq_frequency_table *pxa_freqs_table; | |
592eb999 | 227 | pxa_freqs_t *pxa_freqs; |
9e2697ff RK |
228 | int ret; |
229 | ||
65587f7d | 230 | find_freq_tables(&pxa_freqs_table, &pxa_freqs); |
9e2697ff RK |
231 | ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table); |
232 | ||
233 | if (freq_debug) | |
234 | pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n", | |
3679389b | 235 | policy->min, policy->max); |
9e2697ff RK |
236 | |
237 | return ret; | |
238 | } | |
239 | ||
592eb999 RJ |
240 | static unsigned int pxa_cpufreq_get(unsigned int cpu) |
241 | { | |
242 | return get_clk_frequency_khz(0); | |
243 | } | |
244 | ||
9e2697ff | 245 | static int pxa_set_target(struct cpufreq_policy *policy, |
3679389b RJ |
246 | unsigned int target_freq, |
247 | unsigned int relation) | |
9e2697ff RK |
248 | { |
249 | struct cpufreq_frequency_table *pxa_freqs_table; | |
250 | pxa_freqs_t *pxa_freq_settings; | |
251 | struct cpufreq_freqs freqs; | |
ea833f0b | 252 | unsigned int idx; |
9e2697ff | 253 | unsigned long flags; |
592eb999 RJ |
254 | unsigned int new_freq_cpu, new_freq_mem; |
255 | unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg; | |
9e2697ff RK |
256 | |
257 | /* Get the current policy */ | |
65587f7d | 258 | find_freq_tables(&pxa_freqs_table, &pxa_freq_settings); |
9e2697ff RK |
259 | |
260 | /* Lookup the next frequency */ | |
261 | if (cpufreq_frequency_table_target(policy, pxa_freqs_table, | |
3679389b | 262 | target_freq, relation, &idx)) { |
9e2697ff RK |
263 | return -EINVAL; |
264 | } | |
265 | ||
592eb999 RJ |
266 | new_freq_cpu = pxa_freq_settings[idx].khz; |
267 | new_freq_mem = pxa_freq_settings[idx].membus; | |
9e2697ff | 268 | freqs.old = policy->cur; |
592eb999 | 269 | freqs.new = new_freq_cpu; |
9e2697ff RK |
270 | freqs.cpu = policy->cpu; |
271 | ||
272 | if (freq_debug) | |
3679389b RJ |
273 | pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, " |
274 | "(SDRAM %d Mhz)\n", | |
275 | freqs.new / 1000, (pxa_freq_settings[idx].div2) ? | |
592eb999 | 276 | (new_freq_mem / 2000) : (new_freq_mem / 1000)); |
9e2697ff RK |
277 | |
278 | /* | |
279 | * Tell everyone what we're about to do... | |
280 | * you should add a notify client with any platform specific | |
281 | * Vcc changing capability | |
282 | */ | |
283 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
284 | ||
285 | /* Calculate the next MDREFR. If we're slowing down the SDRAM clock | |
3679389b RJ |
286 | * we need to preset the smaller DRI before the change. If we're |
287 | * speeding up we need to set the larger DRI value after the change. | |
9e2697ff RK |
288 | */ |
289 | preset_mdrefr = postset_mdrefr = MDREFR; | |
592eb999 RJ |
290 | if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) { |
291 | preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK); | |
292 | preset_mdrefr |= mdrefr_dri(new_freq_mem); | |
9e2697ff | 293 | } |
592eb999 RJ |
294 | postset_mdrefr = |
295 | (postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem); | |
9e2697ff RK |
296 | |
297 | /* If we're dividing the memory clock by two for the SDRAM clock, this | |
298 | * must be set prior to the change. Clearing the divide must be done | |
299 | * after the change. | |
300 | */ | |
301 | if (pxa_freq_settings[idx].div2) { | |
302 | preset_mdrefr |= MDREFR_DB2_MASK; | |
303 | postset_mdrefr |= MDREFR_DB2_MASK; | |
304 | } else { | |
305 | postset_mdrefr &= ~MDREFR_DB2_MASK; | |
306 | } | |
307 | ||
308 | local_irq_save(flags); | |
309 | ||
592eb999 | 310 | /* Set new the CCCR and prepare CCLKCFG */ |
9e2697ff | 311 | CCCR = pxa_freq_settings[idx].cccr; |
592eb999 | 312 | cclkcfg = pxa_freq_settings[idx].cclkcfg; |
9e2697ff RK |
313 | |
314 | asm volatile(" \n\ | |
315 | ldr r4, [%1] /* load MDREFR */ \n\ | |
316 | b 2f \n\ | |
3679389b | 317 | .align 5 \n\ |
9e2697ff | 318 | 1: \n\ |
592eb999 | 319 | str %3, [%1] /* preset the MDREFR */ \n\ |
9e2697ff | 320 | mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\ |
592eb999 | 321 | str %4, [%1] /* postset the MDREFR */ \n\ |
9e2697ff RK |
322 | \n\ |
323 | b 3f \n\ | |
324 | 2: b 1b \n\ | |
325 | 3: nop \n\ | |
326 | " | |
3679389b | 327 | : "=&r" (unused) |
592eb999 RJ |
328 | : "r" (&MDREFR), "r" (cclkcfg), |
329 | "r" (preset_mdrefr), "r" (postset_mdrefr) | |
3679389b | 330 | : "r4", "r5"); |
9e2697ff RK |
331 | local_irq_restore(flags); |
332 | ||
333 | /* | |
334 | * Tell everyone what we've just done... | |
335 | * you should add a notify client with any platform specific | |
336 | * SDRAM refresh timer adjustments | |
337 | */ | |
338 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
339 | ||
340 | return 0; | |
341 | } | |
342 | ||
592eb999 | 343 | static __init int pxa_cpufreq_init(struct cpufreq_policy *policy) |
9e2697ff RK |
344 | { |
345 | int i; | |
592eb999 | 346 | unsigned int freq; |
65587f7d MZ |
347 | struct cpufreq_frequency_table *pxa255_freq_table; |
348 | pxa_freqs_t *pxa255_freqs; | |
592eb999 RJ |
349 | |
350 | /* try to guess pxa27x cpu */ | |
351 | if (cpu_is_pxa27x()) | |
352 | pxa27x_guess_max_freq(); | |
9e2697ff | 353 | |
a10c287d PZ |
354 | init_sdram_rows(); |
355 | ||
9e2697ff | 356 | /* set default policy and cpuinfo */ |
9e2697ff | 357 | policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ |
3679389b | 358 | policy->cur = get_clk_frequency_khz(0); /* current freq */ |
9e2697ff RK |
359 | policy->min = policy->max = policy->cur; |
360 | ||
592eb999 RJ |
361 | /* Generate pxa25x the run cpufreq_frequency_table struct */ |
362 | for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) { | |
9e2697ff RK |
363 | pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz; |
364 | pxa255_run_freq_table[i].index = i; | |
365 | } | |
9e2697ff | 366 | pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END; |
592eb999 RJ |
367 | |
368 | /* Generate pxa25x the turbo cpufreq_frequency_table struct */ | |
369 | for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) { | |
3679389b RJ |
370 | pxa255_turbo_freq_table[i].frequency = |
371 | pxa255_turbo_freqs[i].khz; | |
9e2697ff RK |
372 | pxa255_turbo_freq_table[i].index = i; |
373 | } | |
374 | pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END; | |
375 | ||
65587f7d MZ |
376 | pxa255_turbo_table = !!pxa255_turbo_table; |
377 | ||
592eb999 RJ |
378 | /* Generate the pxa27x cpufreq_frequency_table struct */ |
379 | for (i = 0; i < NUM_PXA27x_FREQS; i++) { | |
380 | freq = pxa27x_freqs[i].khz; | |
381 | if (freq > pxa27x_maxfreq) | |
382 | break; | |
383 | pxa27x_freq_table[i].frequency = freq; | |
384 | pxa27x_freq_table[i].index = i; | |
385 | } | |
386 | pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END; | |
387 | ||
388 | /* | |
389 | * Set the policy's minimum and maximum frequencies from the tables | |
390 | * just constructed. This sets cpuinfo.mxx_freq, min and max. | |
391 | */ | |
65587f7d MZ |
392 | if (cpu_is_pxa25x()) { |
393 | find_freq_tables(&pxa255_freq_table, &pxa255_freqs); | |
394 | pr_info("PXA255 cpufreq using %s frequency table\n", | |
395 | pxa255_turbo_table ? "turbo" : "run"); | |
396 | cpufreq_frequency_table_cpuinfo(policy, pxa255_freq_table); | |
397 | } | |
592eb999 RJ |
398 | else if (cpu_is_pxa27x()) |
399 | cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table); | |
400 | ||
9e2697ff RK |
401 | printk(KERN_INFO "PXA CPU frequency change support initialized\n"); |
402 | ||
403 | return 0; | |
404 | } | |
405 | ||
406 | static struct cpufreq_driver pxa_cpufreq_driver = { | |
407 | .verify = pxa_verify_policy, | |
408 | .target = pxa_set_target, | |
409 | .init = pxa_cpufreq_init, | |
ea833f0b | 410 | .get = pxa_cpufreq_get, |
592eb999 | 411 | .name = "PXA2xx", |
9e2697ff RK |
412 | }; |
413 | ||
414 | static int __init pxa_cpu_init(void) | |
415 | { | |
416 | int ret = -ENODEV; | |
592eb999 | 417 | if (cpu_is_pxa25x() || cpu_is_pxa27x()) |
9e2697ff RK |
418 | ret = cpufreq_register_driver(&pxa_cpufreq_driver); |
419 | return ret; | |
420 | } | |
421 | ||
422 | static void __exit pxa_cpu_exit(void) | |
423 | { | |
592eb999 | 424 | cpufreq_unregister_driver(&pxa_cpufreq_driver); |
9e2697ff RK |
425 | } |
426 | ||
427 | ||
3679389b RJ |
428 | MODULE_AUTHOR("Intrinsyc Software Inc."); |
429 | MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture"); | |
9e2697ff RK |
430 | MODULE_LICENSE("GPL"); |
431 | module_init(pxa_cpu_init); | |
432 | module_exit(pxa_cpu_exit); |