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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-pxa / devices.c
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b2441318 1// SPDX-License-Identifier: GPL-2.0
8f58de7c 2#include <linux/module.h>
3#include <linux/kernel.h>
4#include <linux/init.h>
5#include <linux/platform_device.h>
6#include <linux/dma-mapping.h>
8348c259 7#include <linux/spi/pxa2xx_spi.h>
b459396e 8#include <linux/i2c/pxa-i2c.h>
8f58de7c 9
4c25c5d2 10#include "udc.h"
293b2da1
AB		 11#include <linux/platform_data/usb-pxa3xx-ulpi.h>
12#include <linux/platform_data/video-pxafb.h>
13#include <linux/platform_data/mmc-pxamci.h>
14#include <linux/platform_data/irda-pxaficp.h>
4e611091 15#include <mach/irqs.h>
293b2da1
AB		 16#include <linux/platform_data/usb-ohci-pxa27x.h>
17#include <linux/platform_data/keypad-pxa27x.h>
a71daaa1 18#include <linux/platform_data/media/camera-pxa.h>
a09e64fb 19#include <mach/audio.h>
75e874c6 20#include <mach/hardware.h>
4be0856f 21#include <linux/platform_data/mmp_dma.h>
293b2da1 22#include <linux/platform_data/mtd-nand-pxa3xx.h>
8f58de7c 23
24#include "devices.h"
bc3a5959 25#include "generic.h"
8f58de7c 26
27void __init pxa_register_device(struct platform_device *dev, void *data)
28{
29 int ret;
30
31 dev->dev.platform_data = data;
32
33 ret = platform_device_register(dev);
34 if (ret)
35 dev_err(&dev->dev, "unable to register device: %d\n", ret);
36}
37
09a5358d
EM		 38static struct resource pxa_resource_pmu = {
39 .start = IRQ_PMU,
40 .end = IRQ_PMU,
41 .flags = IORESOURCE_IRQ,
42};
43
44struct platform_device pxa_device_pmu = {
f9eff219 45 .name = "xscale-pmu",
df3d17e0 46 .id = -1,
09a5358d
EM		 47 .resource = &pxa_resource_pmu,
48 .num_resources = 1,
49};
50
8f58de7c 51static struct resource pxamci_resources[] = {
52 [0] = {
53 .start = 0x41100000,
54 .end = 0x41100fff,
55 .flags = IORESOURCE_MEM,
56 },
57 [1] = {
58 .start = IRQ_MMC,
59 .end = IRQ_MMC,
60 .flags = IORESOURCE_IRQ,
61 },
62 [2] = {
63 .start = 21,
64 .end = 21,
65 .flags = IORESOURCE_DMA,
66 },
67 [3] = {
68 .start = 22,
69 .end = 22,
70 .flags = IORESOURCE_DMA,
71 },
72};
73
74static u64 pxamci_dmamask = 0xffffffffUL;
75
76struct platform_device pxa_device_mci = {
77 .name = "pxa2xx-mci",
fafc9d3f 78 .id = 0,
8f58de7c 79 .dev = {
80 .dma_mask = &pxamci_dmamask,
81 .coherent_dma_mask = 0xffffffff,
82 },
83 .num_resources = ARRAY_SIZE(pxamci_resources),
84 .resource = pxamci_resources,
85};
86
87void __init pxa_set_mci_info(struct pxamci_platform_data *info)
88{
89 pxa_register_device(&pxa_device_mci, info);
90}
91
92
1257629b
PZ		 93static struct pxa2xx_udc_mach_info pxa_udc_info = {
94 .gpio_pullup = -1,
1257629b 95};
8f58de7c 96
97void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
98{
99 memcpy(&pxa_udc_info, info, sizeof *info);
100}
101
102static struct resource pxa2xx_udc_resources[] = {
103 [0] = {
104 .start = 0x40600000,
105 .end = 0x4060ffff,
106 .flags = IORESOURCE_MEM,
107 },
108 [1] = {
109 .start = IRQ_USB,
110 .end = IRQ_USB,
111 .flags = IORESOURCE_IRQ,
112 },
113};
114
115static u64 udc_dma_mask = ~(u32)0;
116
7a857620
PZ		 117struct platform_device pxa25x_device_udc = {
118 .name = "pxa25x-udc",
119 .id = -1,
120 .resource = pxa2xx_udc_resources,
121 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
122 .dev = {
123 .platform_data = &pxa_udc_info,
124 .dma_mask = &udc_dma_mask,
125 }
126};
127
128struct platform_device pxa27x_device_udc = {
129 .name = "pxa27x-udc",
8f58de7c 130 .id = -1,
131 .resource = pxa2xx_udc_resources,
132 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
133 .dev = {
134 .platform_data = &pxa_udc_info,
135 .dma_mask = &udc_dma_mask,
136 }
137};
138
69f22be7
IG		 139#ifdef CONFIG_PXA3xx
140static struct resource pxa3xx_u2d_resources[] = {
141 [0] = {
142 .start = 0x54100000,
143 .end = 0x54100fff,
144 .flags = IORESOURCE_MEM,
145 },
146 [1] = {
147 .start = IRQ_USB2,
148 .end = IRQ_USB2,
149 .flags = IORESOURCE_IRQ,
150 },
151};
152
153struct platform_device pxa3xx_device_u2d = {
154 .name = "pxa3xx-u2d",
155 .id = -1,
156 .resource = pxa3xx_u2d_resources,
157 .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
158};
159
160void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
161{
162 pxa_register_device(&pxa3xx_device_u2d, info);
163}
164#endif /* CONFIG_PXA3xx */
165
8f58de7c 166static struct resource pxafb_resources[] = {
167 [0] = {
168 .start = 0x44000000,
169 .end = 0x4400ffff,
170 .flags = IORESOURCE_MEM,
171 },
172 [1] = {
173 .start = IRQ_LCD,
174 .end = IRQ_LCD,
175 .flags = IORESOURCE_IRQ,
176 },
177};
178
179static u64 fb_dma_mask = ~(u64)0;
180
181struct platform_device pxa_device_fb = {
182 .name = "pxa2xx-fb",
183 .id = -1,
184 .dev = {
185 .dma_mask = &fb_dma_mask,
186 .coherent_dma_mask = 0xffffffff,
187 },
188 .num_resources = ARRAY_SIZE(pxafb_resources),
189 .resource = pxafb_resources,
190};
191
4321e1a1 192void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
8f58de7c 193{
4321e1a1 194 pxa_device_fb.dev.parent = parent;
8f58de7c 195 pxa_register_device(&pxa_device_fb, info);
196}
197
8f58de7c 198static struct resource pxa_resource_ffuart[] = {
199 {
02f65262
EM		 200 .start = 0x40100000,
201 .end = 0x40100023,
8f58de7c 202 .flags = IORESOURCE_MEM,
203 }, {
204 .start = IRQ_FFUART,
205 .end = IRQ_FFUART,
206 .flags = IORESOURCE_IRQ,
207 }
208};
209
cc155c6f 210struct platform_device pxa_device_ffuart = {
8f58de7c 211 .name = "pxa2xx-uart",
212 .id = 0,
213 .resource = pxa_resource_ffuart,
214 .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
215};
216
cc155c6f
RK		 217void __init pxa_set_ffuart_info(void *info)
218{
219 pxa_register_device(&pxa_device_ffuart, info);
220}
221
8f58de7c 222static struct resource pxa_resource_btuart[] = {
223 {
02f65262
EM		 224 .start = 0x40200000,
225 .end = 0x40200023,
8f58de7c 226 .flags = IORESOURCE_MEM,
227 }, {
228 .start = IRQ_BTUART,
229 .end = IRQ_BTUART,
230 .flags = IORESOURCE_IRQ,
231 }
232};
233
234struct platform_device pxa_device_btuart = {
235 .name = "pxa2xx-uart",
236 .id = 1,
237 .resource = pxa_resource_btuart,
238 .num_resources = ARRAY_SIZE(pxa_resource_btuart),
239};
240
cc155c6f
RK		 241void __init pxa_set_btuart_info(void *info)
242{
243 pxa_register_device(&pxa_device_btuart, info);
244}
245
8f58de7c 246static struct resource pxa_resource_stuart[] = {
247 {
02f65262
EM		 248 .start = 0x40700000,
249 .end = 0x40700023,
8f58de7c 250 .flags = IORESOURCE_MEM,
251 }, {
252 .start = IRQ_STUART,
253 .end = IRQ_STUART,
254 .flags = IORESOURCE_IRQ,
255 }
256};
257
258struct platform_device pxa_device_stuart = {
259 .name = "pxa2xx-uart",
260 .id = 2,
261 .resource = pxa_resource_stuart,
262 .num_resources = ARRAY_SIZE(pxa_resource_stuart),
263};
264
cc155c6f
RK		 265void __init pxa_set_stuart_info(void *info)
266{
267 pxa_register_device(&pxa_device_stuart, info);
268}
269
8f58de7c 270static struct resource pxa_resource_hwuart[] = {
271 {
02f65262
EM		 272 .start = 0x41600000,
273 .end = 0x4160002F,
8f58de7c 274 .flags = IORESOURCE_MEM,
275 }, {
276 .start = IRQ_HWUART,
277 .end = IRQ_HWUART,
278 .flags = IORESOURCE_IRQ,
279 }
280};
281
282struct platform_device pxa_device_hwuart = {
283 .name = "pxa2xx-uart",
284 .id = 3,
285 .resource = pxa_resource_hwuart,
286 .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
287};
288
cc155c6f
RK		 289void __init pxa_set_hwuart_info(void *info)
290{
291 if (cpu_is_pxa255())
292 pxa_register_device(&pxa_device_hwuart, info);
293 else
294 pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
295}
296
8f58de7c 297static struct resource pxai2c_resources[] = {
298 {
299 .start = 0x40301680,
300 .end = 0x403016a3,
301 .flags = IORESOURCE_MEM,
302 }, {
303 .start = IRQ_I2C,
304 .end = IRQ_I2C,
305 .flags = IORESOURCE_IRQ,
306 },
307};
308
309struct platform_device pxa_device_i2c = {
310 .name = "pxa2xx-i2c",
311 .id = 0,
312 .resource = pxai2c_resources,
313 .num_resources = ARRAY_SIZE(pxai2c_resources),
314};
315
316void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
317{
318 pxa_register_device(&pxa_device_i2c, info);
319}
320
99464293
EM		 321#ifdef CONFIG_PXA27x
322static struct resource pxa27x_resources_i2c_power[] = {
323 {
324 .start = 0x40f00180,
325 .end = 0x40f001a3,
326 .flags = IORESOURCE_MEM,
327 }, {
328 .start = IRQ_PWRI2C,
329 .end = IRQ_PWRI2C,
330 .flags = IORESOURCE_IRQ,
331 },
332};
333
334struct platform_device pxa27x_device_i2c_power = {
335 .name = "pxa2xx-i2c",
336 .id = 1,
337 .resource = pxa27x_resources_i2c_power,
338 .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
339};
340#endif
341
8f58de7c 342static struct resource pxai2s_resources[] = {
343 {
344 .start = 0x40400000,
345 .end = 0x40400083,
346 .flags = IORESOURCE_MEM,
347 }, {
348 .start = IRQ_I2S,
349 .end = IRQ_I2S,
350 .flags = IORESOURCE_IRQ,
351 },
352};
353
354struct platform_device pxa_device_i2s = {
355 .name = "pxa2xx-i2s",
356 .id = -1,
357 .resource = pxai2s_resources,
358 .num_resources = ARRAY_SIZE(pxai2s_resources),
359};
360
f0fba2ad
LG		 361struct platform_device pxa_device_asoc_ssp1 = {
362 .name = "pxa-ssp-dai",
363 .id = 0,
364};
365
366struct platform_device pxa_device_asoc_ssp2= {
367 .name = "pxa-ssp-dai",
368 .id = 1,
369};
370
371struct platform_device pxa_device_asoc_ssp3 = {
372 .name = "pxa-ssp-dai",
373 .id = 2,
374};
375
376struct platform_device pxa_device_asoc_ssp4 = {
377 .name = "pxa-ssp-dai",
378 .id = 3,
379};
380
381struct platform_device pxa_device_asoc_platform = {
382 .name = "pxa-pcm-audio",
383 .id = -1,
384};
385
8f58de7c 386static u64 pxaficp_dmamask = ~(u32)0;
387
121f3f9b
RH		 388static struct resource pxa_ir_resources[] = {
389 [0] = {
390 .start = IRQ_STUART,
391 .end = IRQ_STUART,
392 .flags = IORESOURCE_IRQ,
393 },
394 [1] = {
395 .start = IRQ_ICP,
396 .end = IRQ_ICP,
397 .flags = IORESOURCE_IRQ,
398 },
48a629da
RJ		 399 [3] = {
400 .start = 0x40800000,
401 .end = 0x4080001b,
402 .flags = IORESOURCE_MEM,
403 },
404 [4] = {
405 .start = 0x40700000,
406 .end = 0x40700023,
407 .flags = IORESOURCE_MEM,
408 },
409 [5] = {
410 .start = 17,
411 .end = 17,
412 .flags = IORESOURCE_DMA,
413 },
414 [6] = {
415 .start = 18,
416 .end = 18,
417 .flags = IORESOURCE_DMA,
418 },
121f3f9b
RH		 419};
420
8f58de7c 421struct platform_device pxa_device_ficp = {
422 .name = "pxa2xx-ir",
423 .id = -1,
121f3f9b
RH		 424 .num_resources = ARRAY_SIZE(pxa_ir_resources),
425 .resource = pxa_ir_resources,
8f58de7c 426 .dev = {
427 .dma_mask = &pxaficp_dmamask,
428 .coherent_dma_mask = 0xffffffff,
429 },
430};
431
432void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
433{
434 pxa_register_device(&pxa_device_ficp, info);
435}
436
72493146
RJ		 437static struct resource pxa_rtc_resources[] = {
438 [0] = {
439 .start = 0x40900000,
440 .end = 0x40900000 + 0x3b,
441 .flags = IORESOURCE_MEM,
442 },
443 [1] = {
444 .start = IRQ_RTC1Hz,
445 .end = IRQ_RTC1Hz,
3888c090 446 .name = "rtc 1Hz",
72493146
RJ		 447 .flags = IORESOURCE_IRQ,
448 },
449 [2] = {
450 .start = IRQ_RTCAlrm,
451 .end = IRQ_RTCAlrm,
3888c090 452 .name = "rtc alarm",
72493146
RJ		 453 .flags = IORESOURCE_IRQ,
454 },
455};
456
72493146
RJ		 457struct platform_device pxa_device_rtc = {
458 .name = "pxa-rtc",
459 .id = -1,
460 .num_resources = ARRAY_SIZE(pxa_rtc_resources),
461 .resource = pxa_rtc_resources,
462};
463
3888c090
HZ		 464struct platform_device sa1100_device_rtc = {
465 .name = "sa1100-rtc",
466 .id = -1,
2c4fabec
RH		 467 .num_resources = ARRAY_SIZE(pxa_rtc_resources),
468 .resource = pxa_rtc_resources,
3888c090
HZ		 469};
470
9f19d638
MB		 471static struct resource pxa_ac97_resources[] = {
472 [0] = {
473 .start = 0x40500000,
474 .end = 0x40500000 + 0xfff,
475 .flags = IORESOURCE_MEM,
476 },
477 [1] = {
478 .start = IRQ_AC97,
479 .end = IRQ_AC97,
480 .flags = IORESOURCE_IRQ,
481 },
482};
483
484static u64 pxa_ac97_dmamask = 0xffffffffUL;
485
486struct platform_device pxa_device_ac97 = {
487 .name = "pxa2xx-ac97",
488 .id = -1,
489 .dev = {
490 .dma_mask = &pxa_ac97_dmamask,
491 .coherent_dma_mask = 0xffffffff,
492 },
493 .num_resources = ARRAY_SIZE(pxa_ac97_resources),
494 .resource = pxa_ac97_resources,
495};
496
497void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
498{
499 pxa_register_device(&pxa_device_ac97, ops);
500}
501
8f58de7c 502#ifdef CONFIG_PXA25x
503
75540c1a 504static struct resource pxa25x_resource_pwm0[] = {
505 [0] = {
506 .start = 0x40b00000,
507 .end = 0x40b0000f,
508 .flags = IORESOURCE_MEM,
509 },
510};
511
512struct platform_device pxa25x_device_pwm0 = {
513 .name = "pxa25x-pwm",
514 .id = 0,
515 .resource = pxa25x_resource_pwm0,
516 .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
517};
518
519static struct resource pxa25x_resource_pwm1[] = {
520 [0] = {
521 .start = 0x40c00000,
522 .end = 0x40c0000f,
523 .flags = IORESOURCE_MEM,
524 },
525};
526
527struct platform_device pxa25x_device_pwm1 = {
528 .name = "pxa25x-pwm",
529 .id = 1,
530 .resource = pxa25x_resource_pwm1,
531 .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
532};
533
8f58de7c 534static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
535
536static struct resource pxa25x_resource_ssp[] = {
537 [0] = {
538 .start = 0x41000000,
539 .end = 0x4100001f,
540 .flags = IORESOURCE_MEM,
541 },
542 [1] = {
543 .start = IRQ_SSP,
544 .end = IRQ_SSP,
545 .flags = IORESOURCE_IRQ,
546 },
547 [2] = {
548 /* DRCMR for RX */
549 .start = 13,
550 .end = 13,
551 .flags = IORESOURCE_DMA,
552 },
553 [3] = {
554 /* DRCMR for TX */
555 .start = 14,
556 .end = 14,
557 .flags = IORESOURCE_DMA,
558 },
559};
560
561struct platform_device pxa25x_device_ssp = {
562 .name = "pxa25x-ssp",
563 .id = 0,
564 .dev = {
565 .dma_mask = &pxa25x_ssp_dma_mask,
566 .coherent_dma_mask = DMA_BIT_MASK(32),
567 },
568 .resource = pxa25x_resource_ssp,
569 .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
570};
571
572static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
573
574static struct resource pxa25x_resource_nssp[] = {
575 [0] = {
576 .start = 0x41400000,
577 .end = 0x4140002f,
578 .flags = IORESOURCE_MEM,
579 },
580 [1] = {
581 .start = IRQ_NSSP,
582 .end = IRQ_NSSP,
583 .flags = IORESOURCE_IRQ,
584 },
585 [2] = {
586 /* DRCMR for RX */
587 .start = 15,
588 .end = 15,
589 .flags = IORESOURCE_DMA,
590 },
591 [3] = {
592 /* DRCMR for TX */
593 .start = 16,
594 .end = 16,
595 .flags = IORESOURCE_DMA,
596 },
597};
598
599struct platform_device pxa25x_device_nssp = {
600 .name = "pxa25x-nssp",
601 .id = 1,
602 .dev = {
603 .dma_mask = &pxa25x_nssp_dma_mask,
604 .coherent_dma_mask = DMA_BIT_MASK(32),
605 },
606 .resource = pxa25x_resource_nssp,
607 .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
608};
609
610static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
611
612static struct resource pxa25x_resource_assp[] = {
613 [0] = {
614 .start = 0x41500000,
615 .end = 0x4150002f,
616 .flags = IORESOURCE_MEM,
617 },
618 [1] = {
619 .start = IRQ_ASSP,
620 .end = IRQ_ASSP,
621 .flags = IORESOURCE_IRQ,
622 },
623 [2] = {
624 /* DRCMR for RX */
625 .start = 23,
626 .end = 23,
627 .flags = IORESOURCE_DMA,
628 },
629 [3] = {
630 /* DRCMR for TX */
631 .start = 24,
632 .end = 24,
633 .flags = IORESOURCE_DMA,
634 },
635};
636
637struct platform_device pxa25x_device_assp = {
638 /* ASSP is basically equivalent to NSSP */
639 .name = "pxa25x-nssp",
640 .id = 2,
641 .dev = {
642 .dma_mask = &pxa25x_assp_dma_mask,
643 .coherent_dma_mask = DMA_BIT_MASK(32),
644 },
645 .resource = pxa25x_resource_assp,
646 .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
647};
648#endif /* CONFIG_PXA25x */
649
650#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
a4553358 651static struct resource pxa27x_resource_camera[] = {
37320980 652 [0] = {
a4553358
HZ		 653 .start = 0x50000000,
654 .end = 0x50000fff,
37320980 655 .flags = IORESOURCE_MEM,
656 },
657 [1] = {
a4553358
HZ		 658 .start = IRQ_CAMERA,
659 .end = IRQ_CAMERA,
37320980 660 .flags = IORESOURCE_IRQ,
661 },
662};
663
a4553358
HZ		 664static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
665
666static struct platform_device pxa27x_device_camera = {
667 .name = "pxa27x-camera",
668 .id = 0, /* This is used to put cameras on this interface */
669 .dev = {
670 .dma_mask = &pxa27x_dma_mask_camera,
671 .coherent_dma_mask = 0xffffffff,
672 },
673 .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
674 .resource = pxa27x_resource_camera,
37320980 675};
676
a4553358 677void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
37320980 678{
a4553358 679 pxa_register_device(&pxa27x_device_camera, info);
37320980 680}
681
ec68e45b 682static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
683
684static struct resource pxa27x_resource_ohci[] = {
685 [0] = {
686 .start = 0x4C000000,
687 .end = 0x4C00ff6f,
688 .flags = IORESOURCE_MEM,
689 },
690 [1] = {
691 .start = IRQ_USBH1,
692 .end = IRQ_USBH1,
693 .flags = IORESOURCE_IRQ,
694 },
695};
696
697struct platform_device pxa27x_device_ohci = {
698 .name = "pxa27x-ohci",
699 .id = -1,
700 .dev = {
701 .dma_mask = &pxa27x_ohci_dma_mask,
702 .coherent_dma_mask = DMA_BIT_MASK(32),
703 },
704 .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
705 .resource = pxa27x_resource_ohci,
706};
707
708void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
709{
710 pxa_register_device(&pxa27x_device_ohci, info);
711}
a4553358
HZ		 712#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
713
49ea7fc0 714#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
a4553358
HZ		 715static struct resource pxa27x_resource_keypad[] = {
716 [0] = {
717 .start = 0x41500000,
718 .end = 0x4150004c,
719 .flags = IORESOURCE_MEM,
720 },
721 [1] = {
722 .start = IRQ_KEYPAD,
723 .end = IRQ_KEYPAD,
724 .flags = IORESOURCE_IRQ,
725 },
726};
727
728struct platform_device pxa27x_device_keypad = {
729 .name = "pxa27x-keypad",
730 .id = -1,
731 .resource = pxa27x_resource_keypad,
732 .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
733};
734
735void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
736{
737 pxa_register_device(&pxa27x_device_keypad, info);
738}
ec68e45b 739
8f58de7c 740static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
741
742static struct resource pxa27x_resource_ssp1[] = {
743 [0] = {
744 .start = 0x41000000,
745 .end = 0x4100003f,
746 .flags = IORESOURCE_MEM,
747 },
748 [1] = {
749 .start = IRQ_SSP,
750 .end = IRQ_SSP,
751 .flags = IORESOURCE_IRQ,
752 },
753 [2] = {
754 /* DRCMR for RX */
755 .start = 13,
756 .end = 13,
757 .flags = IORESOURCE_DMA,
758 },
759 [3] = {
760 /* DRCMR for TX */
761 .start = 14,
762 .end = 14,
763 .flags = IORESOURCE_DMA,
764 },
765};
766
767struct platform_device pxa27x_device_ssp1 = {
768 .name = "pxa27x-ssp",
769 .id = 0,
770 .dev = {
771 .dma_mask = &pxa27x_ssp1_dma_mask,
772 .coherent_dma_mask = DMA_BIT_MASK(32),
773 },
774 .resource = pxa27x_resource_ssp1,
775 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
776};
777
778static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
779
780static struct resource pxa27x_resource_ssp2[] = {
781 [0] = {
782 .start = 0x41700000,
783 .end = 0x4170003f,
784 .flags = IORESOURCE_MEM,
785 },
786 [1] = {
787 .start = IRQ_SSP2,
788 .end = IRQ_SSP2,
789 .flags = IORESOURCE_IRQ,
790 },
791 [2] = {
792 /* DRCMR for RX */
793 .start = 15,
794 .end = 15,
795 .flags = IORESOURCE_DMA,
796 },
797 [3] = {
798 /* DRCMR for TX */
799 .start = 16,
800 .end = 16,
801 .flags = IORESOURCE_DMA,
802 },
803};
804
805struct platform_device pxa27x_device_ssp2 = {
806 .name = "pxa27x-ssp",
807 .id = 1,
808 .dev = {
809 .dma_mask = &pxa27x_ssp2_dma_mask,
810 .coherent_dma_mask = DMA_BIT_MASK(32),
811 },
812 .resource = pxa27x_resource_ssp2,
813 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
814};
815
816static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
817
818static struct resource pxa27x_resource_ssp3[] = {
819 [0] = {
820 .start = 0x41900000,
821 .end = 0x4190003f,
822 .flags = IORESOURCE_MEM,
823 },
824 [1] = {
825 .start = IRQ_SSP3,
826 .end = IRQ_SSP3,
827 .flags = IORESOURCE_IRQ,
828 },
829 [2] = {
830 /* DRCMR for RX */
831 .start = 66,
832 .end = 66,
833 .flags = IORESOURCE_DMA,
834 },
835 [3] = {
836 /* DRCMR for TX */
837 .start = 67,
838 .end = 67,
839 .flags = IORESOURCE_DMA,
840 },
841};
842
843struct platform_device pxa27x_device_ssp3 = {
844 .name = "pxa27x-ssp",
845 .id = 2,
846 .dev = {
847 .dma_mask = &pxa27x_ssp3_dma_mask,
848 .coherent_dma_mask = DMA_BIT_MASK(32),
849 },
850 .resource = pxa27x_resource_ssp3,
851 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
852};
3f3acefb 853
75540c1a 854static struct resource pxa27x_resource_pwm0[] = {
855 [0] = {
856 .start = 0x40b00000,
857 .end = 0x40b0001f,
858 .flags = IORESOURCE_MEM,
859 },
860};
861
862struct platform_device pxa27x_device_pwm0 = {
863 .name = "pxa27x-pwm",
864 .id = 0,
865 .resource = pxa27x_resource_pwm0,
866 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
867};
868
869static struct resource pxa27x_resource_pwm1[] = {
870 [0] = {
871 .start = 0x40c00000,
872 .end = 0x40c0001f,
873 .flags = IORESOURCE_MEM,
874 },
875};
876
877struct platform_device pxa27x_device_pwm1 = {
878 .name = "pxa27x-pwm",
879 .id = 1,
880 .resource = pxa27x_resource_pwm1,
881 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
882};
49ea7fc0 883#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
8f58de7c 884
885#ifdef CONFIG_PXA3xx
8d33b055
BW		 886static struct resource pxa3xx_resources_mci2[] = {
887 [0] = {
888 .start = 0x42000000,
889 .end = 0x42000fff,
890 .flags = IORESOURCE_MEM,
891 },
892 [1] = {
893 .start = IRQ_MMC2,
894 .end = IRQ_MMC2,
895 .flags = IORESOURCE_IRQ,
896 },
897 [2] = {
898 .start = 93,
899 .end = 93,
900 .flags = IORESOURCE_DMA,
901 },
902 [3] = {
903 .start = 94,
904 .end = 94,
905 .flags = IORESOURCE_DMA,
906 },
907};
908
909struct platform_device pxa3xx_device_mci2 = {
910 .name = "pxa2xx-mci",
911 .id = 1,
912 .dev = {
913 .dma_mask = &pxamci_dmamask,
914 .coherent_dma_mask = 0xffffffff,
915 },
916 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
917 .resource = pxa3xx_resources_mci2,
918};
919
920void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
921{
922 pxa_register_device(&pxa3xx_device_mci2, info);
923}
924
5a1f21b1
BW		 925static struct resource pxa3xx_resources_mci3[] = {
926 [0] = {
927 .start = 0x42500000,
928 .end = 0x42500fff,
929 .flags = IORESOURCE_MEM,
930 },
931 [1] = {
932 .start = IRQ_MMC3,
933 .end = IRQ_MMC3,
934 .flags = IORESOURCE_IRQ,
935 },
936 [2] = {
937 .start = 100,
938 .end = 100,
939 .flags = IORESOURCE_DMA,
940 },
941 [3] = {
942 .start = 101,
943 .end = 101,
944 .flags = IORESOURCE_DMA,
945 },
946};
947
948struct platform_device pxa3xx_device_mci3 = {
949 .name = "pxa2xx-mci",
950 .id = 2,
951 .dev = {
952 .dma_mask = &pxamci_dmamask,
953 .coherent_dma_mask = 0xffffffff,
954 },
955 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
956 .resource = pxa3xx_resources_mci3,
957};
958
959void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
960{
961 pxa_register_device(&pxa3xx_device_mci3, info);
962}
963
a4553358
HZ		 964static struct resource pxa3xx_resources_gcu[] = {
965 {
966 .start = 0x54000000,
967 .end = 0x54000fff,
968 .flags = IORESOURCE_MEM,
969 },
970 {
971 .start = IRQ_GCU,
972 .end = IRQ_GCU,
973 .flags = IORESOURCE_IRQ,
974 },
975};
976
977static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
978
979struct platform_device pxa3xx_device_gcu = {
980 .name = "pxa3xx-gcu",
981 .id = -1,
982 .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
983 .resource = pxa3xx_resources_gcu,
984 .dev = {
985 .dma_mask = &pxa3xx_gcu_dmamask,
986 .coherent_dma_mask = 0xffffffff,
987 },
988};
989
990#endif /* CONFIG_PXA3xx */
991
49ea7fc0 992#if defined(CONFIG_PXA3xx)
a4553358
HZ		 993static struct resource pxa3xx_resources_i2c_power[] = {
994 {
995 .start = 0x40f500c0,
996 .end = 0x40f500d3,
997 .flags = IORESOURCE_MEM,
998 }, {
999 .start = IRQ_PWRI2C,
1000 .end = IRQ_PWRI2C,
1001 .flags = IORESOURCE_IRQ,
1002 },
1003};
1004
1005struct platform_device pxa3xx_device_i2c_power = {
1006 .name = "pxa3xx-pwri2c",
1007 .id = 1,
1008 .resource = pxa3xx_resources_i2c_power,
1009 .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
1010};
1011
9ae819a8
EM		 1012static struct resource pxa3xx_resources_nand[] = {
1013 [0] = {
1014 .start = 0x43100000,
1015 .end = 0x43100053,
1016 .flags = IORESOURCE_MEM,
1017 },
1018 [1] = {
1019 .start = IRQ_NAND,
1020 .end = IRQ_NAND,
1021 .flags = IORESOURCE_IRQ,
1022 },
1023 [2] = {
1024 /* DRCMR for Data DMA */
1025 .start = 97,
1026 .end = 97,
1027 .flags = IORESOURCE_DMA,
1028 },
1029 [3] = {
1030 /* DRCMR for Command DMA */
1031 .start = 99,
1032 .end = 99,
1033 .flags = IORESOURCE_DMA,
1034 },
1035};
1036
1037static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
1038
1039struct platform_device pxa3xx_device_nand = {
1040 .name = "pxa3xx-nand",
1041 .id = -1,
1042 .dev = {
1043 .dma_mask = &pxa3xx_nand_dma_mask,
1044 .coherent_dma_mask = DMA_BIT_MASK(32),
1045 },
1046 .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
1047 .resource = pxa3xx_resources_nand,
1048};
1049
1050void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
1051{
1052 pxa_register_device(&pxa3xx_device_nand, info);
1053}
1ff2c33e 1054
a4553358
HZ		 1055static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
1056
1057static struct resource pxa3xx_resource_ssp4[] = {
1058 [0] = {
1059 .start = 0x41a00000,
1060 .end = 0x41a0003f,
1ff2c33e
DM		 1061 .flags = IORESOURCE_MEM,
1062 },
a4553358
HZ		 1063 [1] = {
1064 .start = IRQ_SSP4,
1065 .end = IRQ_SSP4,
1ff2c33e
DM		 1066 .flags = IORESOURCE_IRQ,
1067 },
a4553358
HZ		 1068 [2] = {
1069 /* DRCMR for RX */
1070 .start = 2,
1071 .end = 2,
1072 .flags = IORESOURCE_DMA,
1073 },
1074 [3] = {
1075 /* DRCMR for TX */
1076 .start = 3,
1077 .end = 3,
1078 .flags = IORESOURCE_DMA,
1079 },
1ff2c33e
DM		 1080};
1081
0da0e227
DM		 1082/*
1083 * PXA3xx SSP is basically equivalent to PXA27x.
1084 * However, we need to register the device by the correct name in order to
1085 * make the driver set the correct internal type, hence we provide specific
1086 * platform_devices for each of them.
1087 */
1088struct platform_device pxa3xx_device_ssp1 = {
1089 .name = "pxa3xx-ssp",
1090 .id = 0,
1091 .dev = {
1092 .dma_mask = &pxa27x_ssp1_dma_mask,
1093 .coherent_dma_mask = DMA_BIT_MASK(32),
1094 },
1095 .resource = pxa27x_resource_ssp1,
1096 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
1097};
1098
1099struct platform_device pxa3xx_device_ssp2 = {
1100 .name = "pxa3xx-ssp",
1101 .id = 1,
1102 .dev = {
1103 .dma_mask = &pxa27x_ssp2_dma_mask,
1104 .coherent_dma_mask = DMA_BIT_MASK(32),
1105 },
1106 .resource = pxa27x_resource_ssp2,
1107 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
1108};
1109
1110struct platform_device pxa3xx_device_ssp3 = {
1111 .name = "pxa3xx-ssp",
1112 .id = 2,
1113 .dev = {
1114 .dma_mask = &pxa27x_ssp3_dma_mask,
1115 .coherent_dma_mask = DMA_BIT_MASK(32),
1116 },
1117 .resource = pxa27x_resource_ssp3,
1118 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
1119};
1120
a4553358 1121struct platform_device pxa3xx_device_ssp4 = {
0da0e227 1122 .name = "pxa3xx-ssp",
a4553358 1123 .id = 3,
1ff2c33e 1124 .dev = {
a4553358
HZ		 1125 .dma_mask = &pxa3xx_ssp4_dma_mask,
1126 .coherent_dma_mask = DMA_BIT_MASK(32),
1ff2c33e 1127 },
a4553358
HZ		 1128 .resource = pxa3xx_resource_ssp4,
1129 .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
1ff2c33e 1130};
49ea7fc0 1131#endif /* CONFIG_PXA3xx */
e172274c 1132
157d2644
HZ		 1133struct resource pxa_resource_gpio[] = {
1134 {
1135 .start = 0x40e00000,
1136 .end = 0x40e0ffff,
1137 .flags = IORESOURCE_MEM,
1138 }, {
1139 .start = IRQ_GPIO0,
1140 .end = IRQ_GPIO0,
1141 .name = "gpio0",
1142 .flags = IORESOURCE_IRQ,
1143 }, {
1144 .start = IRQ_GPIO1,
1145 .end = IRQ_GPIO1,
1146 .name = "gpio1",
1147 .flags = IORESOURCE_IRQ,
1148 }, {
1149 .start = IRQ_GPIO_2_x,
1150 .end = IRQ_GPIO_2_x,
1151 .name = "gpio_mux",
1152 .flags = IORESOURCE_IRQ,
1153 },
1154};
1155
2cab0292
HZ		 1156struct platform_device pxa25x_device_gpio = {
1157#ifdef CONFIG_CPU_PXA26x
1158 .name = "pxa26x-gpio",
1159#else
1160 .name = "pxa25x-gpio",
1161#endif
1162 .id = -1,
1163 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1164 .resource = pxa_resource_gpio,
1165};
1166
1167struct platform_device pxa27x_device_gpio = {
1168 .name = "pxa27x-gpio",
1169 .id = -1,
1170 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1171 .resource = pxa_resource_gpio,
1172};
1173
1174struct platform_device pxa3xx_device_gpio = {
1175 .name = "pxa3xx-gpio",
1176 .id = -1,
1177 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1178 .resource = pxa_resource_gpio,
1179};
1180
1181struct platform_device pxa93x_device_gpio = {
1182 .name = "pxa93x-gpio",
157d2644
HZ		 1183 .id = -1,
1184 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1185 .resource = pxa_resource_gpio,
1186};
1187
e172274c
GL		 1188/* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
1189 * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
1190void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
1191{
1192 struct platform_device *pd;
1193
1194 pd = platform_device_alloc("pxa2xx-spi", id);
1195 if (pd == NULL) {
1196 printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
1197 id);
1198 return;
1199 }
1200
1201 pd->dev.platform_data = info;
1202 platform_device_add(pd);
1203}
4be0856f
RJ		 1204
1205static struct mmp_dma_platdata pxa_dma_pdata = {
1206 .dma_channels = 0,
72b195cb 1207 .nb_requestors = 0,
4be0856f
RJ		 1208};
1209
1210static struct resource pxa_dma_resource[] = {
1211 [0] = {
1212 .start = 0x40000000,
1213 .end = 0x4000ffff,
1214 .flags = IORESOURCE_MEM,
1215 },
1216 [1] = {
1217 .start = IRQ_DMA,
1218 .end = IRQ_DMA,
1219 .flags = IORESOURCE_IRQ,
1220 },
1221};
1222
1223static u64 pxadma_dmamask = 0xffffffffUL;
1224
1225static struct platform_device pxa2xx_pxa_dma = {
1226 .name = "pxa-dma",
1227 .id = 0,
1228 .dev = {
1229 .dma_mask = &pxadma_dmamask,
1230 .coherent_dma_mask = 0xffffffff,
1231 },
1232 .num_resources = ARRAY_SIZE(pxa_dma_resource),
1233 .resource = pxa_dma_resource,
1234};
1235
72b195cb 1236void __init pxa2xx_set_dmac_info(int nb_channels, int nb_requestors)
4be0856f
RJ		 1237{
1238 pxa_dma_pdata.dma_channels = nb_channels;
4c35430a 1239 pxa_dma_pdata.nb_requestors = nb_requestors;
4be0856f
RJ		 1240 pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata);
1241}
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