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8f58de7c | 1 | #include <linux/module.h> |
2 | #include <linux/kernel.h> | |
3 | #include <linux/init.h> | |
4 | #include <linux/platform_device.h> | |
5 | #include <linux/dma-mapping.h> | |
8348c259 | 6 | #include <linux/spi/pxa2xx_spi.h> |
b459396e | 7 | #include <linux/i2c/pxa-i2c.h> |
8f58de7c | 8 | |
a09e64fb | 9 | #include <mach/udc.h> |
293b2da1 AB |
10 | #include <linux/platform_data/usb-pxa3xx-ulpi.h> |
11 | #include <linux/platform_data/video-pxafb.h> | |
12 | #include <linux/platform_data/mmc-pxamci.h> | |
13 | #include <linux/platform_data/irda-pxaficp.h> | |
4e611091 | 14 | #include <mach/irqs.h> |
293b2da1 AB |
15 | #include <linux/platform_data/usb-ohci-pxa27x.h> |
16 | #include <linux/platform_data/keypad-pxa27x.h> | |
17 | #include <linux/platform_data/camera-pxa.h> | |
a09e64fb | 18 | #include <mach/audio.h> |
75e874c6 | 19 | #include <mach/hardware.h> |
4be0856f | 20 | #include <linux/platform_data/mmp_dma.h> |
293b2da1 | 21 | #include <linux/platform_data/mtd-nand-pxa3xx.h> |
8f58de7c | 22 | |
23 | #include "devices.h" | |
bc3a5959 | 24 | #include "generic.h" |
8f58de7c | 25 | |
26 | void __init pxa_register_device(struct platform_device *dev, void *data) | |
27 | { | |
28 | int ret; | |
29 | ||
30 | dev->dev.platform_data = data; | |
31 | ||
32 | ret = platform_device_register(dev); | |
33 | if (ret) | |
34 | dev_err(&dev->dev, "unable to register device: %d\n", ret); | |
35 | } | |
36 | ||
09a5358d EM |
37 | static struct resource pxa_resource_pmu = { |
38 | .start = IRQ_PMU, | |
39 | .end = IRQ_PMU, | |
40 | .flags = IORESOURCE_IRQ, | |
41 | }; | |
42 | ||
43 | struct platform_device pxa_device_pmu = { | |
f9eff219 | 44 | .name = "xscale-pmu", |
df3d17e0 | 45 | .id = -1, |
09a5358d EM |
46 | .resource = &pxa_resource_pmu, |
47 | .num_resources = 1, | |
48 | }; | |
49 | ||
8f58de7c | 50 | static struct resource pxamci_resources[] = { |
51 | [0] = { | |
52 | .start = 0x41100000, | |
53 | .end = 0x41100fff, | |
54 | .flags = IORESOURCE_MEM, | |
55 | }, | |
56 | [1] = { | |
57 | .start = IRQ_MMC, | |
58 | .end = IRQ_MMC, | |
59 | .flags = IORESOURCE_IRQ, | |
60 | }, | |
61 | [2] = { | |
62 | .start = 21, | |
63 | .end = 21, | |
64 | .flags = IORESOURCE_DMA, | |
65 | }, | |
66 | [3] = { | |
67 | .start = 22, | |
68 | .end = 22, | |
69 | .flags = IORESOURCE_DMA, | |
70 | }, | |
71 | }; | |
72 | ||
73 | static u64 pxamci_dmamask = 0xffffffffUL; | |
74 | ||
75 | struct platform_device pxa_device_mci = { | |
76 | .name = "pxa2xx-mci", | |
fafc9d3f | 77 | .id = 0, |
8f58de7c | 78 | .dev = { |
79 | .dma_mask = &pxamci_dmamask, | |
80 | .coherent_dma_mask = 0xffffffff, | |
81 | }, | |
82 | .num_resources = ARRAY_SIZE(pxamci_resources), | |
83 | .resource = pxamci_resources, | |
84 | }; | |
85 | ||
86 | void __init pxa_set_mci_info(struct pxamci_platform_data *info) | |
87 | { | |
88 | pxa_register_device(&pxa_device_mci, info); | |
89 | } | |
90 | ||
91 | ||
1257629b PZ |
92 | static struct pxa2xx_udc_mach_info pxa_udc_info = { |
93 | .gpio_pullup = -1, | |
1257629b | 94 | }; |
8f58de7c | 95 | |
96 | void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info) | |
97 | { | |
98 | memcpy(&pxa_udc_info, info, sizeof *info); | |
99 | } | |
100 | ||
101 | static struct resource pxa2xx_udc_resources[] = { | |
102 | [0] = { | |
103 | .start = 0x40600000, | |
104 | .end = 0x4060ffff, | |
105 | .flags = IORESOURCE_MEM, | |
106 | }, | |
107 | [1] = { | |
108 | .start = IRQ_USB, | |
109 | .end = IRQ_USB, | |
110 | .flags = IORESOURCE_IRQ, | |
111 | }, | |
112 | }; | |
113 | ||
114 | static u64 udc_dma_mask = ~(u32)0; | |
115 | ||
7a857620 PZ |
116 | struct platform_device pxa25x_device_udc = { |
117 | .name = "pxa25x-udc", | |
118 | .id = -1, | |
119 | .resource = pxa2xx_udc_resources, | |
120 | .num_resources = ARRAY_SIZE(pxa2xx_udc_resources), | |
121 | .dev = { | |
122 | .platform_data = &pxa_udc_info, | |
123 | .dma_mask = &udc_dma_mask, | |
124 | } | |
125 | }; | |
126 | ||
127 | struct platform_device pxa27x_device_udc = { | |
128 | .name = "pxa27x-udc", | |
8f58de7c | 129 | .id = -1, |
130 | .resource = pxa2xx_udc_resources, | |
131 | .num_resources = ARRAY_SIZE(pxa2xx_udc_resources), | |
132 | .dev = { | |
133 | .platform_data = &pxa_udc_info, | |
134 | .dma_mask = &udc_dma_mask, | |
135 | } | |
136 | }; | |
137 | ||
69f22be7 IG |
138 | #ifdef CONFIG_PXA3xx |
139 | static struct resource pxa3xx_u2d_resources[] = { | |
140 | [0] = { | |
141 | .start = 0x54100000, | |
142 | .end = 0x54100fff, | |
143 | .flags = IORESOURCE_MEM, | |
144 | }, | |
145 | [1] = { | |
146 | .start = IRQ_USB2, | |
147 | .end = IRQ_USB2, | |
148 | .flags = IORESOURCE_IRQ, | |
149 | }, | |
150 | }; | |
151 | ||
152 | struct platform_device pxa3xx_device_u2d = { | |
153 | .name = "pxa3xx-u2d", | |
154 | .id = -1, | |
155 | .resource = pxa3xx_u2d_resources, | |
156 | .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources), | |
157 | }; | |
158 | ||
159 | void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info) | |
160 | { | |
161 | pxa_register_device(&pxa3xx_device_u2d, info); | |
162 | } | |
163 | #endif /* CONFIG_PXA3xx */ | |
164 | ||
8f58de7c | 165 | static struct resource pxafb_resources[] = { |
166 | [0] = { | |
167 | .start = 0x44000000, | |
168 | .end = 0x4400ffff, | |
169 | .flags = IORESOURCE_MEM, | |
170 | }, | |
171 | [1] = { | |
172 | .start = IRQ_LCD, | |
173 | .end = IRQ_LCD, | |
174 | .flags = IORESOURCE_IRQ, | |
175 | }, | |
176 | }; | |
177 | ||
178 | static u64 fb_dma_mask = ~(u64)0; | |
179 | ||
180 | struct platform_device pxa_device_fb = { | |
181 | .name = "pxa2xx-fb", | |
182 | .id = -1, | |
183 | .dev = { | |
184 | .dma_mask = &fb_dma_mask, | |
185 | .coherent_dma_mask = 0xffffffff, | |
186 | }, | |
187 | .num_resources = ARRAY_SIZE(pxafb_resources), | |
188 | .resource = pxafb_resources, | |
189 | }; | |
190 | ||
4321e1a1 | 191 | void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info) |
8f58de7c | 192 | { |
4321e1a1 | 193 | pxa_device_fb.dev.parent = parent; |
8f58de7c | 194 | pxa_register_device(&pxa_device_fb, info); |
195 | } | |
196 | ||
8f58de7c | 197 | static struct resource pxa_resource_ffuart[] = { |
198 | { | |
02f65262 EM |
199 | .start = 0x40100000, |
200 | .end = 0x40100023, | |
8f58de7c | 201 | .flags = IORESOURCE_MEM, |
202 | }, { | |
203 | .start = IRQ_FFUART, | |
204 | .end = IRQ_FFUART, | |
205 | .flags = IORESOURCE_IRQ, | |
206 | } | |
207 | }; | |
208 | ||
cc155c6f | 209 | struct platform_device pxa_device_ffuart = { |
8f58de7c | 210 | .name = "pxa2xx-uart", |
211 | .id = 0, | |
212 | .resource = pxa_resource_ffuart, | |
213 | .num_resources = ARRAY_SIZE(pxa_resource_ffuart), | |
214 | }; | |
215 | ||
cc155c6f RK |
216 | void __init pxa_set_ffuart_info(void *info) |
217 | { | |
218 | pxa_register_device(&pxa_device_ffuart, info); | |
219 | } | |
220 | ||
8f58de7c | 221 | static struct resource pxa_resource_btuart[] = { |
222 | { | |
02f65262 EM |
223 | .start = 0x40200000, |
224 | .end = 0x40200023, | |
8f58de7c | 225 | .flags = IORESOURCE_MEM, |
226 | }, { | |
227 | .start = IRQ_BTUART, | |
228 | .end = IRQ_BTUART, | |
229 | .flags = IORESOURCE_IRQ, | |
230 | } | |
231 | }; | |
232 | ||
233 | struct platform_device pxa_device_btuart = { | |
234 | .name = "pxa2xx-uart", | |
235 | .id = 1, | |
236 | .resource = pxa_resource_btuart, | |
237 | .num_resources = ARRAY_SIZE(pxa_resource_btuart), | |
238 | }; | |
239 | ||
cc155c6f RK |
240 | void __init pxa_set_btuart_info(void *info) |
241 | { | |
242 | pxa_register_device(&pxa_device_btuart, info); | |
243 | } | |
244 | ||
8f58de7c | 245 | static struct resource pxa_resource_stuart[] = { |
246 | { | |
02f65262 EM |
247 | .start = 0x40700000, |
248 | .end = 0x40700023, | |
8f58de7c | 249 | .flags = IORESOURCE_MEM, |
250 | }, { | |
251 | .start = IRQ_STUART, | |
252 | .end = IRQ_STUART, | |
253 | .flags = IORESOURCE_IRQ, | |
254 | } | |
255 | }; | |
256 | ||
257 | struct platform_device pxa_device_stuart = { | |
258 | .name = "pxa2xx-uart", | |
259 | .id = 2, | |
260 | .resource = pxa_resource_stuart, | |
261 | .num_resources = ARRAY_SIZE(pxa_resource_stuart), | |
262 | }; | |
263 | ||
cc155c6f RK |
264 | void __init pxa_set_stuart_info(void *info) |
265 | { | |
266 | pxa_register_device(&pxa_device_stuart, info); | |
267 | } | |
268 | ||
8f58de7c | 269 | static struct resource pxa_resource_hwuart[] = { |
270 | { | |
02f65262 EM |
271 | .start = 0x41600000, |
272 | .end = 0x4160002F, | |
8f58de7c | 273 | .flags = IORESOURCE_MEM, |
274 | }, { | |
275 | .start = IRQ_HWUART, | |
276 | .end = IRQ_HWUART, | |
277 | .flags = IORESOURCE_IRQ, | |
278 | } | |
279 | }; | |
280 | ||
281 | struct platform_device pxa_device_hwuart = { | |
282 | .name = "pxa2xx-uart", | |
283 | .id = 3, | |
284 | .resource = pxa_resource_hwuart, | |
285 | .num_resources = ARRAY_SIZE(pxa_resource_hwuart), | |
286 | }; | |
287 | ||
cc155c6f RK |
288 | void __init pxa_set_hwuart_info(void *info) |
289 | { | |
290 | if (cpu_is_pxa255()) | |
291 | pxa_register_device(&pxa_device_hwuart, info); | |
292 | else | |
293 | pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware"); | |
294 | } | |
295 | ||
8f58de7c | 296 | static struct resource pxai2c_resources[] = { |
297 | { | |
298 | .start = 0x40301680, | |
299 | .end = 0x403016a3, | |
300 | .flags = IORESOURCE_MEM, | |
301 | }, { | |
302 | .start = IRQ_I2C, | |
303 | .end = IRQ_I2C, | |
304 | .flags = IORESOURCE_IRQ, | |
305 | }, | |
306 | }; | |
307 | ||
308 | struct platform_device pxa_device_i2c = { | |
309 | .name = "pxa2xx-i2c", | |
310 | .id = 0, | |
311 | .resource = pxai2c_resources, | |
312 | .num_resources = ARRAY_SIZE(pxai2c_resources), | |
313 | }; | |
314 | ||
315 | void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) | |
316 | { | |
317 | pxa_register_device(&pxa_device_i2c, info); | |
318 | } | |
319 | ||
99464293 EM |
320 | #ifdef CONFIG_PXA27x |
321 | static struct resource pxa27x_resources_i2c_power[] = { | |
322 | { | |
323 | .start = 0x40f00180, | |
324 | .end = 0x40f001a3, | |
325 | .flags = IORESOURCE_MEM, | |
326 | }, { | |
327 | .start = IRQ_PWRI2C, | |
328 | .end = IRQ_PWRI2C, | |
329 | .flags = IORESOURCE_IRQ, | |
330 | }, | |
331 | }; | |
332 | ||
333 | struct platform_device pxa27x_device_i2c_power = { | |
334 | .name = "pxa2xx-i2c", | |
335 | .id = 1, | |
336 | .resource = pxa27x_resources_i2c_power, | |
337 | .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power), | |
338 | }; | |
339 | #endif | |
340 | ||
8f58de7c | 341 | static struct resource pxai2s_resources[] = { |
342 | { | |
343 | .start = 0x40400000, | |
344 | .end = 0x40400083, | |
345 | .flags = IORESOURCE_MEM, | |
346 | }, { | |
347 | .start = IRQ_I2S, | |
348 | .end = IRQ_I2S, | |
349 | .flags = IORESOURCE_IRQ, | |
350 | }, | |
351 | }; | |
352 | ||
353 | struct platform_device pxa_device_i2s = { | |
354 | .name = "pxa2xx-i2s", | |
355 | .id = -1, | |
356 | .resource = pxai2s_resources, | |
357 | .num_resources = ARRAY_SIZE(pxai2s_resources), | |
358 | }; | |
359 | ||
f0fba2ad LG |
360 | struct platform_device pxa_device_asoc_ssp1 = { |
361 | .name = "pxa-ssp-dai", | |
362 | .id = 0, | |
363 | }; | |
364 | ||
365 | struct platform_device pxa_device_asoc_ssp2= { | |
366 | .name = "pxa-ssp-dai", | |
367 | .id = 1, | |
368 | }; | |
369 | ||
370 | struct platform_device pxa_device_asoc_ssp3 = { | |
371 | .name = "pxa-ssp-dai", | |
372 | .id = 2, | |
373 | }; | |
374 | ||
375 | struct platform_device pxa_device_asoc_ssp4 = { | |
376 | .name = "pxa-ssp-dai", | |
377 | .id = 3, | |
378 | }; | |
379 | ||
380 | struct platform_device pxa_device_asoc_platform = { | |
381 | .name = "pxa-pcm-audio", | |
382 | .id = -1, | |
383 | }; | |
384 | ||
8f58de7c | 385 | static u64 pxaficp_dmamask = ~(u32)0; |
386 | ||
121f3f9b RH |
387 | static struct resource pxa_ir_resources[] = { |
388 | [0] = { | |
389 | .start = IRQ_STUART, | |
390 | .end = IRQ_STUART, | |
391 | .flags = IORESOURCE_IRQ, | |
392 | }, | |
393 | [1] = { | |
394 | .start = IRQ_ICP, | |
395 | .end = IRQ_ICP, | |
396 | .flags = IORESOURCE_IRQ, | |
397 | }, | |
48a629da RJ |
398 | [3] = { |
399 | .start = 0x40800000, | |
400 | .end = 0x4080001b, | |
401 | .flags = IORESOURCE_MEM, | |
402 | }, | |
403 | [4] = { | |
404 | .start = 0x40700000, | |
405 | .end = 0x40700023, | |
406 | .flags = IORESOURCE_MEM, | |
407 | }, | |
408 | [5] = { | |
409 | .start = 17, | |
410 | .end = 17, | |
411 | .flags = IORESOURCE_DMA, | |
412 | }, | |
413 | [6] = { | |
414 | .start = 18, | |
415 | .end = 18, | |
416 | .flags = IORESOURCE_DMA, | |
417 | }, | |
121f3f9b RH |
418 | }; |
419 | ||
8f58de7c | 420 | struct platform_device pxa_device_ficp = { |
421 | .name = "pxa2xx-ir", | |
422 | .id = -1, | |
121f3f9b RH |
423 | .num_resources = ARRAY_SIZE(pxa_ir_resources), |
424 | .resource = pxa_ir_resources, | |
8f58de7c | 425 | .dev = { |
426 | .dma_mask = &pxaficp_dmamask, | |
427 | .coherent_dma_mask = 0xffffffff, | |
428 | }, | |
429 | }; | |
430 | ||
431 | void __init pxa_set_ficp_info(struct pxaficp_platform_data *info) | |
432 | { | |
433 | pxa_register_device(&pxa_device_ficp, info); | |
434 | } | |
435 | ||
72493146 RJ |
436 | static struct resource pxa_rtc_resources[] = { |
437 | [0] = { | |
438 | .start = 0x40900000, | |
439 | .end = 0x40900000 + 0x3b, | |
440 | .flags = IORESOURCE_MEM, | |
441 | }, | |
442 | [1] = { | |
443 | .start = IRQ_RTC1Hz, | |
444 | .end = IRQ_RTC1Hz, | |
3888c090 | 445 | .name = "rtc 1Hz", |
72493146 RJ |
446 | .flags = IORESOURCE_IRQ, |
447 | }, | |
448 | [2] = { | |
449 | .start = IRQ_RTCAlrm, | |
450 | .end = IRQ_RTCAlrm, | |
3888c090 | 451 | .name = "rtc alarm", |
72493146 RJ |
452 | .flags = IORESOURCE_IRQ, |
453 | }, | |
454 | }; | |
455 | ||
72493146 RJ |
456 | struct platform_device pxa_device_rtc = { |
457 | .name = "pxa-rtc", | |
458 | .id = -1, | |
459 | .num_resources = ARRAY_SIZE(pxa_rtc_resources), | |
460 | .resource = pxa_rtc_resources, | |
461 | }; | |
462 | ||
3888c090 HZ |
463 | struct platform_device sa1100_device_rtc = { |
464 | .name = "sa1100-rtc", | |
465 | .id = -1, | |
2c4fabec RH |
466 | .num_resources = ARRAY_SIZE(pxa_rtc_resources), |
467 | .resource = pxa_rtc_resources, | |
3888c090 HZ |
468 | }; |
469 | ||
9f19d638 MB |
470 | static struct resource pxa_ac97_resources[] = { |
471 | [0] = { | |
472 | .start = 0x40500000, | |
473 | .end = 0x40500000 + 0xfff, | |
474 | .flags = IORESOURCE_MEM, | |
475 | }, | |
476 | [1] = { | |
477 | .start = IRQ_AC97, | |
478 | .end = IRQ_AC97, | |
479 | .flags = IORESOURCE_IRQ, | |
480 | }, | |
481 | }; | |
482 | ||
483 | static u64 pxa_ac97_dmamask = 0xffffffffUL; | |
484 | ||
485 | struct platform_device pxa_device_ac97 = { | |
486 | .name = "pxa2xx-ac97", | |
487 | .id = -1, | |
488 | .dev = { | |
489 | .dma_mask = &pxa_ac97_dmamask, | |
490 | .coherent_dma_mask = 0xffffffff, | |
491 | }, | |
492 | .num_resources = ARRAY_SIZE(pxa_ac97_resources), | |
493 | .resource = pxa_ac97_resources, | |
494 | }; | |
495 | ||
496 | void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops) | |
497 | { | |
498 | pxa_register_device(&pxa_device_ac97, ops); | |
499 | } | |
500 | ||
8f58de7c | 501 | #ifdef CONFIG_PXA25x |
502 | ||
75540c1a | 503 | static struct resource pxa25x_resource_pwm0[] = { |
504 | [0] = { | |
505 | .start = 0x40b00000, | |
506 | .end = 0x40b0000f, | |
507 | .flags = IORESOURCE_MEM, | |
508 | }, | |
509 | }; | |
510 | ||
511 | struct platform_device pxa25x_device_pwm0 = { | |
512 | .name = "pxa25x-pwm", | |
513 | .id = 0, | |
514 | .resource = pxa25x_resource_pwm0, | |
515 | .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0), | |
516 | }; | |
517 | ||
518 | static struct resource pxa25x_resource_pwm1[] = { | |
519 | [0] = { | |
520 | .start = 0x40c00000, | |
521 | .end = 0x40c0000f, | |
522 | .flags = IORESOURCE_MEM, | |
523 | }, | |
524 | }; | |
525 | ||
526 | struct platform_device pxa25x_device_pwm1 = { | |
527 | .name = "pxa25x-pwm", | |
528 | .id = 1, | |
529 | .resource = pxa25x_resource_pwm1, | |
530 | .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1), | |
531 | }; | |
532 | ||
8f58de7c | 533 | static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32); |
534 | ||
535 | static struct resource pxa25x_resource_ssp[] = { | |
536 | [0] = { | |
537 | .start = 0x41000000, | |
538 | .end = 0x4100001f, | |
539 | .flags = IORESOURCE_MEM, | |
540 | }, | |
541 | [1] = { | |
542 | .start = IRQ_SSP, | |
543 | .end = IRQ_SSP, | |
544 | .flags = IORESOURCE_IRQ, | |
545 | }, | |
546 | [2] = { | |
547 | /* DRCMR for RX */ | |
548 | .start = 13, | |
549 | .end = 13, | |
550 | .flags = IORESOURCE_DMA, | |
551 | }, | |
552 | [3] = { | |
553 | /* DRCMR for TX */ | |
554 | .start = 14, | |
555 | .end = 14, | |
556 | .flags = IORESOURCE_DMA, | |
557 | }, | |
558 | }; | |
559 | ||
560 | struct platform_device pxa25x_device_ssp = { | |
561 | .name = "pxa25x-ssp", | |
562 | .id = 0, | |
563 | .dev = { | |
564 | .dma_mask = &pxa25x_ssp_dma_mask, | |
565 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
566 | }, | |
567 | .resource = pxa25x_resource_ssp, | |
568 | .num_resources = ARRAY_SIZE(pxa25x_resource_ssp), | |
569 | }; | |
570 | ||
571 | static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32); | |
572 | ||
573 | static struct resource pxa25x_resource_nssp[] = { | |
574 | [0] = { | |
575 | .start = 0x41400000, | |
576 | .end = 0x4140002f, | |
577 | .flags = IORESOURCE_MEM, | |
578 | }, | |
579 | [1] = { | |
580 | .start = IRQ_NSSP, | |
581 | .end = IRQ_NSSP, | |
582 | .flags = IORESOURCE_IRQ, | |
583 | }, | |
584 | [2] = { | |
585 | /* DRCMR for RX */ | |
586 | .start = 15, | |
587 | .end = 15, | |
588 | .flags = IORESOURCE_DMA, | |
589 | }, | |
590 | [3] = { | |
591 | /* DRCMR for TX */ | |
592 | .start = 16, | |
593 | .end = 16, | |
594 | .flags = IORESOURCE_DMA, | |
595 | }, | |
596 | }; | |
597 | ||
598 | struct platform_device pxa25x_device_nssp = { | |
599 | .name = "pxa25x-nssp", | |
600 | .id = 1, | |
601 | .dev = { | |
602 | .dma_mask = &pxa25x_nssp_dma_mask, | |
603 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
604 | }, | |
605 | .resource = pxa25x_resource_nssp, | |
606 | .num_resources = ARRAY_SIZE(pxa25x_resource_nssp), | |
607 | }; | |
608 | ||
609 | static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32); | |
610 | ||
611 | static struct resource pxa25x_resource_assp[] = { | |
612 | [0] = { | |
613 | .start = 0x41500000, | |
614 | .end = 0x4150002f, | |
615 | .flags = IORESOURCE_MEM, | |
616 | }, | |
617 | [1] = { | |
618 | .start = IRQ_ASSP, | |
619 | .end = IRQ_ASSP, | |
620 | .flags = IORESOURCE_IRQ, | |
621 | }, | |
622 | [2] = { | |
623 | /* DRCMR for RX */ | |
624 | .start = 23, | |
625 | .end = 23, | |
626 | .flags = IORESOURCE_DMA, | |
627 | }, | |
628 | [3] = { | |
629 | /* DRCMR for TX */ | |
630 | .start = 24, | |
631 | .end = 24, | |
632 | .flags = IORESOURCE_DMA, | |
633 | }, | |
634 | }; | |
635 | ||
636 | struct platform_device pxa25x_device_assp = { | |
637 | /* ASSP is basically equivalent to NSSP */ | |
638 | .name = "pxa25x-nssp", | |
639 | .id = 2, | |
640 | .dev = { | |
641 | .dma_mask = &pxa25x_assp_dma_mask, | |
642 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
643 | }, | |
644 | .resource = pxa25x_resource_assp, | |
645 | .num_resources = ARRAY_SIZE(pxa25x_resource_assp), | |
646 | }; | |
647 | #endif /* CONFIG_PXA25x */ | |
648 | ||
649 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | |
a4553358 | 650 | static struct resource pxa27x_resource_camera[] = { |
37320980 | 651 | [0] = { |
a4553358 HZ |
652 | .start = 0x50000000, |
653 | .end = 0x50000fff, | |
37320980 | 654 | .flags = IORESOURCE_MEM, |
655 | }, | |
656 | [1] = { | |
a4553358 HZ |
657 | .start = IRQ_CAMERA, |
658 | .end = IRQ_CAMERA, | |
37320980 | 659 | .flags = IORESOURCE_IRQ, |
660 | }, | |
661 | }; | |
662 | ||
a4553358 HZ |
663 | static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32); |
664 | ||
665 | static struct platform_device pxa27x_device_camera = { | |
666 | .name = "pxa27x-camera", | |
667 | .id = 0, /* This is used to put cameras on this interface */ | |
668 | .dev = { | |
669 | .dma_mask = &pxa27x_dma_mask_camera, | |
670 | .coherent_dma_mask = 0xffffffff, | |
671 | }, | |
672 | .num_resources = ARRAY_SIZE(pxa27x_resource_camera), | |
673 | .resource = pxa27x_resource_camera, | |
37320980 | 674 | }; |
675 | ||
a4553358 | 676 | void __init pxa_set_camera_info(struct pxacamera_platform_data *info) |
37320980 | 677 | { |
a4553358 | 678 | pxa_register_device(&pxa27x_device_camera, info); |
37320980 | 679 | } |
680 | ||
ec68e45b | 681 | static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32); |
682 | ||
683 | static struct resource pxa27x_resource_ohci[] = { | |
684 | [0] = { | |
685 | .start = 0x4C000000, | |
686 | .end = 0x4C00ff6f, | |
687 | .flags = IORESOURCE_MEM, | |
688 | }, | |
689 | [1] = { | |
690 | .start = IRQ_USBH1, | |
691 | .end = IRQ_USBH1, | |
692 | .flags = IORESOURCE_IRQ, | |
693 | }, | |
694 | }; | |
695 | ||
696 | struct platform_device pxa27x_device_ohci = { | |
697 | .name = "pxa27x-ohci", | |
698 | .id = -1, | |
699 | .dev = { | |
700 | .dma_mask = &pxa27x_ohci_dma_mask, | |
701 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
702 | }, | |
703 | .num_resources = ARRAY_SIZE(pxa27x_resource_ohci), | |
704 | .resource = pxa27x_resource_ohci, | |
705 | }; | |
706 | ||
707 | void __init pxa_set_ohci_info(struct pxaohci_platform_data *info) | |
708 | { | |
709 | pxa_register_device(&pxa27x_device_ohci, info); | |
710 | } | |
a4553358 HZ |
711 | #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ |
712 | ||
49ea7fc0 | 713 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
a4553358 HZ |
714 | static struct resource pxa27x_resource_keypad[] = { |
715 | [0] = { | |
716 | .start = 0x41500000, | |
717 | .end = 0x4150004c, | |
718 | .flags = IORESOURCE_MEM, | |
719 | }, | |
720 | [1] = { | |
721 | .start = IRQ_KEYPAD, | |
722 | .end = IRQ_KEYPAD, | |
723 | .flags = IORESOURCE_IRQ, | |
724 | }, | |
725 | }; | |
726 | ||
727 | struct platform_device pxa27x_device_keypad = { | |
728 | .name = "pxa27x-keypad", | |
729 | .id = -1, | |
730 | .resource = pxa27x_resource_keypad, | |
731 | .num_resources = ARRAY_SIZE(pxa27x_resource_keypad), | |
732 | }; | |
733 | ||
734 | void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info) | |
735 | { | |
736 | pxa_register_device(&pxa27x_device_keypad, info); | |
737 | } | |
ec68e45b | 738 | |
8f58de7c | 739 | static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32); |
740 | ||
741 | static struct resource pxa27x_resource_ssp1[] = { | |
742 | [0] = { | |
743 | .start = 0x41000000, | |
744 | .end = 0x4100003f, | |
745 | .flags = IORESOURCE_MEM, | |
746 | }, | |
747 | [1] = { | |
748 | .start = IRQ_SSP, | |
749 | .end = IRQ_SSP, | |
750 | .flags = IORESOURCE_IRQ, | |
751 | }, | |
752 | [2] = { | |
753 | /* DRCMR for RX */ | |
754 | .start = 13, | |
755 | .end = 13, | |
756 | .flags = IORESOURCE_DMA, | |
757 | }, | |
758 | [3] = { | |
759 | /* DRCMR for TX */ | |
760 | .start = 14, | |
761 | .end = 14, | |
762 | .flags = IORESOURCE_DMA, | |
763 | }, | |
764 | }; | |
765 | ||
766 | struct platform_device pxa27x_device_ssp1 = { | |
767 | .name = "pxa27x-ssp", | |
768 | .id = 0, | |
769 | .dev = { | |
770 | .dma_mask = &pxa27x_ssp1_dma_mask, | |
771 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
772 | }, | |
773 | .resource = pxa27x_resource_ssp1, | |
774 | .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1), | |
775 | }; | |
776 | ||
777 | static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32); | |
778 | ||
779 | static struct resource pxa27x_resource_ssp2[] = { | |
780 | [0] = { | |
781 | .start = 0x41700000, | |
782 | .end = 0x4170003f, | |
783 | .flags = IORESOURCE_MEM, | |
784 | }, | |
785 | [1] = { | |
786 | .start = IRQ_SSP2, | |
787 | .end = IRQ_SSP2, | |
788 | .flags = IORESOURCE_IRQ, | |
789 | }, | |
790 | [2] = { | |
791 | /* DRCMR for RX */ | |
792 | .start = 15, | |
793 | .end = 15, | |
794 | .flags = IORESOURCE_DMA, | |
795 | }, | |
796 | [3] = { | |
797 | /* DRCMR for TX */ | |
798 | .start = 16, | |
799 | .end = 16, | |
800 | .flags = IORESOURCE_DMA, | |
801 | }, | |
802 | }; | |
803 | ||
804 | struct platform_device pxa27x_device_ssp2 = { | |
805 | .name = "pxa27x-ssp", | |
806 | .id = 1, | |
807 | .dev = { | |
808 | .dma_mask = &pxa27x_ssp2_dma_mask, | |
809 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
810 | }, | |
811 | .resource = pxa27x_resource_ssp2, | |
812 | .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2), | |
813 | }; | |
814 | ||
815 | static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32); | |
816 | ||
817 | static struct resource pxa27x_resource_ssp3[] = { | |
818 | [0] = { | |
819 | .start = 0x41900000, | |
820 | .end = 0x4190003f, | |
821 | .flags = IORESOURCE_MEM, | |
822 | }, | |
823 | [1] = { | |
824 | .start = IRQ_SSP3, | |
825 | .end = IRQ_SSP3, | |
826 | .flags = IORESOURCE_IRQ, | |
827 | }, | |
828 | [2] = { | |
829 | /* DRCMR for RX */ | |
830 | .start = 66, | |
831 | .end = 66, | |
832 | .flags = IORESOURCE_DMA, | |
833 | }, | |
834 | [3] = { | |
835 | /* DRCMR for TX */ | |
836 | .start = 67, | |
837 | .end = 67, | |
838 | .flags = IORESOURCE_DMA, | |
839 | }, | |
840 | }; | |
841 | ||
842 | struct platform_device pxa27x_device_ssp3 = { | |
843 | .name = "pxa27x-ssp", | |
844 | .id = 2, | |
845 | .dev = { | |
846 | .dma_mask = &pxa27x_ssp3_dma_mask, | |
847 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
848 | }, | |
849 | .resource = pxa27x_resource_ssp3, | |
850 | .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3), | |
851 | }; | |
3f3acefb | 852 | |
75540c1a | 853 | static struct resource pxa27x_resource_pwm0[] = { |
854 | [0] = { | |
855 | .start = 0x40b00000, | |
856 | .end = 0x40b0001f, | |
857 | .flags = IORESOURCE_MEM, | |
858 | }, | |
859 | }; | |
860 | ||
861 | struct platform_device pxa27x_device_pwm0 = { | |
862 | .name = "pxa27x-pwm", | |
863 | .id = 0, | |
864 | .resource = pxa27x_resource_pwm0, | |
865 | .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0), | |
866 | }; | |
867 | ||
868 | static struct resource pxa27x_resource_pwm1[] = { | |
869 | [0] = { | |
870 | .start = 0x40c00000, | |
871 | .end = 0x40c0001f, | |
872 | .flags = IORESOURCE_MEM, | |
873 | }, | |
874 | }; | |
875 | ||
876 | struct platform_device pxa27x_device_pwm1 = { | |
877 | .name = "pxa27x-pwm", | |
878 | .id = 1, | |
879 | .resource = pxa27x_resource_pwm1, | |
880 | .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1), | |
881 | }; | |
49ea7fc0 | 882 | #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ |
8f58de7c | 883 | |
884 | #ifdef CONFIG_PXA3xx | |
8d33b055 BW |
885 | static struct resource pxa3xx_resources_mci2[] = { |
886 | [0] = { | |
887 | .start = 0x42000000, | |
888 | .end = 0x42000fff, | |
889 | .flags = IORESOURCE_MEM, | |
890 | }, | |
891 | [1] = { | |
892 | .start = IRQ_MMC2, | |
893 | .end = IRQ_MMC2, | |
894 | .flags = IORESOURCE_IRQ, | |
895 | }, | |
896 | [2] = { | |
897 | .start = 93, | |
898 | .end = 93, | |
899 | .flags = IORESOURCE_DMA, | |
900 | }, | |
901 | [3] = { | |
902 | .start = 94, | |
903 | .end = 94, | |
904 | .flags = IORESOURCE_DMA, | |
905 | }, | |
906 | }; | |
907 | ||
908 | struct platform_device pxa3xx_device_mci2 = { | |
909 | .name = "pxa2xx-mci", | |
910 | .id = 1, | |
911 | .dev = { | |
912 | .dma_mask = &pxamci_dmamask, | |
913 | .coherent_dma_mask = 0xffffffff, | |
914 | }, | |
915 | .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2), | |
916 | .resource = pxa3xx_resources_mci2, | |
917 | }; | |
918 | ||
919 | void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info) | |
920 | { | |
921 | pxa_register_device(&pxa3xx_device_mci2, info); | |
922 | } | |
923 | ||
5a1f21b1 BW |
924 | static struct resource pxa3xx_resources_mci3[] = { |
925 | [0] = { | |
926 | .start = 0x42500000, | |
927 | .end = 0x42500fff, | |
928 | .flags = IORESOURCE_MEM, | |
929 | }, | |
930 | [1] = { | |
931 | .start = IRQ_MMC3, | |
932 | .end = IRQ_MMC3, | |
933 | .flags = IORESOURCE_IRQ, | |
934 | }, | |
935 | [2] = { | |
936 | .start = 100, | |
937 | .end = 100, | |
938 | .flags = IORESOURCE_DMA, | |
939 | }, | |
940 | [3] = { | |
941 | .start = 101, | |
942 | .end = 101, | |
943 | .flags = IORESOURCE_DMA, | |
944 | }, | |
945 | }; | |
946 | ||
947 | struct platform_device pxa3xx_device_mci3 = { | |
948 | .name = "pxa2xx-mci", | |
949 | .id = 2, | |
950 | .dev = { | |
951 | .dma_mask = &pxamci_dmamask, | |
952 | .coherent_dma_mask = 0xffffffff, | |
953 | }, | |
954 | .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3), | |
955 | .resource = pxa3xx_resources_mci3, | |
956 | }; | |
957 | ||
958 | void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info) | |
959 | { | |
960 | pxa_register_device(&pxa3xx_device_mci3, info); | |
961 | } | |
962 | ||
a4553358 HZ |
963 | static struct resource pxa3xx_resources_gcu[] = { |
964 | { | |
965 | .start = 0x54000000, | |
966 | .end = 0x54000fff, | |
967 | .flags = IORESOURCE_MEM, | |
968 | }, | |
969 | { | |
970 | .start = IRQ_GCU, | |
971 | .end = IRQ_GCU, | |
972 | .flags = IORESOURCE_IRQ, | |
973 | }, | |
974 | }; | |
975 | ||
976 | static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32); | |
977 | ||
978 | struct platform_device pxa3xx_device_gcu = { | |
979 | .name = "pxa3xx-gcu", | |
980 | .id = -1, | |
981 | .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu), | |
982 | .resource = pxa3xx_resources_gcu, | |
983 | .dev = { | |
984 | .dma_mask = &pxa3xx_gcu_dmamask, | |
985 | .coherent_dma_mask = 0xffffffff, | |
986 | }, | |
987 | }; | |
988 | ||
989 | #endif /* CONFIG_PXA3xx */ | |
990 | ||
49ea7fc0 | 991 | #if defined(CONFIG_PXA3xx) |
a4553358 HZ |
992 | static struct resource pxa3xx_resources_i2c_power[] = { |
993 | { | |
994 | .start = 0x40f500c0, | |
995 | .end = 0x40f500d3, | |
996 | .flags = IORESOURCE_MEM, | |
997 | }, { | |
998 | .start = IRQ_PWRI2C, | |
999 | .end = IRQ_PWRI2C, | |
1000 | .flags = IORESOURCE_IRQ, | |
1001 | }, | |
1002 | }; | |
1003 | ||
1004 | struct platform_device pxa3xx_device_i2c_power = { | |
1005 | .name = "pxa3xx-pwri2c", | |
1006 | .id = 1, | |
1007 | .resource = pxa3xx_resources_i2c_power, | |
1008 | .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power), | |
1009 | }; | |
1010 | ||
9ae819a8 EM |
1011 | static struct resource pxa3xx_resources_nand[] = { |
1012 | [0] = { | |
1013 | .start = 0x43100000, | |
1014 | .end = 0x43100053, | |
1015 | .flags = IORESOURCE_MEM, | |
1016 | }, | |
1017 | [1] = { | |
1018 | .start = IRQ_NAND, | |
1019 | .end = IRQ_NAND, | |
1020 | .flags = IORESOURCE_IRQ, | |
1021 | }, | |
1022 | [2] = { | |
1023 | /* DRCMR for Data DMA */ | |
1024 | .start = 97, | |
1025 | .end = 97, | |
1026 | .flags = IORESOURCE_DMA, | |
1027 | }, | |
1028 | [3] = { | |
1029 | /* DRCMR for Command DMA */ | |
1030 | .start = 99, | |
1031 | .end = 99, | |
1032 | .flags = IORESOURCE_DMA, | |
1033 | }, | |
1034 | }; | |
1035 | ||
1036 | static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32); | |
1037 | ||
1038 | struct platform_device pxa3xx_device_nand = { | |
1039 | .name = "pxa3xx-nand", | |
1040 | .id = -1, | |
1041 | .dev = { | |
1042 | .dma_mask = &pxa3xx_nand_dma_mask, | |
1043 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1044 | }, | |
1045 | .num_resources = ARRAY_SIZE(pxa3xx_resources_nand), | |
1046 | .resource = pxa3xx_resources_nand, | |
1047 | }; | |
1048 | ||
1049 | void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info) | |
1050 | { | |
1051 | pxa_register_device(&pxa3xx_device_nand, info); | |
1052 | } | |
1ff2c33e | 1053 | |
a4553358 HZ |
1054 | static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32); |
1055 | ||
1056 | static struct resource pxa3xx_resource_ssp4[] = { | |
1057 | [0] = { | |
1058 | .start = 0x41a00000, | |
1059 | .end = 0x41a0003f, | |
1ff2c33e DM |
1060 | .flags = IORESOURCE_MEM, |
1061 | }, | |
a4553358 HZ |
1062 | [1] = { |
1063 | .start = IRQ_SSP4, | |
1064 | .end = IRQ_SSP4, | |
1ff2c33e DM |
1065 | .flags = IORESOURCE_IRQ, |
1066 | }, | |
a4553358 HZ |
1067 | [2] = { |
1068 | /* DRCMR for RX */ | |
1069 | .start = 2, | |
1070 | .end = 2, | |
1071 | .flags = IORESOURCE_DMA, | |
1072 | }, | |
1073 | [3] = { | |
1074 | /* DRCMR for TX */ | |
1075 | .start = 3, | |
1076 | .end = 3, | |
1077 | .flags = IORESOURCE_DMA, | |
1078 | }, | |
1ff2c33e DM |
1079 | }; |
1080 | ||
0da0e227 DM |
1081 | /* |
1082 | * PXA3xx SSP is basically equivalent to PXA27x. | |
1083 | * However, we need to register the device by the correct name in order to | |
1084 | * make the driver set the correct internal type, hence we provide specific | |
1085 | * platform_devices for each of them. | |
1086 | */ | |
1087 | struct platform_device pxa3xx_device_ssp1 = { | |
1088 | .name = "pxa3xx-ssp", | |
1089 | .id = 0, | |
1090 | .dev = { | |
1091 | .dma_mask = &pxa27x_ssp1_dma_mask, | |
1092 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1093 | }, | |
1094 | .resource = pxa27x_resource_ssp1, | |
1095 | .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1), | |
1096 | }; | |
1097 | ||
1098 | struct platform_device pxa3xx_device_ssp2 = { | |
1099 | .name = "pxa3xx-ssp", | |
1100 | .id = 1, | |
1101 | .dev = { | |
1102 | .dma_mask = &pxa27x_ssp2_dma_mask, | |
1103 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1104 | }, | |
1105 | .resource = pxa27x_resource_ssp2, | |
1106 | .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2), | |
1107 | }; | |
1108 | ||
1109 | struct platform_device pxa3xx_device_ssp3 = { | |
1110 | .name = "pxa3xx-ssp", | |
1111 | .id = 2, | |
1112 | .dev = { | |
1113 | .dma_mask = &pxa27x_ssp3_dma_mask, | |
1114 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1115 | }, | |
1116 | .resource = pxa27x_resource_ssp3, | |
1117 | .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3), | |
1118 | }; | |
1119 | ||
a4553358 | 1120 | struct platform_device pxa3xx_device_ssp4 = { |
0da0e227 | 1121 | .name = "pxa3xx-ssp", |
a4553358 | 1122 | .id = 3, |
1ff2c33e | 1123 | .dev = { |
a4553358 HZ |
1124 | .dma_mask = &pxa3xx_ssp4_dma_mask, |
1125 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1ff2c33e | 1126 | }, |
a4553358 HZ |
1127 | .resource = pxa3xx_resource_ssp4, |
1128 | .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4), | |
1ff2c33e | 1129 | }; |
49ea7fc0 | 1130 | #endif /* CONFIG_PXA3xx */ |
e172274c | 1131 | |
157d2644 HZ |
1132 | struct resource pxa_resource_gpio[] = { |
1133 | { | |
1134 | .start = 0x40e00000, | |
1135 | .end = 0x40e0ffff, | |
1136 | .flags = IORESOURCE_MEM, | |
1137 | }, { | |
1138 | .start = IRQ_GPIO0, | |
1139 | .end = IRQ_GPIO0, | |
1140 | .name = "gpio0", | |
1141 | .flags = IORESOURCE_IRQ, | |
1142 | }, { | |
1143 | .start = IRQ_GPIO1, | |
1144 | .end = IRQ_GPIO1, | |
1145 | .name = "gpio1", | |
1146 | .flags = IORESOURCE_IRQ, | |
1147 | }, { | |
1148 | .start = IRQ_GPIO_2_x, | |
1149 | .end = IRQ_GPIO_2_x, | |
1150 | .name = "gpio_mux", | |
1151 | .flags = IORESOURCE_IRQ, | |
1152 | }, | |
1153 | }; | |
1154 | ||
2cab0292 HZ |
1155 | struct platform_device pxa25x_device_gpio = { |
1156 | #ifdef CONFIG_CPU_PXA26x | |
1157 | .name = "pxa26x-gpio", | |
1158 | #else | |
1159 | .name = "pxa25x-gpio", | |
1160 | #endif | |
1161 | .id = -1, | |
1162 | .num_resources = ARRAY_SIZE(pxa_resource_gpio), | |
1163 | .resource = pxa_resource_gpio, | |
1164 | }; | |
1165 | ||
1166 | struct platform_device pxa27x_device_gpio = { | |
1167 | .name = "pxa27x-gpio", | |
1168 | .id = -1, | |
1169 | .num_resources = ARRAY_SIZE(pxa_resource_gpio), | |
1170 | .resource = pxa_resource_gpio, | |
1171 | }; | |
1172 | ||
1173 | struct platform_device pxa3xx_device_gpio = { | |
1174 | .name = "pxa3xx-gpio", | |
1175 | .id = -1, | |
1176 | .num_resources = ARRAY_SIZE(pxa_resource_gpio), | |
1177 | .resource = pxa_resource_gpio, | |
1178 | }; | |
1179 | ||
1180 | struct platform_device pxa93x_device_gpio = { | |
1181 | .name = "pxa93x-gpio", | |
157d2644 HZ |
1182 | .id = -1, |
1183 | .num_resources = ARRAY_SIZE(pxa_resource_gpio), | |
1184 | .resource = pxa_resource_gpio, | |
1185 | }; | |
1186 | ||
e172274c GL |
1187 | /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1. |
1188 | * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */ | |
1189 | void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info) | |
1190 | { | |
1191 | struct platform_device *pd; | |
1192 | ||
1193 | pd = platform_device_alloc("pxa2xx-spi", id); | |
1194 | if (pd == NULL) { | |
1195 | printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n", | |
1196 | id); | |
1197 | return; | |
1198 | } | |
1199 | ||
1200 | pd->dev.platform_data = info; | |
1201 | platform_device_add(pd); | |
1202 | } | |
4be0856f RJ |
1203 | |
1204 | static struct mmp_dma_platdata pxa_dma_pdata = { | |
1205 | .dma_channels = 0, | |
1206 | }; | |
1207 | ||
1208 | static struct resource pxa_dma_resource[] = { | |
1209 | [0] = { | |
1210 | .start = 0x40000000, | |
1211 | .end = 0x4000ffff, | |
1212 | .flags = IORESOURCE_MEM, | |
1213 | }, | |
1214 | [1] = { | |
1215 | .start = IRQ_DMA, | |
1216 | .end = IRQ_DMA, | |
1217 | .flags = IORESOURCE_IRQ, | |
1218 | }, | |
1219 | }; | |
1220 | ||
1221 | static u64 pxadma_dmamask = 0xffffffffUL; | |
1222 | ||
1223 | static struct platform_device pxa2xx_pxa_dma = { | |
1224 | .name = "pxa-dma", | |
1225 | .id = 0, | |
1226 | .dev = { | |
1227 | .dma_mask = &pxadma_dmamask, | |
1228 | .coherent_dma_mask = 0xffffffff, | |
1229 | }, | |
1230 | .num_resources = ARRAY_SIZE(pxa_dma_resource), | |
1231 | .resource = pxa_dma_resource, | |
1232 | }; | |
1233 | ||
1234 | void __init pxa2xx_set_dmac_info(int nb_channels) | |
1235 | { | |
1236 | pxa_dma_pdata.dma_channels = nb_channels; | |
1237 | pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata); | |
1238 | } |