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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
ce4fb7b8 | 2 | #ifndef __ASM_ARCH_REGS_LCD_H |
3 | #define __ASM_ARCH_REGS_LCD_H | |
3692fd0a | 4 | |
a09e64fb | 5 | #include <mach/bitfield.h> |
3692fd0a | 6 | |
ce4fb7b8 | 7 | /* |
8 | * LCD Controller Registers and Bits Definitions | |
9 | */ | |
10 | #define LCCR0 (0x000) /* LCD Controller Control Register 0 */ | |
11 | #define LCCR1 (0x004) /* LCD Controller Control Register 1 */ | |
12 | #define LCCR2 (0x008) /* LCD Controller Control Register 2 */ | |
13 | #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ | |
3c42a449 EM |
14 | #define LCCR4 (0x010) /* LCD Controller Control Register 4 */ |
15 | #define LCCR5 (0x014) /* LCD Controller Control Register 5 */ | |
198fc108 EM |
16 | #define LCSR (0x038) /* LCD Controller Status Register 0 */ |
17 | #define LCSR1 (0x034) /* LCD Controller Status Register 1 */ | |
ce4fb7b8 | 18 | #define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ |
19 | #define TMEDRGBR (0x040) /* TMED RGB Seed Register */ | |
20 | #define TMEDCR (0x044) /* TMED Control Register */ | |
21 | ||
6e354846 EM |
22 | #define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ |
23 | #define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ | |
24 | #define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */ | |
25 | #define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */ | |
26 | #define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */ | |
27 | #define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ | |
28 | #define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */ | |
29 | ||
198fc108 EM |
30 | #define OVL1C1 (0x050) /* Overlay 1 Control Register 1 */ |
31 | #define OVL1C2 (0x060) /* Overlay 1 Control Register 2 */ | |
32 | #define OVL2C1 (0x070) /* Overlay 2 Control Register 1 */ | |
33 | #define OVL2C2 (0x080) /* Overlay 2 Control Register 2 */ | |
34 | ||
3c42a449 EM |
35 | #define CMDCR (0x100) /* Command Control Register */ |
36 | #define PRSR (0x104) /* Panel Read Status Register */ | |
37 | ||
878f5783 | 38 | #define LCCR3_BPP(x) ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0)) |
ce4fb7b8 | 39 | |
40 | #define LCCR3_PDFOR_0 (0 << 30) | |
41 | #define LCCR3_PDFOR_1 (1 << 30) | |
42 | #define LCCR3_PDFOR_2 (2 << 30) | |
43 | #define LCCR3_PDFOR_3 (3 << 30) | |
44 | ||
45 | #define LCCR4_PAL_FOR_0 (0 << 15) | |
46 | #define LCCR4_PAL_FOR_1 (1 << 15) | |
47 | #define LCCR4_PAL_FOR_2 (2 << 15) | |
a0427509 | 48 | #define LCCR4_PAL_FOR_3 (3 << 15) |
ce4fb7b8 | 49 | #define LCCR4_PAL_FOR_MASK (3 << 15) |
50 | ||
51 | #define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ | |
ce4fb7b8 | 52 | #define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */ |
198fc108 EM |
53 | #define FDADR2 (0x220) /* DMA Channel 2 Frame Descriptor Address Register */ |
54 | #define FDADR3 (0x230) /* DMA Channel 3 Frame Descriptor Address Register */ | |
55 | #define FDADR4 (0x240) /* DMA Channel 4 Frame Descriptor Address Register */ | |
56 | #define FDADR5 (0x250) /* DMA Channel 5 Frame Descriptor Address Register */ | |
3c42a449 | 57 | #define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */ |
ce4fb7b8 | 58 | |
59 | #define LCCR0_ENB (1 << 0) /* LCD Controller enable */ | |
60 | #define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ | |
61 | #define LCCR0_Color (LCCR0_CMS*0) /* Color display */ | |
62 | #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ | |
63 | #define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display Select */ | |
64 | #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ | |
65 | #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ | |
66 | ||
67 | #define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ | |
68 | #define LCCR0_SFM (1 << 4) /* Start of frame mask */ | |
69 | #define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ | |
70 | #define LCCR0_EFM (1 << 6) /* End of Frame mask */ | |
71 | #define LCCR0_PAS (1 << 7) /* Passive/Active display Select */ | |
72 | #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ | |
73 | #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ | |
74 | #define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome) */ | |
75 | #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */ | |
76 | #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */ | |
77 | #define LCCR0_DIS (1 << 10) /* LCD Disable */ | |
78 | #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ | |
79 | #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ | |
80 | #define LCCR0_PDD_S 12 | |
3692fd0a | 81 | #define LCCR0_BM (1 << 20) /* Branch mask */ |
ce4fb7b8 | 82 | #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ |
83 | #define LCCR0_LCDT (1 << 22) /* LCD panel type */ | |
84 | #define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ | |
85 | #define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */ | |
86 | #define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */ | |
87 | #define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */ | |
88 | ||
89 | #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ | |
90 | #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) | |
91 | ||
92 | #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ | |
93 | #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW)) | |
94 | ||
95 | #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */ | |
96 | #define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW)) | |
97 | ||
98 | #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ | |
99 | #define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW)) | |
100 | ||
101 | #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ | |
102 | #define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP)) | |
103 | ||
104 | #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */ | |
105 | #define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW)) | |
106 | ||
107 | #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ | |
108 | #define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW)) | |
109 | ||
110 | #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ | |
111 | #define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW)) | |
112 | ||
113 | #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ | |
114 | #define LCCR3_API_S 16 | |
115 | #define LCCR3_VSP (1 << 20) /* vertical sync polarity */ | |
116 | #define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ | |
117 | #define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */ | |
118 | #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ | |
119 | #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ | |
120 | ||
121 | #define LCCR3_OEP (1 << 23) /* Output Enable Polarity */ | |
122 | #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ | |
123 | #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ | |
124 | ||
125 | #define LCCR3_DPC (1 << 27) /* double pixel clock mode */ | |
126 | #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ | |
127 | #define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD))) | |
128 | ||
ce4fb7b8 | 129 | #define LCCR3_ACB Fld (8, 8) /* AC Bias */ |
130 | #define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB))) | |
131 | ||
132 | #define LCCR3_HorSnchH (LCCR3_HSP*0) /* HSP Active High */ | |
133 | #define LCCR3_HorSnchL (LCCR3_HSP*1) /* HSP Active Low */ | |
134 | ||
135 | #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* VSP Active High */ | |
136 | #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* VSP Active Low */ | |
137 | ||
3c42a449 EM |
138 | #define LCCR5_IUM(x) (1 << ((x) + 23)) /* input underrun mask */ |
139 | #define LCCR5_BSM(x) (1 << ((x) + 15)) /* branch mask */ | |
140 | #define LCCR5_EOFM(x) (1 << ((x) + 7)) /* end of frame mask */ | |
141 | #define LCCR5_SOFM(x) (1 << ((x) + 0)) /* start of frame mask */ | |
142 | ||
ce4fb7b8 | 143 | #define LCSR_LDD (1 << 0) /* LCD Disable Done */ |
144 | #define LCSR_SOF (1 << 1) /* Start of frame */ | |
145 | #define LCSR_BER (1 << 2) /* Bus error */ | |
146 | #define LCSR_ABC (1 << 3) /* AC Bias count */ | |
147 | #define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ | |
148 | #define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ | |
149 | #define LCSR_OU (1 << 6) /* output FIFO underrun */ | |
150 | #define LCSR_QD (1 << 7) /* quick disable */ | |
151 | #define LCSR_EOF (1 << 8) /* end of frame */ | |
152 | #define LCSR_BS (1 << 9) /* branch status */ | |
153 | #define LCSR_SINT (1 << 10) /* subsequent interrupt */ | |
3c42a449 EM |
154 | #define LCSR_RD_ST (1 << 11) /* read status */ |
155 | #define LCSR_CMD_INT (1 << 12) /* command interrupt */ | |
ce4fb7b8 | 156 | |
198fc108 EM |
157 | #define LCSR1_IU(x) (1 << ((x) + 23)) /* Input FIFO underrun */ |
158 | #define LCSR1_BS(x) (1 << ((x) + 15)) /* Branch Status */ | |
159 | #define LCSR1_EOF(x) (1 << ((x) + 7)) /* End of Frame Status */ | |
160 | #define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */ | |
161 | ||
ce4fb7b8 | 162 | #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ |
163 | ||
198fc108 EM |
164 | /* overlay control registers */ |
165 | #define OVLxC1_PPL(x) ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */ | |
166 | #define OVLxC1_LPO(x) ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */ | |
167 | #define OVLxC1_BPP(x) (((x) & 0xf) << 20) /* Bits Per Pixel */ | |
168 | #define OVLxC1_OEN (1 << 31) /* Enable bit for Overlay */ | |
169 | #define OVLxC2_XPOS(x) (((x) & 0x3ff) << 0) /* Horizontal Position */ | |
170 | #define OVLxC2_YPOS(x) (((x) & 0x3ff) << 10) /* Vertical Position */ | |
171 | #define OVL2C2_PFOR(x) (((x) & 0x7) << 20) /* Pixel Format */ | |
172 | ||
3c42a449 EM |
173 | /* smartpanel related */ |
174 | #define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */ | |
175 | #define PRSR_A0 (1 << 8) /* Read Data Source */ | |
176 | #define PRSR_ST_OK (1 << 9) /* Status OK */ | |
177 | #define PRSR_CON_NT (1 << 10) /* Continue to Next Command */ | |
178 | ||
179 | #define SMART_CMD_A0 (0x1 << 8) | |
180 | #define SMART_CMD_READ_STATUS_REG (0x0 << 9) | |
181 | #define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0) | |
182 | #define SMART_CMD_WRITE_COMMAND (0x1 << 9) | |
183 | #define SMART_CMD_WRITE_DATA ((0x1 << 9) | SMART_CMD_A0) | |
184 | #define SMART_CMD_WRITE_FRAME ((0x2 << 9) | SMART_CMD_A0) | |
185 | #define SMART_CMD_WAIT_FOR_VSYNC (0x3 << 9) | |
186 | #define SMART_CMD_NOOP (0x4 << 9) | |
187 | #define SMART_CMD_INTERRUPT (0x5 << 9) | |
188 | ||
189 | #define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff)) | |
190 | #define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff)) | |
69bdea70 EM |
191 | |
192 | /* SMART_DELAY() is introduced for software controlled delay primitive which | |
193 | * can be inserted between command sequences, unused command 0x6 is used here | |
194 | * and delay ranges from 0ms ~ 255ms | |
195 | */ | |
196 | #define SMART_CMD_DELAY (0x6 << 9) | |
197 | #define SMART_DELAY(ms) (SMART_CMD_DELAY | ((ms) & 0xff)) | |
ce4fb7b8 | 198 | #endif /* __ASM_ARCH_REGS_LCD_H */ |