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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/irq.c | |
3 | * | |
e3630db1 | 4 | * Generic PXA IRQ handling |
1da177e4 LT |
5 | * |
6 | * Author: Nicolas Pitre | |
7 | * Created: Jun 15, 2001 | |
8 | * Copyright: MontaVista Software Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/interrupt.h> | |
c0165504 | 18 | #include <linux/sysdev.h> |
1da177e4 | 19 | |
a09e64fb | 20 | #include <mach/hardware.h> |
1da177e4 LT |
21 | #include <asm/irq.h> |
22 | #include <asm/mach/irq.h> | |
a09e64fb | 23 | #include <mach/pxa-regs.h> |
a58fbcd8 | 24 | #include <mach/gpio.h> |
1da177e4 LT |
25 | |
26 | #include "generic.h" | |
27 | ||
f6fb7af4 | 28 | #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) |
29 | #define _ICMR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR)) | |
30 | #define _ICLR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR)) | |
1da177e4 LT |
31 | |
32 | /* | |
33 | * This is for peripheral IRQs internal to the PXA chip. | |
34 | */ | |
35 | ||
f6fb7af4 | 36 | static int pxa_internal_irq_nr; |
37 | ||
38 | static void pxa_mask_irq(unsigned int irq) | |
1da177e4 | 39 | { |
f6fb7af4 | 40 | _ICMR(irq) &= ~(1 << IRQ_BIT(irq)); |
1da177e4 LT |
41 | } |
42 | ||
f6fb7af4 | 43 | static void pxa_unmask_irq(unsigned int irq) |
1da177e4 | 44 | { |
f6fb7af4 | 45 | _ICMR(irq) |= 1 << IRQ_BIT(irq); |
1da177e4 LT |
46 | } |
47 | ||
f6fb7af4 | 48 | static struct irq_chip pxa_internal_irq_chip = { |
38c677cb | 49 | .name = "SC", |
f6fb7af4 | 50 | .ack = pxa_mask_irq, |
51 | .mask = pxa_mask_irq, | |
52 | .unmask = pxa_unmask_irq, | |
1da177e4 LT |
53 | }; |
54 | ||
a58fbcd8 EM |
55 | /* |
56 | * GPIO IRQs for GPIO 0 and 1 | |
57 | */ | |
58 | static int pxa_set_low_gpio_type(unsigned int irq, unsigned int type) | |
59 | { | |
60 | int gpio = irq - IRQ_GPIO0; | |
61 | ||
62 | if (__gpio_is_occupied(gpio)) { | |
63 | pr_err("%s failed: GPIO is configured\n", __func__); | |
64 | return -EINVAL; | |
65 | } | |
66 | ||
67 | if (type & IRQ_TYPE_EDGE_RISING) | |
68 | GRER0 |= GPIO_bit(gpio); | |
69 | else | |
70 | GRER0 &= ~GPIO_bit(gpio); | |
71 | ||
72 | if (type & IRQ_TYPE_EDGE_FALLING) | |
73 | GFER0 |= GPIO_bit(gpio); | |
74 | else | |
75 | GFER0 &= ~GPIO_bit(gpio); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
80 | static void pxa_ack_low_gpio(unsigned int irq) | |
81 | { | |
82 | GEDR0 = (1 << (irq - IRQ_GPIO0)); | |
83 | } | |
84 | ||
85 | static void pxa_mask_low_gpio(unsigned int irq) | |
86 | { | |
87 | ICMR &= ~(1 << (irq - PXA_IRQ(0))); | |
88 | } | |
89 | ||
90 | static void pxa_unmask_low_gpio(unsigned int irq) | |
91 | { | |
92 | ICMR |= 1 << (irq - PXA_IRQ(0)); | |
93 | } | |
94 | ||
95 | static struct irq_chip pxa_low_gpio_chip = { | |
96 | .name = "GPIO-l", | |
97 | .ack = pxa_ack_low_gpio, | |
98 | .mask = pxa_mask_low_gpio, | |
99 | .unmask = pxa_unmask_low_gpio, | |
100 | .set_type = pxa_set_low_gpio_type, | |
101 | }; | |
102 | ||
103 | static void __init pxa_init_low_gpio_irq(set_wake_t fn) | |
104 | { | |
105 | int irq; | |
106 | ||
107 | /* clear edge detection on GPIO 0 and 1 */ | |
108 | GFER0 &= ~0x3; | |
109 | GRER0 &= ~0x3; | |
110 | GEDR0 = 0x3; | |
111 | ||
112 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | |
113 | set_irq_chip(irq, &pxa_low_gpio_chip); | |
114 | set_irq_handler(irq, handle_edge_irq); | |
115 | set_irq_flags(irq, IRQF_VALID); | |
116 | } | |
117 | ||
118 | pxa_low_gpio_chip.set_wake = fn; | |
119 | } | |
120 | ||
b9e25ace | 121 | void __init pxa_init_irq(int irq_nr, set_wake_t fn) |
53665a50 EM |
122 | { |
123 | int irq; | |
124 | ||
f6fb7af4 | 125 | pxa_internal_irq_nr = irq_nr; |
53665a50 | 126 | |
57a7a62e | 127 | for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) { |
f6fb7af4 | 128 | _ICMR(irq) = 0; /* disable all IRQs */ |
129 | _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */ | |
130 | } | |
53665a50 EM |
131 | |
132 | /* only unmasked interrupts kick us out of idle */ | |
133 | ICCR = 1; | |
134 | ||
f6fb7af4 | 135 | for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) { |
136 | set_irq_chip(irq, &pxa_internal_irq_chip); | |
c08b7b3e EM |
137 | set_irq_handler(irq, handle_level_irq); |
138 | set_irq_flags(irq, IRQF_VALID); | |
139 | } | |
1da177e4 | 140 | |
b9e25ace | 141 | pxa_internal_irq_chip.set_wake = fn; |
a58fbcd8 | 142 | pxa_init_low_gpio_irq(fn); |
c95530c7 | 143 | } |
c0165504 | 144 | |
145 | #ifdef CONFIG_PM | |
146 | static unsigned long saved_icmr[2]; | |
147 | ||
148 | static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) | |
149 | { | |
f6fb7af4 | 150 | int i, irq = PXA_IRQ(0); |
151 | ||
152 | for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) { | |
153 | saved_icmr[i] = _ICMR(irq); | |
154 | _ICMR(irq) = 0; | |
c0165504 | 155 | } |
156 | ||
157 | return 0; | |
158 | } | |
159 | ||
160 | static int pxa_irq_resume(struct sys_device *dev) | |
161 | { | |
f6fb7af4 | 162 | int i, irq = PXA_IRQ(0); |
163 | ||
164 | for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) { | |
165 | _ICMR(irq) = saved_icmr[i]; | |
166 | _ICLR(irq) = 0; | |
c0165504 | 167 | } |
168 | ||
f6fb7af4 | 169 | ICCR = 1; |
c0165504 | 170 | return 0; |
171 | } | |
172 | #else | |
173 | #define pxa_irq_suspend NULL | |
174 | #define pxa_irq_resume NULL | |
175 | #endif | |
176 | ||
177 | struct sysdev_class pxa_irq_sysclass = { | |
178 | .name = "irq", | |
179 | .suspend = pxa_irq_suspend, | |
180 | .resume = pxa_irq_resume, | |
181 | }; | |
182 | ||
183 | static int __init pxa_irq_init(void) | |
184 | { | |
185 | return sysdev_class_register(&pxa_irq_sysclass); | |
186 | } | |
187 | ||
188 | core_initcall(pxa_irq_init); |