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e9937d4b LB |
1 | /* |
2 | * linux/arch/arm/mach-pxa/lpd270.c | |
3 | * | |
4 | * Support for the LogicPD PXA270 Card Engine. | |
5 | * Derived from the mainstone code, which carries these notices: | |
6 | * | |
7 | * Author: Nicolas Pitre | |
8 | * Created: Nov 05, 2002 | |
9 | * Copyright: MontaVista Software Inc. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/platform_device.h> | |
2eaa03b5 | 18 | #include <linux/syscore_ops.h> |
e9937d4b LB |
19 | #include <linux/interrupt.h> |
20 | #include <linux/sched.h> | |
21 | #include <linux/bitops.h> | |
22 | #include <linux/fb.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mtd/partitions.h> | |
4a730719 | 26 | #include <linux/pwm_backlight.h> |
e9937d4b LB |
27 | |
28 | #include <asm/types.h> | |
29 | #include <asm/setup.h> | |
30 | #include <asm/memory.h> | |
31 | #include <asm/mach-types.h> | |
a09e64fb | 32 | #include <mach/hardware.h> |
e9937d4b LB |
33 | #include <asm/irq.h> |
34 | #include <asm/sizes.h> | |
35 | ||
36 | #include <asm/mach/arch.h> | |
37 | #include <asm/mach/map.h> | |
38 | #include <asm/mach/irq.h> | |
39 | #include <asm/mach/flash.h> | |
40 | ||
51c62982 | 41 | #include <mach/pxa27x.h> |
da065a0b | 42 | #include <mach/gpio.h> |
a09e64fb RK |
43 | #include <mach/lpd270.h> |
44 | #include <mach/audio.h> | |
45 | #include <mach/pxafb.h> | |
46 | #include <mach/mmc.h> | |
47 | #include <mach/irda.h> | |
48 | #include <mach/ohci.h> | |
ad68bb9f | 49 | #include <mach/smemc.h> |
e9937d4b LB |
50 | |
51 | #include "generic.h" | |
46c41e62 | 52 | #include "devices.h" |
e9937d4b | 53 | |
fd90ff20 EM |
54 | static unsigned long lpd270_pin_config[] __initdata = { |
55 | /* Chip Selects */ | |
56 | GPIO15_nCS_1, /* Mainboard Flash */ | |
57 | GPIO78_nCS_2, /* CPLD + Ethernet */ | |
58 | ||
59 | /* LCD - 16bpp Active TFT */ | |
60 | GPIO58_LCD_LDD_0, | |
61 | GPIO59_LCD_LDD_1, | |
62 | GPIO60_LCD_LDD_2, | |
63 | GPIO61_LCD_LDD_3, | |
64 | GPIO62_LCD_LDD_4, | |
65 | GPIO63_LCD_LDD_5, | |
66 | GPIO64_LCD_LDD_6, | |
67 | GPIO65_LCD_LDD_7, | |
68 | GPIO66_LCD_LDD_8, | |
69 | GPIO67_LCD_LDD_9, | |
70 | GPIO68_LCD_LDD_10, | |
71 | GPIO69_LCD_LDD_11, | |
72 | GPIO70_LCD_LDD_12, | |
73 | GPIO71_LCD_LDD_13, | |
74 | GPIO72_LCD_LDD_14, | |
75 | GPIO73_LCD_LDD_15, | |
76 | GPIO74_LCD_FCLK, | |
77 | GPIO75_LCD_LCLK, | |
78 | GPIO76_LCD_PCLK, | |
79 | GPIO77_LCD_BIAS, | |
80 | GPIO16_PWM0_OUT, /* Backlight */ | |
81 | ||
82 | /* USB Host */ | |
83 | GPIO88_USBH1_PWR, | |
84 | GPIO89_USBH1_PEN, | |
85 | ||
86 | /* AC97 */ | |
c11b6a42 EM |
87 | GPIO28_AC97_BITCLK, |
88 | GPIO29_AC97_SDATA_IN_0, | |
89 | GPIO30_AC97_SDATA_OUT, | |
90 | GPIO31_AC97_SYNC, | |
fd90ff20 EM |
91 | GPIO45_AC97_SYSCLK, |
92 | ||
93 | GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, | |
94 | }; | |
e9937d4b LB |
95 | |
96 | static unsigned int lpd270_irq_enabled; | |
97 | ||
a3f4c927 | 98 | static void lpd270_mask_irq(struct irq_data *d) |
e9937d4b | 99 | { |
a3f4c927 | 100 | int lpd270_irq = d->irq - LPD270_IRQ(0); |
e9937d4b LB |
101 | |
102 | __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS); | |
103 | ||
104 | lpd270_irq_enabled &= ~(1 << lpd270_irq); | |
105 | __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK); | |
106 | } | |
107 | ||
a3f4c927 | 108 | static void lpd270_unmask_irq(struct irq_data *d) |
e9937d4b | 109 | { |
a3f4c927 | 110 | int lpd270_irq = d->irq - LPD270_IRQ(0); |
e9937d4b LB |
111 | |
112 | lpd270_irq_enabled |= 1 << lpd270_irq; | |
113 | __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK); | |
114 | } | |
115 | ||
38c677cb DB |
116 | static struct irq_chip lpd270_irq_chip = { |
117 | .name = "CPLD", | |
a3f4c927 LB |
118 | .irq_ack = lpd270_mask_irq, |
119 | .irq_mask = lpd270_mask_irq, | |
120 | .irq_unmask = lpd270_unmask_irq, | |
e9937d4b LB |
121 | }; |
122 | ||
10dd5ce2 | 123 | static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc) |
e9937d4b LB |
124 | { |
125 | unsigned long pending; | |
126 | ||
127 | pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled; | |
128 | do { | |
a3f4c927 LB |
129 | /* clear useless edge notification */ |
130 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
e9937d4b LB |
131 | if (likely(pending)) { |
132 | irq = LPD270_IRQ(0) + __ffs(pending); | |
d8aa0251 | 133 | generic_handle_irq(irq); |
e9937d4b LB |
134 | |
135 | pending = __raw_readw(LPD270_INT_STATUS) & | |
136 | lpd270_irq_enabled; | |
137 | } | |
138 | } while (pending); | |
139 | } | |
140 | ||
141 | static void __init lpd270_init_irq(void) | |
142 | { | |
143 | int irq; | |
144 | ||
cd49104d | 145 | pxa27x_init_irq(); |
e9937d4b LB |
146 | |
147 | __raw_writew(0, LPD270_INT_MASK); | |
148 | __raw_writew(0, LPD270_INT_STATUS); | |
149 | ||
150 | /* setup extra LogicPD PXA270 irqs */ | |
151 | for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { | |
f38c02f3 TG |
152 | irq_set_chip_and_handler(irq, &lpd270_irq_chip, |
153 | handle_level_irq); | |
e9937d4b LB |
154 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
155 | } | |
6845664a TG |
156 | irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); |
157 | irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); | |
e9937d4b LB |
158 | } |
159 | ||
160 | ||
161 | #ifdef CONFIG_PM | |
2eaa03b5 | 162 | static void lpd270_irq_resume(void) |
e9937d4b LB |
163 | { |
164 | __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK); | |
e9937d4b LB |
165 | } |
166 | ||
2eaa03b5 | 167 | static struct syscore_ops lpd270_irq_syscore_ops = { |
e9937d4b LB |
168 | .resume = lpd270_irq_resume, |
169 | }; | |
170 | ||
e9937d4b LB |
171 | static int __init lpd270_irq_device_init(void) |
172 | { | |
720046de | 173 | if (machine_is_logicpd_pxa270()) { |
2eaa03b5 RW |
174 | register_syscore_ops(&lpd270_irq_syscore_ops); |
175 | return 0; | |
720046de | 176 | } |
2eaa03b5 | 177 | return -ENODEV; |
e9937d4b LB |
178 | } |
179 | ||
180 | device_initcall(lpd270_irq_device_init); | |
181 | #endif | |
182 | ||
183 | ||
184 | static struct resource smc91x_resources[] = { | |
185 | [0] = { | |
186 | .start = LPD270_ETH_PHYS, | |
187 | .end = (LPD270_ETH_PHYS + 0xfffff), | |
188 | .flags = IORESOURCE_MEM, | |
189 | }, | |
190 | [1] = { | |
191 | .start = LPD270_ETHERNET_IRQ, | |
192 | .end = LPD270_ETHERNET_IRQ, | |
193 | .flags = IORESOURCE_IRQ, | |
194 | }, | |
195 | }; | |
196 | ||
197 | static struct platform_device smc91x_device = { | |
198 | .name = "smc91x", | |
199 | .id = 0, | |
200 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
201 | .resource = smc91x_resources, | |
202 | }; | |
203 | ||
e9937d4b LB |
204 | static struct resource lpd270_flash_resources[] = { |
205 | [0] = { | |
206 | .start = PXA_CS0_PHYS, | |
207 | .end = PXA_CS0_PHYS + SZ_64M - 1, | |
208 | .flags = IORESOURCE_MEM, | |
209 | }, | |
210 | [1] = { | |
211 | .start = PXA_CS1_PHYS, | |
212 | .end = PXA_CS1_PHYS + SZ_64M - 1, | |
213 | .flags = IORESOURCE_MEM, | |
214 | }, | |
215 | }; | |
216 | ||
217 | static struct mtd_partition lpd270_flash0_partitions[] = { | |
218 | { | |
219 | .name = "Bootloader", | |
220 | .size = 0x00040000, | |
221 | .offset = 0, | |
222 | .mask_flags = MTD_WRITEABLE /* force read-only */ | |
223 | }, { | |
224 | .name = "Kernel", | |
225 | .size = 0x00400000, | |
226 | .offset = 0x00040000, | |
227 | }, { | |
228 | .name = "Filesystem", | |
229 | .size = MTDPART_SIZ_FULL, | |
230 | .offset = 0x00440000 | |
231 | }, | |
232 | }; | |
233 | ||
234 | static struct flash_platform_data lpd270_flash_data[2] = { | |
235 | { | |
236 | .name = "processor-flash", | |
237 | .map_name = "cfi_probe", | |
238 | .parts = lpd270_flash0_partitions, | |
239 | .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions), | |
240 | }, { | |
241 | .name = "mainboard-flash", | |
242 | .map_name = "cfi_probe", | |
243 | .parts = NULL, | |
244 | .nr_parts = 0, | |
245 | } | |
246 | }; | |
247 | ||
248 | static struct platform_device lpd270_flash_device[2] = { | |
249 | { | |
250 | .name = "pxa2xx-flash", | |
251 | .id = 0, | |
252 | .dev = { | |
253 | .platform_data = &lpd270_flash_data[0], | |
254 | }, | |
255 | .resource = &lpd270_flash_resources[0], | |
256 | .num_resources = 1, | |
257 | }, { | |
258 | .name = "pxa2xx-flash", | |
259 | .id = 1, | |
260 | .dev = { | |
261 | .platform_data = &lpd270_flash_data[1], | |
262 | }, | |
263 | .resource = &lpd270_flash_resources[1], | |
264 | .num_resources = 1, | |
265 | }, | |
266 | }; | |
267 | ||
4a730719 RK |
268 | static struct platform_pwm_backlight_data lpd270_backlight_data = { |
269 | .pwm_id = 0, | |
270 | .max_brightness = 1, | |
271 | .dft_brightness = 1, | |
272 | .pwm_period_ns = 78770, | |
273 | }; | |
274 | ||
275 | static struct platform_device lpd270_backlight_device = { | |
276 | .name = "pwm-backlight", | |
277 | .dev = { | |
278 | .parent = &pxa27x_device_pwm0.dev, | |
279 | .platform_data = &lpd270_backlight_data, | |
280 | }, | |
281 | }; | |
e9937d4b LB |
282 | |
283 | /* 5.7" TFT QVGA (LoLo display number 1) */ | |
d14b272b | 284 | static struct pxafb_mode_info sharp_lq057q3dc02_mode = { |
65660297 LB |
285 | .pixclock = 150000, |
286 | .xres = 320, | |
287 | .yres = 240, | |
e9937d4b | 288 | .bpp = 16, |
65660297 LB |
289 | .hsync_len = 0x14, |
290 | .left_margin = 0x28, | |
291 | .right_margin = 0x0a, | |
292 | .vsync_len = 0x02, | |
e9937d4b LB |
293 | .upper_margin = 0x08, |
294 | .lower_margin = 0x14, | |
65660297 | 295 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
d14b272b RP |
296 | }; |
297 | ||
298 | static struct pxafb_mach_info sharp_lq057q3dc02 = { | |
299 | .modes = &sharp_lq057q3dc02_mode, | |
300 | .num_modes = 1, | |
0219e835 EM |
301 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL | |
302 | LCD_ALTERNATE_MAPPING, | |
65660297 LB |
303 | }; |
304 | ||
305 | /* 12.1" TFT SVGA (LoLo display number 2) */ | |
d14b272b | 306 | static struct pxafb_mode_info sharp_lq121s1dg31_mode = { |
65660297 LB |
307 | .pixclock = 50000, |
308 | .xres = 800, | |
309 | .yres = 600, | |
310 | .bpp = 16, | |
311 | .hsync_len = 0x05, | |
312 | .left_margin = 0x52, | |
313 | .right_margin = 0x05, | |
314 | .vsync_len = 0x04, | |
315 | .upper_margin = 0x14, | |
316 | .lower_margin = 0x0a, | |
317 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
d14b272b RP |
318 | }; |
319 | ||
320 | static struct pxafb_mach_info sharp_lq121s1dg31 = { | |
321 | .modes = &sharp_lq121s1dg31_mode, | |
322 | .num_modes = 1, | |
0219e835 EM |
323 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL | |
324 | LCD_ALTERNATE_MAPPING, | |
65660297 LB |
325 | }; |
326 | ||
327 | /* 3.6" TFT QVGA (LoLo display number 3) */ | |
d14b272b | 328 | static struct pxafb_mode_info sharp_lq036q1da01_mode = { |
65660297 LB |
329 | .pixclock = 150000, |
330 | .xres = 320, | |
331 | .yres = 240, | |
332 | .bpp = 16, | |
333 | .hsync_len = 0x0e, | |
334 | .left_margin = 0x04, | |
335 | .right_margin = 0x0a, | |
336 | .vsync_len = 0x03, | |
337 | .upper_margin = 0x03, | |
338 | .lower_margin = 0x03, | |
339 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
d14b272b RP |
340 | }; |
341 | ||
342 | static struct pxafb_mach_info sharp_lq036q1da01 = { | |
343 | .modes = &sharp_lq036q1da01_mode, | |
344 | .num_modes = 1, | |
0219e835 EM |
345 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL | |
346 | LCD_ALTERNATE_MAPPING, | |
e9937d4b LB |
347 | }; |
348 | ||
349 | /* 6.4" TFT VGA (LoLo display number 5) */ | |
d14b272b | 350 | static struct pxafb_mode_info sharp_lq64d343_mode = { |
65660297 | 351 | .pixclock = 25000, |
e9937d4b LB |
352 | .xres = 640, |
353 | .yres = 480, | |
354 | .bpp = 16, | |
65660297 | 355 | .hsync_len = 0x31, |
e9937d4b LB |
356 | .left_margin = 0x89, |
357 | .right_margin = 0x19, | |
65660297 | 358 | .vsync_len = 0x12, |
e9937d4b | 359 | .upper_margin = 0x22, |
65660297 | 360 | .lower_margin = 0x00, |
e9937d4b | 361 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
d14b272b RP |
362 | }; |
363 | ||
364 | static struct pxafb_mach_info sharp_lq64d343 = { | |
365 | .modes = &sharp_lq64d343_mode, | |
366 | .num_modes = 1, | |
0219e835 EM |
367 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL | |
368 | LCD_ALTERNATE_MAPPING, | |
65660297 LB |
369 | }; |
370 | ||
371 | /* 10.4" TFT VGA (LoLo display number 7) */ | |
d14b272b | 372 | static struct pxafb_mode_info sharp_lq10d368_mode = { |
65660297 LB |
373 | .pixclock = 25000, |
374 | .xres = 640, | |
375 | .yres = 480, | |
376 | .bpp = 16, | |
377 | .hsync_len = 0x31, | |
378 | .left_margin = 0x89, | |
379 | .right_margin = 0x19, | |
380 | .vsync_len = 0x12, | |
381 | .upper_margin = 0x22, | |
382 | .lower_margin = 0x00, | |
383 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
d14b272b RP |
384 | }; |
385 | ||
386 | static struct pxafb_mach_info sharp_lq10d368 = { | |
387 | .modes = &sharp_lq10d368_mode, | |
388 | .num_modes = 1, | |
0219e835 EM |
389 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL | |
390 | LCD_ALTERNATE_MAPPING, | |
e9937d4b LB |
391 | }; |
392 | ||
393 | /* 3.5" TFT QVGA (LoLo display number 8) */ | |
d14b272b | 394 | static struct pxafb_mode_info sharp_lq035q7db02_20_mode = { |
65660297 | 395 | .pixclock = 150000, |
e9937d4b LB |
396 | .xres = 240, |
397 | .yres = 320, | |
398 | .bpp = 16, | |
65660297 LB |
399 | .hsync_len = 0x0e, |
400 | .left_margin = 0x0a, | |
401 | .right_margin = 0x0a, | |
402 | .vsync_len = 0x03, | |
e9937d4b LB |
403 | .upper_margin = 0x05, |
404 | .lower_margin = 0x14, | |
65660297 | 405 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
d14b272b RP |
406 | }; |
407 | ||
408 | static struct pxafb_mach_info sharp_lq035q7db02_20 = { | |
409 | .modes = &sharp_lq035q7db02_20_mode, | |
410 | .num_modes = 1, | |
0219e835 EM |
411 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL | |
412 | LCD_ALTERNATE_MAPPING, | |
e9937d4b LB |
413 | }; |
414 | ||
65660297 LB |
415 | static struct pxafb_mach_info *lpd270_lcd_to_use; |
416 | ||
417 | static int __init lpd270_set_lcd(char *str) | |
418 | { | |
419 | if (!strnicmp(str, "lq057q3dc02", 11)) { | |
420 | lpd270_lcd_to_use = &sharp_lq057q3dc02; | |
421 | } else if (!strnicmp(str, "lq121s1dg31", 11)) { | |
422 | lpd270_lcd_to_use = &sharp_lq121s1dg31; | |
423 | } else if (!strnicmp(str, "lq036q1da01", 11)) { | |
424 | lpd270_lcd_to_use = &sharp_lq036q1da01; | |
425 | } else if (!strnicmp(str, "lq64d343", 8)) { | |
426 | lpd270_lcd_to_use = &sharp_lq64d343; | |
427 | } else if (!strnicmp(str, "lq10d368", 8)) { | |
428 | lpd270_lcd_to_use = &sharp_lq10d368; | |
429 | } else if (!strnicmp(str, "lq035q7db02-20", 14)) { | |
430 | lpd270_lcd_to_use = &sharp_lq035q7db02_20; | |
431 | } else { | |
432 | printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str); | |
433 | } | |
434 | ||
435 | return 1; | |
436 | } | |
437 | ||
438 | __setup("lcd=", lpd270_set_lcd); | |
439 | ||
e9937d4b LB |
440 | static struct platform_device *platform_devices[] __initdata = { |
441 | &smc91x_device, | |
4a730719 | 442 | &lpd270_backlight_device, |
e9937d4b LB |
443 | &lpd270_flash_device[0], |
444 | &lpd270_flash_device[1], | |
445 | }; | |
446 | ||
e9937d4b LB |
447 | static struct pxaohci_platform_data lpd270_ohci_platform_data = { |
448 | .port_mode = PMM_PERPORT_MODE, | |
097b5334 | 449 | .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW, |
e9937d4b LB |
450 | }; |
451 | ||
452 | static void __init lpd270_init(void) | |
453 | { | |
fd90ff20 EM |
454 | pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config)); |
455 | ||
cc155c6f RK |
456 | pxa_set_ffuart_info(NULL); |
457 | pxa_set_btuart_info(NULL); | |
458 | pxa_set_stuart_info(NULL); | |
459 | ||
ad68bb9f | 460 | lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4; |
e9937d4b LB |
461 | lpd270_flash_data[1].width = 4; |
462 | ||
463 | /* | |
464 | * System bus arbiter setting: | |
465 | * - Core_Park | |
466 | * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4 | |
467 | */ | |
468 | ARB_CNTRL = ARB_CORE_PARK | 0x234; | |
469 | ||
e9937d4b LB |
470 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
471 | ||
9f19d638 MB |
472 | pxa_set_ac97_info(NULL); |
473 | ||
65660297 | 474 | if (lpd270_lcd_to_use != NULL) |
4321e1a1 | 475 | pxa_set_fb_info(NULL, lpd270_lcd_to_use); |
e9937d4b LB |
476 | |
477 | pxa_set_ohci_info(&lpd270_ohci_platform_data); | |
478 | } | |
479 | ||
480 | ||
481 | static struct map_desc lpd270_io_desc[] __initdata = { | |
482 | { | |
483 | .virtual = LPD270_CPLD_VIRT, | |
484 | .pfn = __phys_to_pfn(LPD270_CPLD_PHYS), | |
485 | .length = LPD270_CPLD_SIZE, | |
486 | .type = MT_DEVICE, | |
487 | }, | |
488 | }; | |
489 | ||
490 | static void __init lpd270_map_io(void) | |
491 | { | |
851982c1 | 492 | pxa27x_map_io(); |
e9937d4b LB |
493 | iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc)); |
494 | ||
e9937d4b LB |
495 | /* for use I SRAM as framebuffer. */ |
496 | PSLR |= 0x00000F04; | |
497 | PCFR = 0x00000066; | |
498 | } | |
499 | ||
500 | MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine") | |
501 | /* Maintainer: Peter Barada */ | |
e9937d4b LB |
502 | .boot_params = 0xa0000100, |
503 | .map_io = lpd270_map_io, | |
6ac6b817 | 504 | .nr_irqs = LPD270_NR_IRQS, |
e9937d4b | 505 | .init_irq = lpd270_init_irq, |
8a97ae2f | 506 | .handle_irq = pxa27x_handle_irq, |
e9937d4b LB |
507 | .timer = &pxa_timer, |
508 | .init_machine = lpd270_init, | |
509 | MACHINE_END |