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e9937d4b LB |
1 | /* |
2 | * linux/arch/arm/mach-pxa/lpd270.c | |
3 | * | |
4 | * Support for the LogicPD PXA270 Card Engine. | |
5 | * Derived from the mainstone code, which carries these notices: | |
6 | * | |
7 | * Author: Nicolas Pitre | |
8 | * Created: Nov 05, 2002 | |
9 | * Copyright: MontaVista Software Inc. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
2f8163ba | 15 | #include <linux/gpio.h> |
e9937d4b LB |
16 | #include <linux/init.h> |
17 | #include <linux/platform_device.h> | |
2eaa03b5 | 18 | #include <linux/syscore_ops.h> |
e9937d4b LB |
19 | #include <linux/interrupt.h> |
20 | #include <linux/sched.h> | |
21 | #include <linux/bitops.h> | |
22 | #include <linux/fb.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mtd/partitions.h> | |
4a730719 | 26 | #include <linux/pwm_backlight.h> |
b70661c7 | 27 | #include <linux/smc91x.h> |
e9937d4b LB |
28 | |
29 | #include <asm/types.h> | |
30 | #include <asm/setup.h> | |
31 | #include <asm/memory.h> | |
32 | #include <asm/mach-types.h> | |
a09e64fb | 33 | #include <mach/hardware.h> |
e9937d4b LB |
34 | #include <asm/irq.h> |
35 | #include <asm/sizes.h> | |
36 | ||
37 | #include <asm/mach/arch.h> | |
38 | #include <asm/mach/map.h> | |
39 | #include <asm/mach/irq.h> | |
40 | #include <asm/mach/flash.h> | |
41 | ||
51c62982 | 42 | #include <mach/pxa27x.h> |
a09e64fb RK |
43 | #include <mach/lpd270.h> |
44 | #include <mach/audio.h> | |
293b2da1 AB |
45 | #include <linux/platform_data/video-pxafb.h> |
46 | #include <linux/platform_data/mmc-pxamci.h> | |
47 | #include <linux/platform_data/irda-pxaficp.h> | |
48 | #include <linux/platform_data/usb-ohci-pxa27x.h> | |
ad68bb9f | 49 | #include <mach/smemc.h> |
e9937d4b LB |
50 | |
51 | #include "generic.h" | |
46c41e62 | 52 | #include "devices.h" |
e9937d4b | 53 | |
fd90ff20 EM |
54 | static unsigned long lpd270_pin_config[] __initdata = { |
55 | /* Chip Selects */ | |
56 | GPIO15_nCS_1, /* Mainboard Flash */ | |
57 | GPIO78_nCS_2, /* CPLD + Ethernet */ | |
58 | ||
59 | /* LCD - 16bpp Active TFT */ | |
60 | GPIO58_LCD_LDD_0, | |
61 | GPIO59_LCD_LDD_1, | |
62 | GPIO60_LCD_LDD_2, | |
63 | GPIO61_LCD_LDD_3, | |
64 | GPIO62_LCD_LDD_4, | |
65 | GPIO63_LCD_LDD_5, | |
66 | GPIO64_LCD_LDD_6, | |
67 | GPIO65_LCD_LDD_7, | |
68 | GPIO66_LCD_LDD_8, | |
69 | GPIO67_LCD_LDD_9, | |
70 | GPIO68_LCD_LDD_10, | |
71 | GPIO69_LCD_LDD_11, | |
72 | GPIO70_LCD_LDD_12, | |
73 | GPIO71_LCD_LDD_13, | |
74 | GPIO72_LCD_LDD_14, | |
75 | GPIO73_LCD_LDD_15, | |
76 | GPIO74_LCD_FCLK, | |
77 | GPIO75_LCD_LCLK, | |
78 | GPIO76_LCD_PCLK, | |
79 | GPIO77_LCD_BIAS, | |
80 | GPIO16_PWM0_OUT, /* Backlight */ | |
81 | ||
82 | /* USB Host */ | |
83 | GPIO88_USBH1_PWR, | |
84 | GPIO89_USBH1_PEN, | |
85 | ||
86 | /* AC97 */ | |
c11b6a42 EM |
87 | GPIO28_AC97_BITCLK, |
88 | GPIO29_AC97_SDATA_IN_0, | |
89 | GPIO30_AC97_SDATA_OUT, | |
90 | GPIO31_AC97_SYNC, | |
fd90ff20 EM |
91 | GPIO45_AC97_SYSCLK, |
92 | ||
93 | GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, | |
94 | }; | |
e9937d4b LB |
95 | |
96 | static unsigned int lpd270_irq_enabled; | |
97 | ||
a3f4c927 | 98 | static void lpd270_mask_irq(struct irq_data *d) |
e9937d4b | 99 | { |
a3f4c927 | 100 | int lpd270_irq = d->irq - LPD270_IRQ(0); |
e9937d4b LB |
101 | |
102 | __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS); | |
103 | ||
104 | lpd270_irq_enabled &= ~(1 << lpd270_irq); | |
105 | __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK); | |
106 | } | |
107 | ||
a3f4c927 | 108 | static void lpd270_unmask_irq(struct irq_data *d) |
e9937d4b | 109 | { |
a3f4c927 | 110 | int lpd270_irq = d->irq - LPD270_IRQ(0); |
e9937d4b LB |
111 | |
112 | lpd270_irq_enabled |= 1 << lpd270_irq; | |
113 | __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK); | |
114 | } | |
115 | ||
38c677cb DB |
116 | static struct irq_chip lpd270_irq_chip = { |
117 | .name = "CPLD", | |
a3f4c927 LB |
118 | .irq_ack = lpd270_mask_irq, |
119 | .irq_mask = lpd270_mask_irq, | |
120 | .irq_unmask = lpd270_unmask_irq, | |
e9937d4b LB |
121 | }; |
122 | ||
bd0b9ac4 | 123 | static void lpd270_irq_handler(struct irq_desc *desc) |
e9937d4b | 124 | { |
6947d04a | 125 | unsigned int irq; |
e9937d4b LB |
126 | unsigned long pending; |
127 | ||
128 | pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled; | |
129 | do { | |
a3f4c927 LB |
130 | /* clear useless edge notification */ |
131 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
e9937d4b LB |
132 | if (likely(pending)) { |
133 | irq = LPD270_IRQ(0) + __ffs(pending); | |
d8aa0251 | 134 | generic_handle_irq(irq); |
e9937d4b LB |
135 | |
136 | pending = __raw_readw(LPD270_INT_STATUS) & | |
137 | lpd270_irq_enabled; | |
138 | } | |
139 | } while (pending); | |
140 | } | |
141 | ||
142 | static void __init lpd270_init_irq(void) | |
143 | { | |
144 | int irq; | |
145 | ||
cd49104d | 146 | pxa27x_init_irq(); |
e9937d4b LB |
147 | |
148 | __raw_writew(0, LPD270_INT_MASK); | |
149 | __raw_writew(0, LPD270_INT_STATUS); | |
150 | ||
151 | /* setup extra LogicPD PXA270 irqs */ | |
152 | for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { | |
f38c02f3 TG |
153 | irq_set_chip_and_handler(irq, &lpd270_irq_chip, |
154 | handle_level_irq); | |
e8d36d5d | 155 | irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); |
e9937d4b | 156 | } |
6384fdad HZ |
157 | irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler); |
158 | irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING); | |
e9937d4b LB |
159 | } |
160 | ||
161 | ||
162 | #ifdef CONFIG_PM | |
2eaa03b5 | 163 | static void lpd270_irq_resume(void) |
e9937d4b LB |
164 | { |
165 | __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK); | |
e9937d4b LB |
166 | } |
167 | ||
2eaa03b5 | 168 | static struct syscore_ops lpd270_irq_syscore_ops = { |
e9937d4b LB |
169 | .resume = lpd270_irq_resume, |
170 | }; | |
171 | ||
e9937d4b LB |
172 | static int __init lpd270_irq_device_init(void) |
173 | { | |
720046de | 174 | if (machine_is_logicpd_pxa270()) { |
2eaa03b5 RW |
175 | register_syscore_ops(&lpd270_irq_syscore_ops); |
176 | return 0; | |
720046de | 177 | } |
2eaa03b5 | 178 | return -ENODEV; |
e9937d4b LB |
179 | } |
180 | ||
181 | device_initcall(lpd270_irq_device_init); | |
182 | #endif | |
183 | ||
184 | ||
185 | static struct resource smc91x_resources[] = { | |
186 | [0] = { | |
187 | .start = LPD270_ETH_PHYS, | |
188 | .end = (LPD270_ETH_PHYS + 0xfffff), | |
189 | .flags = IORESOURCE_MEM, | |
190 | }, | |
191 | [1] = { | |
192 | .start = LPD270_ETHERNET_IRQ, | |
193 | .end = LPD270_ETHERNET_IRQ, | |
b70661c7 | 194 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, |
e9937d4b LB |
195 | }, |
196 | }; | |
197 | ||
b70661c7 | 198 | struct smc91x_platdata smc91x_platdata = { |
04b91701 | 199 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, |
b70661c7 AB |
200 | }; |
201 | ||
e9937d4b LB |
202 | static struct platform_device smc91x_device = { |
203 | .name = "smc91x", | |
204 | .id = 0, | |
205 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
206 | .resource = smc91x_resources, | |
b70661c7 | 207 | .dev.platform_data = &smc91x_platdata, |
e9937d4b LB |
208 | }; |
209 | ||
e9937d4b LB |
210 | static struct resource lpd270_flash_resources[] = { |
211 | [0] = { | |
212 | .start = PXA_CS0_PHYS, | |
213 | .end = PXA_CS0_PHYS + SZ_64M - 1, | |
214 | .flags = IORESOURCE_MEM, | |
215 | }, | |
216 | [1] = { | |
217 | .start = PXA_CS1_PHYS, | |
218 | .end = PXA_CS1_PHYS + SZ_64M - 1, | |
219 | .flags = IORESOURCE_MEM, | |
220 | }, | |
221 | }; | |
222 | ||
223 | static struct mtd_partition lpd270_flash0_partitions[] = { | |
224 | { | |
225 | .name = "Bootloader", | |
226 | .size = 0x00040000, | |
227 | .offset = 0, | |
228 | .mask_flags = MTD_WRITEABLE /* force read-only */ | |
229 | }, { | |
230 | .name = "Kernel", | |
231 | .size = 0x00400000, | |
232 | .offset = 0x00040000, | |
233 | }, { | |
234 | .name = "Filesystem", | |
235 | .size = MTDPART_SIZ_FULL, | |
236 | .offset = 0x00440000 | |
237 | }, | |
238 | }; | |
239 | ||
240 | static struct flash_platform_data lpd270_flash_data[2] = { | |
241 | { | |
242 | .name = "processor-flash", | |
243 | .map_name = "cfi_probe", | |
244 | .parts = lpd270_flash0_partitions, | |
245 | .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions), | |
246 | }, { | |
247 | .name = "mainboard-flash", | |
248 | .map_name = "cfi_probe", | |
249 | .parts = NULL, | |
250 | .nr_parts = 0, | |
251 | } | |
252 | }; | |
253 | ||
254 | static struct platform_device lpd270_flash_device[2] = { | |
255 | { | |
256 | .name = "pxa2xx-flash", | |
257 | .id = 0, | |
258 | .dev = { | |
259 | .platform_data = &lpd270_flash_data[0], | |
260 | }, | |
261 | .resource = &lpd270_flash_resources[0], | |
262 | .num_resources = 1, | |
263 | }, { | |
264 | .name = "pxa2xx-flash", | |
265 | .id = 1, | |
266 | .dev = { | |
267 | .platform_data = &lpd270_flash_data[1], | |
268 | }, | |
269 | .resource = &lpd270_flash_resources[1], | |
270 | .num_resources = 1, | |
271 | }, | |
272 | }; | |
273 | ||
4a730719 RK |
274 | static struct platform_pwm_backlight_data lpd270_backlight_data = { |
275 | .pwm_id = 0, | |
276 | .max_brightness = 1, | |
277 | .dft_brightness = 1, | |
278 | .pwm_period_ns = 78770, | |
db01120c | 279 | .enable_gpio = -1, |
4a730719 RK |
280 | }; |
281 | ||
282 | static struct platform_device lpd270_backlight_device = { | |
283 | .name = "pwm-backlight", | |
284 | .dev = { | |
285 | .parent = &pxa27x_device_pwm0.dev, | |
286 | .platform_data = &lpd270_backlight_data, | |
287 | }, | |
288 | }; | |
e9937d4b LB |
289 | |
290 | /* 5.7" TFT QVGA (LoLo display number 1) */ | |
d14b272b | 291 | static struct pxafb_mode_info sharp_lq057q3dc02_mode = { |
65660297 LB |
292 | .pixclock = 150000, |
293 | .xres = 320, | |
294 | .yres = 240, | |
e9937d4b | 295 | .bpp = 16, |
65660297 LB |
296 | .hsync_len = 0x14, |
297 | .left_margin = 0x28, | |
298 | .right_margin = 0x0a, | |
299 | .vsync_len = 0x02, | |
e9937d4b LB |
300 | .upper_margin = 0x08, |
301 | .lower_margin = 0x14, | |
65660297 | 302 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
d14b272b RP |
303 | }; |
304 | ||
305 | static struct pxafb_mach_info sharp_lq057q3dc02 = { | |
306 | .modes = &sharp_lq057q3dc02_mode, | |
307 | .num_modes = 1, | |
0219e835 EM |
308 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL | |
309 | LCD_ALTERNATE_MAPPING, | |
65660297 LB |
310 | }; |
311 | ||
312 | /* 12.1" TFT SVGA (LoLo display number 2) */ | |
d14b272b | 313 | static struct pxafb_mode_info sharp_lq121s1dg31_mode = { |
65660297 LB |
314 | .pixclock = 50000, |
315 | .xres = 800, | |
316 | .yres = 600, | |
317 | .bpp = 16, | |
318 | .hsync_len = 0x05, | |
319 | .left_margin = 0x52, | |
320 | .right_margin = 0x05, | |
321 | .vsync_len = 0x04, | |
322 | .upper_margin = 0x14, | |
323 | .lower_margin = 0x0a, | |
324 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
d14b272b RP |
325 | }; |
326 | ||
327 | static struct pxafb_mach_info sharp_lq121s1dg31 = { | |
328 | .modes = &sharp_lq121s1dg31_mode, | |
329 | .num_modes = 1, | |
0219e835 EM |
330 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL | |
331 | LCD_ALTERNATE_MAPPING, | |
65660297 LB |
332 | }; |
333 | ||
334 | /* 3.6" TFT QVGA (LoLo display number 3) */ | |
d14b272b | 335 | static struct pxafb_mode_info sharp_lq036q1da01_mode = { |
65660297 LB |
336 | .pixclock = 150000, |
337 | .xres = 320, | |
338 | .yres = 240, | |
339 | .bpp = 16, | |
340 | .hsync_len = 0x0e, | |
341 | .left_margin = 0x04, | |
342 | .right_margin = 0x0a, | |
343 | .vsync_len = 0x03, | |
344 | .upper_margin = 0x03, | |
345 | .lower_margin = 0x03, | |
346 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
d14b272b RP |
347 | }; |
348 | ||
349 | static struct pxafb_mach_info sharp_lq036q1da01 = { | |
350 | .modes = &sharp_lq036q1da01_mode, | |
351 | .num_modes = 1, | |
0219e835 EM |
352 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL | |
353 | LCD_ALTERNATE_MAPPING, | |
e9937d4b LB |
354 | }; |
355 | ||
356 | /* 6.4" TFT VGA (LoLo display number 5) */ | |
d14b272b | 357 | static struct pxafb_mode_info sharp_lq64d343_mode = { |
65660297 | 358 | .pixclock = 25000, |
e9937d4b LB |
359 | .xres = 640, |
360 | .yres = 480, | |
361 | .bpp = 16, | |
65660297 | 362 | .hsync_len = 0x31, |
e9937d4b LB |
363 | .left_margin = 0x89, |
364 | .right_margin = 0x19, | |
65660297 | 365 | .vsync_len = 0x12, |
e9937d4b | 366 | .upper_margin = 0x22, |
65660297 | 367 | .lower_margin = 0x00, |
e9937d4b | 368 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
d14b272b RP |
369 | }; |
370 | ||
371 | static struct pxafb_mach_info sharp_lq64d343 = { | |
372 | .modes = &sharp_lq64d343_mode, | |
373 | .num_modes = 1, | |
0219e835 EM |
374 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL | |
375 | LCD_ALTERNATE_MAPPING, | |
65660297 LB |
376 | }; |
377 | ||
378 | /* 10.4" TFT VGA (LoLo display number 7) */ | |
d14b272b | 379 | static struct pxafb_mode_info sharp_lq10d368_mode = { |
65660297 LB |
380 | .pixclock = 25000, |
381 | .xres = 640, | |
382 | .yres = 480, | |
383 | .bpp = 16, | |
384 | .hsync_len = 0x31, | |
385 | .left_margin = 0x89, | |
386 | .right_margin = 0x19, | |
387 | .vsync_len = 0x12, | |
388 | .upper_margin = 0x22, | |
389 | .lower_margin = 0x00, | |
390 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
d14b272b RP |
391 | }; |
392 | ||
393 | static struct pxafb_mach_info sharp_lq10d368 = { | |
394 | .modes = &sharp_lq10d368_mode, | |
395 | .num_modes = 1, | |
0219e835 EM |
396 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL | |
397 | LCD_ALTERNATE_MAPPING, | |
e9937d4b LB |
398 | }; |
399 | ||
400 | /* 3.5" TFT QVGA (LoLo display number 8) */ | |
d14b272b | 401 | static struct pxafb_mode_info sharp_lq035q7db02_20_mode = { |
65660297 | 402 | .pixclock = 150000, |
e9937d4b LB |
403 | .xres = 240, |
404 | .yres = 320, | |
405 | .bpp = 16, | |
65660297 LB |
406 | .hsync_len = 0x0e, |
407 | .left_margin = 0x0a, | |
408 | .right_margin = 0x0a, | |
409 | .vsync_len = 0x03, | |
e9937d4b LB |
410 | .upper_margin = 0x05, |
411 | .lower_margin = 0x14, | |
65660297 | 412 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
d14b272b RP |
413 | }; |
414 | ||
415 | static struct pxafb_mach_info sharp_lq035q7db02_20 = { | |
416 | .modes = &sharp_lq035q7db02_20_mode, | |
417 | .num_modes = 1, | |
0219e835 EM |
418 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL | |
419 | LCD_ALTERNATE_MAPPING, | |
e9937d4b LB |
420 | }; |
421 | ||
65660297 LB |
422 | static struct pxafb_mach_info *lpd270_lcd_to_use; |
423 | ||
424 | static int __init lpd270_set_lcd(char *str) | |
425 | { | |
2bebf5cb | 426 | if (!strncasecmp(str, "lq057q3dc02", 11)) { |
65660297 | 427 | lpd270_lcd_to_use = &sharp_lq057q3dc02; |
2bebf5cb | 428 | } else if (!strncasecmp(str, "lq121s1dg31", 11)) { |
65660297 | 429 | lpd270_lcd_to_use = &sharp_lq121s1dg31; |
2bebf5cb | 430 | } else if (!strncasecmp(str, "lq036q1da01", 11)) { |
65660297 | 431 | lpd270_lcd_to_use = &sharp_lq036q1da01; |
2bebf5cb | 432 | } else if (!strncasecmp(str, "lq64d343", 8)) { |
65660297 | 433 | lpd270_lcd_to_use = &sharp_lq64d343; |
2bebf5cb | 434 | } else if (!strncasecmp(str, "lq10d368", 8)) { |
65660297 | 435 | lpd270_lcd_to_use = &sharp_lq10d368; |
2bebf5cb | 436 | } else if (!strncasecmp(str, "lq035q7db02-20", 14)) { |
65660297 LB |
437 | lpd270_lcd_to_use = &sharp_lq035q7db02_20; |
438 | } else { | |
439 | printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str); | |
440 | } | |
441 | ||
442 | return 1; | |
443 | } | |
444 | ||
445 | __setup("lcd=", lpd270_set_lcd); | |
446 | ||
e9937d4b LB |
447 | static struct platform_device *platform_devices[] __initdata = { |
448 | &smc91x_device, | |
4a730719 | 449 | &lpd270_backlight_device, |
e9937d4b LB |
450 | &lpd270_flash_device[0], |
451 | &lpd270_flash_device[1], | |
452 | }; | |
453 | ||
e9937d4b LB |
454 | static struct pxaohci_platform_data lpd270_ohci_platform_data = { |
455 | .port_mode = PMM_PERPORT_MODE, | |
097b5334 | 456 | .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW, |
e9937d4b LB |
457 | }; |
458 | ||
459 | static void __init lpd270_init(void) | |
460 | { | |
fd90ff20 EM |
461 | pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config)); |
462 | ||
cc155c6f RK |
463 | pxa_set_ffuart_info(NULL); |
464 | pxa_set_btuart_info(NULL); | |
465 | pxa_set_stuart_info(NULL); | |
466 | ||
ad68bb9f | 467 | lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4; |
e9937d4b LB |
468 | lpd270_flash_data[1].width = 4; |
469 | ||
470 | /* | |
471 | * System bus arbiter setting: | |
472 | * - Core_Park | |
473 | * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4 | |
474 | */ | |
475 | ARB_CNTRL = ARB_CORE_PARK | 0x234; | |
476 | ||
e9937d4b LB |
477 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
478 | ||
9f19d638 MB |
479 | pxa_set_ac97_info(NULL); |
480 | ||
65660297 | 481 | if (lpd270_lcd_to_use != NULL) |
4321e1a1 | 482 | pxa_set_fb_info(NULL, lpd270_lcd_to_use); |
e9937d4b LB |
483 | |
484 | pxa_set_ohci_info(&lpd270_ohci_platform_data); | |
485 | } | |
486 | ||
487 | ||
488 | static struct map_desc lpd270_io_desc[] __initdata = { | |
489 | { | |
97b09da4 | 490 | .virtual = (unsigned long)LPD270_CPLD_VIRT, |
e9937d4b LB |
491 | .pfn = __phys_to_pfn(LPD270_CPLD_PHYS), |
492 | .length = LPD270_CPLD_SIZE, | |
493 | .type = MT_DEVICE, | |
494 | }, | |
495 | }; | |
496 | ||
497 | static void __init lpd270_map_io(void) | |
498 | { | |
851982c1 | 499 | pxa27x_map_io(); |
e9937d4b LB |
500 | iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc)); |
501 | ||
e9937d4b LB |
502 | /* for use I SRAM as framebuffer. */ |
503 | PSLR |= 0x00000F04; | |
504 | PCFR = 0x00000066; | |
505 | } | |
506 | ||
507 | MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine") | |
508 | /* Maintainer: Peter Barada */ | |
7375aba6 | 509 | .atag_offset = 0x100, |
e9937d4b | 510 | .map_io = lpd270_map_io, |
6ac6b817 | 511 | .nr_irqs = LPD270_NR_IRQS, |
e9937d4b | 512 | .init_irq = lpd270_init_irq, |
8a97ae2f | 513 | .handle_irq = pxa27x_handle_irq, |
6bb27d73 | 514 | .init_time = pxa_timer_init, |
e9937d4b | 515 | .init_machine = lpd270_init, |
271a74fc | 516 | .restart = pxa_restart, |
e9937d4b | 517 | MACHINE_END |