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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/mainstone.c | |
3 | * | |
4 | * Support for the Intel HCDDBBVA0 Development Platform. | |
5 | * (go figure how they came up with such name...) | |
6 | * | |
7 | * Author: Nicolas Pitre | |
8 | * Created: Nov 05, 2002 | |
9 | * Copyright: MontaVista Software Inc. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
d052d1be | 17 | #include <linux/platform_device.h> |
22f11c4e | 18 | #include <linux/sysdev.h> |
1da177e4 LT |
19 | #include <linux/interrupt.h> |
20 | #include <linux/sched.h> | |
21 | #include <linux/bitops.h> | |
22 | #include <linux/fb.h> | |
74ec71e1 TP |
23 | #include <linux/ioport.h> |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mtd/partitions.h> | |
3777f774 | 26 | #include <linux/backlight.h> |
450d2874 | 27 | #include <linux/input.h> |
28 | #include <linux/gpio_keys.h> | |
1da177e4 LT |
29 | |
30 | #include <asm/types.h> | |
31 | #include <asm/setup.h> | |
32 | #include <asm/memory.h> | |
33 | #include <asm/mach-types.h> | |
34 | #include <asm/hardware.h> | |
35 | #include <asm/irq.h> | |
74ec71e1 | 36 | #include <asm/sizes.h> |
1da177e4 LT |
37 | |
38 | #include <asm/mach/arch.h> | |
39 | #include <asm/mach/map.h> | |
40 | #include <asm/mach/irq.h> | |
74ec71e1 | 41 | #include <asm/mach/flash.h> |
1da177e4 LT |
42 | |
43 | #include <asm/arch/pxa-regs.h> | |
8785a8fb | 44 | #include <asm/arch/pxa2xx-regs.h> |
fef06d27 | 45 | #include <asm/arch/mfp-pxa27x.h> |
1da177e4 LT |
46 | #include <asm/arch/mainstone.h> |
47 | #include <asm/arch/audio.h> | |
48 | #include <asm/arch/pxafb.h> | |
49 | #include <asm/arch/mmc.h> | |
6f475c01 | 50 | #include <asm/arch/irda.h> |
81f280e2 | 51 | #include <asm/arch/ohci.h> |
55c26e40 | 52 | #include <asm/arch/pxa27x_keypad.h> |
1da177e4 LT |
53 | |
54 | #include "generic.h" | |
46c41e62 | 55 | #include "devices.h" |
1da177e4 | 56 | |
fef06d27 | 57 | static unsigned long mainstone_pin_config[] = { |
58 | /* Chip Select */ | |
59 | GPIO15_nCS_1, | |
60 | ||
61 | /* LCD - 16bpp Active TFT */ | |
62 | GPIO58_LCD_LDD_0, | |
63 | GPIO59_LCD_LDD_1, | |
64 | GPIO60_LCD_LDD_2, | |
65 | GPIO61_LCD_LDD_3, | |
66 | GPIO62_LCD_LDD_4, | |
67 | GPIO63_LCD_LDD_5, | |
68 | GPIO64_LCD_LDD_6, | |
69 | GPIO65_LCD_LDD_7, | |
70 | GPIO66_LCD_LDD_8, | |
71 | GPIO67_LCD_LDD_9, | |
72 | GPIO68_LCD_LDD_10, | |
73 | GPIO69_LCD_LDD_11, | |
74 | GPIO70_LCD_LDD_12, | |
75 | GPIO71_LCD_LDD_13, | |
76 | GPIO72_LCD_LDD_14, | |
77 | GPIO73_LCD_LDD_15, | |
78 | GPIO74_LCD_FCLK, | |
79 | GPIO75_LCD_LCLK, | |
80 | GPIO76_LCD_PCLK, | |
81 | GPIO77_LCD_BIAS, | |
82 | GPIO16_PWM0_OUT, /* Backlight */ | |
83 | ||
84 | /* MMC */ | |
85 | GPIO32_MMC_CLK, | |
86 | GPIO112_MMC_CMD, | |
87 | GPIO92_MMC_DAT_0, | |
88 | GPIO109_MMC_DAT_1, | |
89 | GPIO110_MMC_DAT_2, | |
90 | GPIO111_MMC_DAT_3, | |
91 | ||
92 | /* USB Host Port 1 */ | |
93 | GPIO88_USBH1_PWR, | |
94 | GPIO89_USBH1_PEN, | |
95 | ||
96 | /* PC Card */ | |
97 | GPIO48_nPOE, | |
98 | GPIO49_nPWE, | |
99 | GPIO50_nPIOR, | |
100 | GPIO51_nPIOW, | |
101 | GPIO85_nPCE_1, | |
102 | GPIO54_nPCE_2, | |
103 | GPIO79_PSKTSEL, | |
104 | GPIO55_nPREG, | |
105 | GPIO56_nPWAIT, | |
106 | GPIO57_nIOIS16, | |
107 | ||
108 | /* AC97 */ | |
109 | GPIO45_AC97_SYSCLK, | |
110 | ||
111 | /* Keypad */ | |
112 | GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, | |
113 | GPIO94_KP_DKIN_1 | WAKEUP_ON_LEVEL_HIGH, | |
114 | GPIO95_KP_DKIN_2 | WAKEUP_ON_LEVEL_HIGH, | |
115 | GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, | |
116 | GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, | |
117 | GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, | |
118 | GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, | |
119 | GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, | |
120 | GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH, | |
121 | GPIO103_KP_MKOUT_0, | |
122 | GPIO104_KP_MKOUT_1, | |
123 | GPIO105_KP_MKOUT_2, | |
124 | GPIO106_KP_MKOUT_3, | |
125 | GPIO107_KP_MKOUT_4, | |
126 | GPIO108_KP_MKOUT_5, | |
127 | GPIO96_KP_MKOUT_6, | |
128 | ||
129 | /* GPIO */ | |
130 | GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, | |
131 | }; | |
1da177e4 LT |
132 | |
133 | static unsigned long mainstone_irq_enabled; | |
134 | ||
135 | static void mainstone_mask_irq(unsigned int irq) | |
136 | { | |
137 | int mainstone_irq = (irq - MAINSTONE_IRQ(0)); | |
138 | MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq)); | |
139 | } | |
140 | ||
141 | static void mainstone_unmask_irq(unsigned int irq) | |
142 | { | |
143 | int mainstone_irq = (irq - MAINSTONE_IRQ(0)); | |
144 | /* the irq can be acknowledged only if deasserted, so it's done here */ | |
145 | MST_INTSETCLR &= ~(1 << mainstone_irq); | |
146 | MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq)); | |
147 | } | |
148 | ||
38c677cb DB |
149 | static struct irq_chip mainstone_irq_chip = { |
150 | .name = "FPGA", | |
1da177e4 LT |
151 | .ack = mainstone_mask_irq, |
152 | .mask = mainstone_mask_irq, | |
153 | .unmask = mainstone_unmask_irq, | |
154 | }; | |
155 | ||
10dd5ce2 | 156 | static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc) |
1da177e4 LT |
157 | { |
158 | unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled; | |
159 | do { | |
160 | GEDR(0) = GPIO_bit(0); /* clear useless edge notification */ | |
161 | if (likely(pending)) { | |
162 | irq = MAINSTONE_IRQ(0) + __ffs(pending); | |
163 | desc = irq_desc + irq; | |
0cd61b68 | 164 | desc_handle_irq(irq, desc); |
1da177e4 LT |
165 | } |
166 | pending = MST_INTSETCLR & mainstone_irq_enabled; | |
167 | } while (pending); | |
168 | } | |
169 | ||
170 | static void __init mainstone_init_irq(void) | |
171 | { | |
172 | int irq; | |
173 | ||
cd49104d | 174 | pxa27x_init_irq(); |
1da177e4 LT |
175 | |
176 | /* setup extra Mainstone irqs */ | |
177 | for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { | |
178 | set_irq_chip(irq, &mainstone_irq_chip); | |
10dd5ce2 | 179 | set_irq_handler(irq, handle_level_irq); |
ec64152f TG |
180 | if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) |
181 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); | |
182 | else | |
183 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
1da177e4 LT |
184 | } |
185 | set_irq_flags(MAINSTONE_IRQ(8), 0); | |
186 | set_irq_flags(MAINSTONE_IRQ(12), 0); | |
187 | ||
188 | MST_INTMSKENA = 0; | |
189 | MST_INTSETCLR = 0; | |
190 | ||
191 | set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); | |
192 | set_irq_type(IRQ_GPIO(0), IRQT_FALLING); | |
193 | } | |
194 | ||
22f11c4e NP |
195 | #ifdef CONFIG_PM |
196 | ||
197 | static int mainstone_irq_resume(struct sys_device *dev) | |
198 | { | |
199 | MST_INTMSKENA = mainstone_irq_enabled; | |
200 | return 0; | |
201 | } | |
202 | ||
203 | static struct sysdev_class mainstone_irq_sysclass = { | |
af5ca3f4 | 204 | .name = "cpld_irq", |
22f11c4e NP |
205 | .resume = mainstone_irq_resume, |
206 | }; | |
207 | ||
208 | static struct sys_device mainstone_irq_device = { | |
209 | .cls = &mainstone_irq_sysclass, | |
210 | }; | |
211 | ||
212 | static int __init mainstone_irq_device_init(void) | |
213 | { | |
16f159b1 RK |
214 | int ret = -ENODEV; |
215 | ||
216 | if (machine_is_mainstone()) { | |
217 | ret = sysdev_class_register(&mainstone_irq_sysclass); | |
218 | if (ret == 0) | |
219 | ret = sysdev_register(&mainstone_irq_device); | |
220 | } | |
22f11c4e NP |
221 | return ret; |
222 | } | |
223 | ||
224 | device_initcall(mainstone_irq_device_init); | |
225 | ||
226 | #endif | |
227 | ||
1da177e4 LT |
228 | |
229 | static struct resource smc91x_resources[] = { | |
230 | [0] = { | |
231 | .start = (MST_ETH_PHYS + 0x300), | |
232 | .end = (MST_ETH_PHYS + 0xfffff), | |
233 | .flags = IORESOURCE_MEM, | |
234 | }, | |
235 | [1] = { | |
236 | .start = MAINSTONE_IRQ(3), | |
237 | .end = MAINSTONE_IRQ(3), | |
e7b3dc7e | 238 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, |
1da177e4 LT |
239 | } |
240 | }; | |
241 | ||
242 | static struct platform_device smc91x_device = { | |
243 | .name = "smc91x", | |
244 | .id = 0, | |
245 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
246 | .resource = smc91x_resources, | |
247 | }; | |
248 | ||
f7cbb7fc | 249 | static int mst_audio_startup(struct snd_pcm_substream *substream, void *priv) |
1da177e4 LT |
250 | { |
251 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
252 | MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF; | |
253 | return 0; | |
254 | } | |
255 | ||
f7cbb7fc | 256 | static void mst_audio_shutdown(struct snd_pcm_substream *substream, void *priv) |
1da177e4 LT |
257 | { |
258 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
259 | MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF; | |
260 | } | |
261 | ||
262 | static long mst_audio_suspend_mask; | |
263 | ||
264 | static void mst_audio_suspend(void *priv) | |
265 | { | |
266 | mst_audio_suspend_mask = MST_MSCWR2; | |
267 | MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF; | |
268 | } | |
269 | ||
270 | static void mst_audio_resume(void *priv) | |
271 | { | |
272 | MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF; | |
273 | } | |
274 | ||
275 | static pxa2xx_audio_ops_t mst_audio_ops = { | |
276 | .startup = mst_audio_startup, | |
277 | .shutdown = mst_audio_shutdown, | |
278 | .suspend = mst_audio_suspend, | |
279 | .resume = mst_audio_resume, | |
280 | }; | |
281 | ||
282 | static struct platform_device mst_audio_device = { | |
283 | .name = "pxa2xx-ac97", | |
284 | .id = -1, | |
285 | .dev = { .platform_data = &mst_audio_ops }, | |
286 | }; | |
287 | ||
74ec71e1 TP |
288 | static struct resource flash_resources[] = { |
289 | [0] = { | |
290 | .start = PXA_CS0_PHYS, | |
291 | .end = PXA_CS0_PHYS + SZ_64M - 1, | |
292 | .flags = IORESOURCE_MEM, | |
293 | }, | |
294 | [1] = { | |
295 | .start = PXA_CS1_PHYS, | |
296 | .end = PXA_CS1_PHYS + SZ_64M - 1, | |
297 | .flags = IORESOURCE_MEM, | |
298 | }, | |
299 | }; | |
300 | ||
301 | static struct mtd_partition mainstoneflash0_partitions[] = { | |
302 | { | |
303 | .name = "Bootloader", | |
304 | .size = 0x00040000, | |
305 | .offset = 0, | |
306 | .mask_flags = MTD_WRITEABLE /* force read-only */ | |
307 | },{ | |
308 | .name = "Kernel", | |
309 | .size = 0x00400000, | |
310 | .offset = 0x00040000, | |
311 | },{ | |
312 | .name = "Filesystem", | |
313 | .size = MTDPART_SIZ_FULL, | |
314 | .offset = 0x00440000 | |
315 | } | |
316 | }; | |
317 | ||
318 | static struct flash_platform_data mst_flash_data[2] = { | |
319 | { | |
320 | .map_name = "cfi_probe", | |
321 | .parts = mainstoneflash0_partitions, | |
322 | .nr_parts = ARRAY_SIZE(mainstoneflash0_partitions), | |
323 | }, { | |
324 | .map_name = "cfi_probe", | |
325 | .parts = NULL, | |
326 | .nr_parts = 0, | |
327 | } | |
328 | }; | |
329 | ||
330 | static struct platform_device mst_flash_device[2] = { | |
331 | { | |
332 | .name = "pxa2xx-flash", | |
333 | .id = 0, | |
334 | .dev = { | |
335 | .platform_data = &mst_flash_data[0], | |
336 | }, | |
337 | .resource = &flash_resources[0], | |
338 | .num_resources = 1, | |
339 | }, | |
340 | { | |
341 | .name = "pxa2xx-flash", | |
342 | .id = 1, | |
343 | .dev = { | |
344 | .platform_data = &mst_flash_data[1], | |
345 | }, | |
346 | .resource = &flash_resources[1], | |
347 | .num_resources = 1, | |
348 | }, | |
349 | }; | |
350 | ||
3777f774 RK |
351 | #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE |
352 | static int mainstone_backlight_update_status(struct backlight_device *bl) | |
1da177e4 | 353 | { |
3777f774 RK |
354 | int brightness = bl->props.brightness; |
355 | ||
356 | if (bl->props.power != FB_BLANK_UNBLANK || | |
357 | bl->props.fb_blank != FB_BLANK_UNBLANK) | |
358 | brightness = 0; | |
359 | ||
fef06d27 | 360 | if (brightness != 0) |
7053acbd | 361 | pxa_set_cken(CKEN_PWM0, 1); |
fef06d27 | 362 | |
3777f774 RK |
363 | PWM_CTRL0 = 0; |
364 | PWM_PWDUTY0 = brightness; | |
365 | PWM_PERVAL0 = bl->props.max_brightness; | |
fef06d27 | 366 | |
3777f774 | 367 | if (brightness == 0) |
7053acbd | 368 | pxa_set_cken(CKEN_PWM0, 0); |
3777f774 RK |
369 | return 0; /* pointless return value */ |
370 | } | |
371 | ||
372 | static int mainstone_backlight_get_brightness(struct backlight_device *bl) | |
373 | { | |
374 | return PWM_PWDUTY0; | |
375 | } | |
376 | ||
377 | static /*const*/ struct backlight_ops mainstone_backlight_ops = { | |
378 | .update_status = mainstone_backlight_update_status, | |
379 | .get_brightness = mainstone_backlight_get_brightness, | |
380 | }; | |
381 | ||
382 | static void __init mainstone_backlight_register(void) | |
383 | { | |
384 | struct backlight_device *bl; | |
385 | ||
386 | bl = backlight_device_register("mainstone-bl", &pxa_device_fb.dev, | |
387 | NULL, &mainstone_backlight_ops); | |
388 | if (IS_ERR(bl)) { | |
389 | printk(KERN_ERR "mainstone: unable to register backlight: %ld\n", | |
390 | PTR_ERR(bl)); | |
391 | return; | |
1da177e4 | 392 | } |
3777f774 RK |
393 | |
394 | /* | |
395 | * broken design - register-then-setup interfaces are | |
396 | * utterly broken by definition. | |
397 | */ | |
398 | bl->props.max_brightness = 1023; | |
399 | bl->props.brightness = 1023; | |
400 | backlight_update_status(bl); | |
1da177e4 | 401 | } |
3777f774 RK |
402 | #else |
403 | #define mainstone_backlight_register() do { } while (0) | |
404 | #endif | |
1da177e4 | 405 | |
d14b272b | 406 | static struct pxafb_mode_info toshiba_ltm04c380k_mode = { |
1da177e4 LT |
407 | .pixclock = 50000, |
408 | .xres = 640, | |
409 | .yres = 480, | |
410 | .bpp = 16, | |
411 | .hsync_len = 1, | |
412 | .left_margin = 0x9f, | |
413 | .right_margin = 1, | |
414 | .vsync_len = 44, | |
415 | .upper_margin = 0, | |
416 | .lower_margin = 0, | |
417 | .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, | |
1da177e4 LT |
418 | }; |
419 | ||
d14b272b | 420 | static struct pxafb_mode_info toshiba_ltm035a776c_mode = { |
1da177e4 LT |
421 | .pixclock = 110000, |
422 | .xres = 240, | |
423 | .yres = 320, | |
424 | .bpp = 16, | |
425 | .hsync_len = 4, | |
426 | .left_margin = 8, | |
427 | .right_margin = 20, | |
428 | .vsync_len = 3, | |
429 | .upper_margin = 1, | |
430 | .lower_margin = 10, | |
431 | .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, | |
d14b272b RP |
432 | }; |
433 | ||
434 | static struct pxafb_mach_info mainstone_pxafb_info = { | |
435 | .num_modes = 1, | |
1da177e4 LT |
436 | .lccr0 = LCCR0_Act, |
437 | .lccr3 = LCCR3_PCP, | |
1da177e4 LT |
438 | }; |
439 | ||
40220c1a | 440 | static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_int, void *data) |
1da177e4 LT |
441 | { |
442 | int err; | |
443 | ||
1da177e4 LT |
444 | /* make sure SD/Memory Stick multiplexer's signals |
445 | * are routed to MMC controller | |
446 | */ | |
447 | MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL; | |
448 | ||
52e405ea | 449 | err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED, |
1da177e4 | 450 | "MMC card detect", data); |
2687bd38 | 451 | if (err) |
1da177e4 | 452 | printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); |
1da177e4 | 453 | |
2687bd38 | 454 | return err; |
1da177e4 LT |
455 | } |
456 | ||
457 | static void mainstone_mci_setpower(struct device *dev, unsigned int vdd) | |
458 | { | |
459 | struct pxamci_platform_data* p_d = dev->platform_data; | |
460 | ||
461 | if (( 1 << vdd) & p_d->ocr_mask) { | |
8e86f427 | 462 | printk(KERN_DEBUG "%s: on\n", __func__); |
1da177e4 LT |
463 | MST_MSCWR1 |= MST_MSCWR1_MMC_ON; |
464 | MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL; | |
465 | } else { | |
8e86f427 | 466 | printk(KERN_DEBUG "%s: off\n", __func__); |
1da177e4 LT |
467 | MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON; |
468 | } | |
469 | } | |
470 | ||
471 | static void mainstone_mci_exit(struct device *dev, void *data) | |
472 | { | |
473 | free_irq(MAINSTONE_MMC_IRQ, data); | |
474 | } | |
475 | ||
476 | static struct pxamci_platform_data mainstone_mci_platform_data = { | |
477 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | |
478 | .init = mainstone_mci_init, | |
479 | .setpower = mainstone_mci_setpower, | |
480 | .exit = mainstone_mci_exit, | |
481 | }; | |
482 | ||
6f475c01 NP |
483 | static void mainstone_irda_transceiver_mode(struct device *dev, int mode) |
484 | { | |
485 | unsigned long flags; | |
486 | ||
487 | local_irq_save(flags); | |
488 | if (mode & IR_SIRMODE) { | |
489 | MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR; | |
490 | } else if (mode & IR_FIRMODE) { | |
491 | MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR; | |
492 | } | |
493 | if (mode & IR_OFF) { | |
494 | MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF; | |
495 | } else { | |
496 | MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL; | |
497 | } | |
498 | local_irq_restore(flags); | |
499 | } | |
500 | ||
501 | static struct pxaficp_platform_data mainstone_ficp_platform_data = { | |
502 | .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF, | |
503 | .transceiver_mode = mainstone_irda_transceiver_mode, | |
504 | }; | |
505 | ||
450d2874 | 506 | static struct gpio_keys_button gpio_keys_button[] = { |
507 | [0] = { | |
508 | .desc = "wakeup", | |
509 | .code = KEY_SUSPEND, | |
510 | .type = EV_KEY, | |
511 | .gpio = 1, | |
512 | .wakeup = 1, | |
513 | }, | |
514 | }; | |
515 | ||
516 | static struct gpio_keys_platform_data mainstone_gpio_keys = { | |
517 | .buttons = gpio_keys_button, | |
518 | .nbuttons = 1, | |
519 | }; | |
520 | ||
521 | static struct platform_device mst_gpio_keys_device = { | |
522 | .name = "gpio-keys", | |
523 | .id = -1, | |
524 | .dev = { | |
525 | .platform_data = &mainstone_gpio_keys, | |
526 | }, | |
527 | }; | |
528 | ||
74ec71e1 TP |
529 | static struct platform_device *platform_devices[] __initdata = { |
530 | &smc91x_device, | |
531 | &mst_audio_device, | |
532 | &mst_flash_device[0], | |
533 | &mst_flash_device[1], | |
450d2874 | 534 | &mst_gpio_keys_device, |
74ec71e1 TP |
535 | }; |
536 | ||
81f280e2 RP |
537 | static int mainstone_ohci_init(struct device *dev) |
538 | { | |
81f280e2 RP |
539 | /* Set the Power Control Polarity Low and Power Sense |
540 | Polarity Low to active low. */ | |
541 | UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & | |
542 | ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE); | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
547 | static struct pxaohci_platform_data mainstone_ohci_platform_data = { | |
548 | .port_mode = PMM_PERPORT_MODE, | |
549 | .init = mainstone_ohci_init, | |
550 | }; | |
551 | ||
55c26e40 | 552 | #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES) |
553 | static unsigned int mainstone_matrix_keys[] = { | |
554 | KEY(0, 0, KEY_A), KEY(1, 0, KEY_B), KEY(2, 0, KEY_C), | |
555 | KEY(3, 0, KEY_D), KEY(4, 0, KEY_E), KEY(5, 0, KEY_F), | |
556 | KEY(0, 1, KEY_G), KEY(1, 1, KEY_H), KEY(2, 1, KEY_I), | |
557 | KEY(3, 1, KEY_J), KEY(4, 1, KEY_K), KEY(5, 1, KEY_L), | |
558 | KEY(0, 2, KEY_M), KEY(1, 2, KEY_N), KEY(2, 2, KEY_O), | |
559 | KEY(3, 2, KEY_P), KEY(4, 2, KEY_Q), KEY(5, 2, KEY_R), | |
560 | KEY(0, 3, KEY_S), KEY(1, 3, KEY_T), KEY(2, 3, KEY_U), | |
561 | KEY(3, 3, KEY_V), KEY(4, 3, KEY_W), KEY(5, 3, KEY_X), | |
562 | KEY(2, 4, KEY_Y), KEY(3, 4, KEY_Z), | |
563 | ||
564 | KEY(0, 4, KEY_DOT), /* . */ | |
565 | KEY(1, 4, KEY_CLOSE), /* @ */ | |
566 | KEY(4, 4, KEY_SLASH), | |
567 | KEY(5, 4, KEY_BACKSLASH), | |
568 | KEY(0, 5, KEY_HOME), | |
569 | KEY(1, 5, KEY_LEFTSHIFT), | |
570 | KEY(2, 5, KEY_SPACE), | |
571 | KEY(3, 5, KEY_SPACE), | |
572 | KEY(4, 5, KEY_ENTER), | |
573 | KEY(5, 5, KEY_BACKSPACE), | |
574 | ||
575 | KEY(0, 6, KEY_UP), | |
576 | KEY(1, 6, KEY_DOWN), | |
577 | KEY(2, 6, KEY_LEFT), | |
578 | KEY(3, 6, KEY_RIGHT), | |
579 | KEY(4, 6, KEY_SELECT), | |
580 | }; | |
581 | ||
582 | struct pxa27x_keypad_platform_data mainstone_keypad_info = { | |
583 | .matrix_key_rows = 6, | |
584 | .matrix_key_cols = 7, | |
585 | .matrix_key_map = mainstone_matrix_keys, | |
586 | .matrix_key_map_size = ARRAY_SIZE(mainstone_matrix_keys), | |
587 | ||
588 | .enable_rotary0 = 1, | |
589 | .rotary0_up_key = KEY_UP, | |
590 | .rotary0_down_key = KEY_DOWN, | |
591 | ||
592 | .debounce_interval = 30, | |
593 | }; | |
594 | ||
595 | static void __init mainstone_init_keypad(void) | |
596 | { | |
597 | pxa_set_keypad_info(&mainstone_keypad_info); | |
598 | } | |
599 | #else | |
600 | static inline void mainstone_init_keypad(void) {} | |
601 | #endif | |
602 | ||
1da177e4 LT |
603 | static void __init mainstone_init(void) |
604 | { | |
74ec71e1 TP |
605 | int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */ |
606 | ||
fef06d27 | 607 | pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config)); |
608 | ||
74ec71e1 TP |
609 | mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; |
610 | mst_flash_data[1].width = 4; | |
611 | ||
612 | /* Compensate for SW7 which swaps the flash banks */ | |
613 | mst_flash_data[SW7].name = "processor-flash"; | |
614 | mst_flash_data[SW7 ^ 1].name = "mainboard-flash"; | |
615 | ||
616 | printk(KERN_NOTICE "Mainstone configured to boot from %s\n", | |
617 | mst_flash_data[0].name); | |
618 | ||
5b2e98cd JH |
619 | /* system bus arbiter setting |
620 | * - Core_Park | |
621 | * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4 | |
622 | */ | |
623 | ARB_CNTRL = ARB_CORE_PARK | 0x234; | |
624 | ||
74ec71e1 | 625 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
1da177e4 LT |
626 | |
627 | /* reading Mainstone's "Virtual Configuration Register" | |
628 | might be handy to select LCD type here */ | |
629 | if (0) | |
d14b272b | 630 | mainstone_pxafb_info.modes = &toshiba_ltm04c380k_mode; |
1da177e4 | 631 | else |
d14b272b RP |
632 | mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode; |
633 | ||
634 | set_pxa_fb_info(&mainstone_pxafb_info); | |
3777f774 | 635 | mainstone_backlight_register(); |
1da177e4 LT |
636 | |
637 | pxa_set_mci_info(&mainstone_mci_platform_data); | |
6f475c01 | 638 | pxa_set_ficp_info(&mainstone_ficp_platform_data); |
81f280e2 | 639 | pxa_set_ohci_info(&mainstone_ohci_platform_data); |
55c26e40 | 640 | |
641 | mainstone_init_keypad(); | |
1da177e4 LT |
642 | } |
643 | ||
644 | ||
645 | static struct map_desc mainstone_io_desc[] __initdata = { | |
6f9182eb DS |
646 | { /* CPLD */ |
647 | .virtual = MST_FPGA_VIRT, | |
648 | .pfn = __phys_to_pfn(MST_FPGA_PHYS), | |
649 | .length = 0x00100000, | |
650 | .type = MT_DEVICE | |
651 | } | |
1da177e4 LT |
652 | }; |
653 | ||
654 | static void __init mainstone_map_io(void) | |
655 | { | |
656 | pxa_map_io(); | |
657 | iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc)); | |
658 | ||
8775420d TP |
659 | /* for use I SRAM as framebuffer. */ |
660 | PSLR |= 0xF04; | |
661 | PCFR = 0x66; | |
1da177e4 LT |
662 | } |
663 | ||
664 | MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)") | |
e9dea0c6 | 665 | /* Maintainer: MontaVista Software Inc. */ |
e9dea0c6 | 666 | .phys_io = 0x40000000, |
a7d14f87 | 667 | .boot_params = 0xa0000100, /* BLOB boot parameter setting */ |
68070bde | 668 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, |
e9dea0c6 RK |
669 | .map_io = mainstone_map_io, |
670 | .init_irq = mainstone_init_irq, | |
1da177e4 | 671 | .timer = &pxa_timer, |
e9dea0c6 | 672 | .init_machine = mainstone_init, |
1da177e4 | 673 | MACHINE_END |