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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/mainstone.c | |
3 | * | |
4 | * Support for the Intel HCDDBBVA0 Development Platform. | |
5 | * (go figure how they came up with such name...) | |
6 | * | |
7 | * Author: Nicolas Pitre | |
8 | * Created: Nov 05, 2002 | |
9 | * Copyright: MontaVista Software Inc. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
d052d1be | 17 | #include <linux/platform_device.h> |
22f11c4e | 18 | #include <linux/sysdev.h> |
1da177e4 LT |
19 | #include <linux/interrupt.h> |
20 | #include <linux/sched.h> | |
21 | #include <linux/bitops.h> | |
22 | #include <linux/fb.h> | |
74ec71e1 TP |
23 | #include <linux/ioport.h> |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mtd/partitions.h> | |
3777f774 | 26 | #include <linux/backlight.h> |
1da177e4 LT |
27 | |
28 | #include <asm/types.h> | |
29 | #include <asm/setup.h> | |
30 | #include <asm/memory.h> | |
31 | #include <asm/mach-types.h> | |
32 | #include <asm/hardware.h> | |
33 | #include <asm/irq.h> | |
74ec71e1 | 34 | #include <asm/sizes.h> |
1da177e4 LT |
35 | |
36 | #include <asm/mach/arch.h> | |
37 | #include <asm/mach/map.h> | |
38 | #include <asm/mach/irq.h> | |
74ec71e1 | 39 | #include <asm/mach/flash.h> |
1da177e4 LT |
40 | |
41 | #include <asm/arch/pxa-regs.h> | |
8785a8fb | 42 | #include <asm/arch/pxa2xx-regs.h> |
1da177e4 LT |
43 | #include <asm/arch/mainstone.h> |
44 | #include <asm/arch/audio.h> | |
45 | #include <asm/arch/pxafb.h> | |
46 | #include <asm/arch/mmc.h> | |
6f475c01 | 47 | #include <asm/arch/irda.h> |
81f280e2 | 48 | #include <asm/arch/ohci.h> |
1da177e4 LT |
49 | |
50 | #include "generic.h" | |
46c41e62 | 51 | #include "devices.h" |
1da177e4 LT |
52 | |
53 | ||
54 | static unsigned long mainstone_irq_enabled; | |
55 | ||
56 | static void mainstone_mask_irq(unsigned int irq) | |
57 | { | |
58 | int mainstone_irq = (irq - MAINSTONE_IRQ(0)); | |
59 | MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq)); | |
60 | } | |
61 | ||
62 | static void mainstone_unmask_irq(unsigned int irq) | |
63 | { | |
64 | int mainstone_irq = (irq - MAINSTONE_IRQ(0)); | |
65 | /* the irq can be acknowledged only if deasserted, so it's done here */ | |
66 | MST_INTSETCLR &= ~(1 << mainstone_irq); | |
67 | MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq)); | |
68 | } | |
69 | ||
38c677cb DB |
70 | static struct irq_chip mainstone_irq_chip = { |
71 | .name = "FPGA", | |
1da177e4 LT |
72 | .ack = mainstone_mask_irq, |
73 | .mask = mainstone_mask_irq, | |
74 | .unmask = mainstone_unmask_irq, | |
75 | }; | |
76 | ||
10dd5ce2 | 77 | static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc) |
1da177e4 LT |
78 | { |
79 | unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled; | |
80 | do { | |
81 | GEDR(0) = GPIO_bit(0); /* clear useless edge notification */ | |
82 | if (likely(pending)) { | |
83 | irq = MAINSTONE_IRQ(0) + __ffs(pending); | |
84 | desc = irq_desc + irq; | |
0cd61b68 | 85 | desc_handle_irq(irq, desc); |
1da177e4 LT |
86 | } |
87 | pending = MST_INTSETCLR & mainstone_irq_enabled; | |
88 | } while (pending); | |
89 | } | |
90 | ||
91 | static void __init mainstone_init_irq(void) | |
92 | { | |
93 | int irq; | |
94 | ||
cd49104d | 95 | pxa27x_init_irq(); |
1da177e4 LT |
96 | |
97 | /* setup extra Mainstone irqs */ | |
98 | for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { | |
99 | set_irq_chip(irq, &mainstone_irq_chip); | |
10dd5ce2 | 100 | set_irq_handler(irq, handle_level_irq); |
ec64152f TG |
101 | if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) |
102 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); | |
103 | else | |
104 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
1da177e4 LT |
105 | } |
106 | set_irq_flags(MAINSTONE_IRQ(8), 0); | |
107 | set_irq_flags(MAINSTONE_IRQ(12), 0); | |
108 | ||
109 | MST_INTMSKENA = 0; | |
110 | MST_INTSETCLR = 0; | |
111 | ||
112 | set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); | |
113 | set_irq_type(IRQ_GPIO(0), IRQT_FALLING); | |
114 | } | |
115 | ||
22f11c4e NP |
116 | #ifdef CONFIG_PM |
117 | ||
118 | static int mainstone_irq_resume(struct sys_device *dev) | |
119 | { | |
120 | MST_INTMSKENA = mainstone_irq_enabled; | |
121 | return 0; | |
122 | } | |
123 | ||
124 | static struct sysdev_class mainstone_irq_sysclass = { | |
af5ca3f4 | 125 | .name = "cpld_irq", |
22f11c4e NP |
126 | .resume = mainstone_irq_resume, |
127 | }; | |
128 | ||
129 | static struct sys_device mainstone_irq_device = { | |
130 | .cls = &mainstone_irq_sysclass, | |
131 | }; | |
132 | ||
133 | static int __init mainstone_irq_device_init(void) | |
134 | { | |
16f159b1 RK |
135 | int ret = -ENODEV; |
136 | ||
137 | if (machine_is_mainstone()) { | |
138 | ret = sysdev_class_register(&mainstone_irq_sysclass); | |
139 | if (ret == 0) | |
140 | ret = sysdev_register(&mainstone_irq_device); | |
141 | } | |
22f11c4e NP |
142 | return ret; |
143 | } | |
144 | ||
145 | device_initcall(mainstone_irq_device_init); | |
146 | ||
147 | #endif | |
148 | ||
1da177e4 LT |
149 | |
150 | static struct resource smc91x_resources[] = { | |
151 | [0] = { | |
152 | .start = (MST_ETH_PHYS + 0x300), | |
153 | .end = (MST_ETH_PHYS + 0xfffff), | |
154 | .flags = IORESOURCE_MEM, | |
155 | }, | |
156 | [1] = { | |
157 | .start = MAINSTONE_IRQ(3), | |
158 | .end = MAINSTONE_IRQ(3), | |
e7b3dc7e | 159 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, |
1da177e4 LT |
160 | } |
161 | }; | |
162 | ||
163 | static struct platform_device smc91x_device = { | |
164 | .name = "smc91x", | |
165 | .id = 0, | |
166 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
167 | .resource = smc91x_resources, | |
168 | }; | |
169 | ||
f7cbb7fc | 170 | static int mst_audio_startup(struct snd_pcm_substream *substream, void *priv) |
1da177e4 LT |
171 | { |
172 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
173 | MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF; | |
174 | return 0; | |
175 | } | |
176 | ||
f7cbb7fc | 177 | static void mst_audio_shutdown(struct snd_pcm_substream *substream, void *priv) |
1da177e4 LT |
178 | { |
179 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
180 | MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF; | |
181 | } | |
182 | ||
183 | static long mst_audio_suspend_mask; | |
184 | ||
185 | static void mst_audio_suspend(void *priv) | |
186 | { | |
187 | mst_audio_suspend_mask = MST_MSCWR2; | |
188 | MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF; | |
189 | } | |
190 | ||
191 | static void mst_audio_resume(void *priv) | |
192 | { | |
193 | MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF; | |
194 | } | |
195 | ||
196 | static pxa2xx_audio_ops_t mst_audio_ops = { | |
197 | .startup = mst_audio_startup, | |
198 | .shutdown = mst_audio_shutdown, | |
199 | .suspend = mst_audio_suspend, | |
200 | .resume = mst_audio_resume, | |
201 | }; | |
202 | ||
203 | static struct platform_device mst_audio_device = { | |
204 | .name = "pxa2xx-ac97", | |
205 | .id = -1, | |
206 | .dev = { .platform_data = &mst_audio_ops }, | |
207 | }; | |
208 | ||
74ec71e1 TP |
209 | static struct resource flash_resources[] = { |
210 | [0] = { | |
211 | .start = PXA_CS0_PHYS, | |
212 | .end = PXA_CS0_PHYS + SZ_64M - 1, | |
213 | .flags = IORESOURCE_MEM, | |
214 | }, | |
215 | [1] = { | |
216 | .start = PXA_CS1_PHYS, | |
217 | .end = PXA_CS1_PHYS + SZ_64M - 1, | |
218 | .flags = IORESOURCE_MEM, | |
219 | }, | |
220 | }; | |
221 | ||
222 | static struct mtd_partition mainstoneflash0_partitions[] = { | |
223 | { | |
224 | .name = "Bootloader", | |
225 | .size = 0x00040000, | |
226 | .offset = 0, | |
227 | .mask_flags = MTD_WRITEABLE /* force read-only */ | |
228 | },{ | |
229 | .name = "Kernel", | |
230 | .size = 0x00400000, | |
231 | .offset = 0x00040000, | |
232 | },{ | |
233 | .name = "Filesystem", | |
234 | .size = MTDPART_SIZ_FULL, | |
235 | .offset = 0x00440000 | |
236 | } | |
237 | }; | |
238 | ||
239 | static struct flash_platform_data mst_flash_data[2] = { | |
240 | { | |
241 | .map_name = "cfi_probe", | |
242 | .parts = mainstoneflash0_partitions, | |
243 | .nr_parts = ARRAY_SIZE(mainstoneflash0_partitions), | |
244 | }, { | |
245 | .map_name = "cfi_probe", | |
246 | .parts = NULL, | |
247 | .nr_parts = 0, | |
248 | } | |
249 | }; | |
250 | ||
251 | static struct platform_device mst_flash_device[2] = { | |
252 | { | |
253 | .name = "pxa2xx-flash", | |
254 | .id = 0, | |
255 | .dev = { | |
256 | .platform_data = &mst_flash_data[0], | |
257 | }, | |
258 | .resource = &flash_resources[0], | |
259 | .num_resources = 1, | |
260 | }, | |
261 | { | |
262 | .name = "pxa2xx-flash", | |
263 | .id = 1, | |
264 | .dev = { | |
265 | .platform_data = &mst_flash_data[1], | |
266 | }, | |
267 | .resource = &flash_resources[1], | |
268 | .num_resources = 1, | |
269 | }, | |
270 | }; | |
271 | ||
3777f774 RK |
272 | #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE |
273 | static int mainstone_backlight_update_status(struct backlight_device *bl) | |
1da177e4 | 274 | { |
3777f774 RK |
275 | int brightness = bl->props.brightness; |
276 | ||
277 | if (bl->props.power != FB_BLANK_UNBLANK || | |
278 | bl->props.fb_blank != FB_BLANK_UNBLANK) | |
279 | brightness = 0; | |
280 | ||
281 | if (brightness != 0) { | |
1da177e4 | 282 | pxa_gpio_mode(GPIO16_PWM0_MD); |
7053acbd | 283 | pxa_set_cken(CKEN_PWM0, 1); |
3777f774 RK |
284 | } |
285 | PWM_CTRL0 = 0; | |
286 | PWM_PWDUTY0 = brightness; | |
287 | PWM_PERVAL0 = bl->props.max_brightness; | |
288 | if (brightness == 0) | |
7053acbd | 289 | pxa_set_cken(CKEN_PWM0, 0); |
3777f774 RK |
290 | return 0; /* pointless return value */ |
291 | } | |
292 | ||
293 | static int mainstone_backlight_get_brightness(struct backlight_device *bl) | |
294 | { | |
295 | return PWM_PWDUTY0; | |
296 | } | |
297 | ||
298 | static /*const*/ struct backlight_ops mainstone_backlight_ops = { | |
299 | .update_status = mainstone_backlight_update_status, | |
300 | .get_brightness = mainstone_backlight_get_brightness, | |
301 | }; | |
302 | ||
303 | static void __init mainstone_backlight_register(void) | |
304 | { | |
305 | struct backlight_device *bl; | |
306 | ||
307 | bl = backlight_device_register("mainstone-bl", &pxa_device_fb.dev, | |
308 | NULL, &mainstone_backlight_ops); | |
309 | if (IS_ERR(bl)) { | |
310 | printk(KERN_ERR "mainstone: unable to register backlight: %ld\n", | |
311 | PTR_ERR(bl)); | |
312 | return; | |
1da177e4 | 313 | } |
3777f774 RK |
314 | |
315 | /* | |
316 | * broken design - register-then-setup interfaces are | |
317 | * utterly broken by definition. | |
318 | */ | |
319 | bl->props.max_brightness = 1023; | |
320 | bl->props.brightness = 1023; | |
321 | backlight_update_status(bl); | |
1da177e4 | 322 | } |
3777f774 RK |
323 | #else |
324 | #define mainstone_backlight_register() do { } while (0) | |
325 | #endif | |
1da177e4 | 326 | |
d14b272b | 327 | static struct pxafb_mode_info toshiba_ltm04c380k_mode = { |
1da177e4 LT |
328 | .pixclock = 50000, |
329 | .xres = 640, | |
330 | .yres = 480, | |
331 | .bpp = 16, | |
332 | .hsync_len = 1, | |
333 | .left_margin = 0x9f, | |
334 | .right_margin = 1, | |
335 | .vsync_len = 44, | |
336 | .upper_margin = 0, | |
337 | .lower_margin = 0, | |
338 | .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, | |
1da177e4 LT |
339 | }; |
340 | ||
d14b272b | 341 | static struct pxafb_mode_info toshiba_ltm035a776c_mode = { |
1da177e4 LT |
342 | .pixclock = 110000, |
343 | .xres = 240, | |
344 | .yres = 320, | |
345 | .bpp = 16, | |
346 | .hsync_len = 4, | |
347 | .left_margin = 8, | |
348 | .right_margin = 20, | |
349 | .vsync_len = 3, | |
350 | .upper_margin = 1, | |
351 | .lower_margin = 10, | |
352 | .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, | |
d14b272b RP |
353 | }; |
354 | ||
355 | static struct pxafb_mach_info mainstone_pxafb_info = { | |
356 | .num_modes = 1, | |
1da177e4 LT |
357 | .lccr0 = LCCR0_Act, |
358 | .lccr3 = LCCR3_PCP, | |
1da177e4 LT |
359 | }; |
360 | ||
40220c1a | 361 | static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_int, void *data) |
1da177e4 LT |
362 | { |
363 | int err; | |
364 | ||
365 | /* | |
366 | * setup GPIO for PXA27x MMC controller | |
367 | */ | |
368 | pxa_gpio_mode(GPIO32_MMCCLK_MD); | |
369 | pxa_gpio_mode(GPIO112_MMCCMD_MD); | |
370 | pxa_gpio_mode(GPIO92_MMCDAT0_MD); | |
371 | pxa_gpio_mode(GPIO109_MMCDAT1_MD); | |
372 | pxa_gpio_mode(GPIO110_MMCDAT2_MD); | |
373 | pxa_gpio_mode(GPIO111_MMCDAT3_MD); | |
374 | ||
375 | /* make sure SD/Memory Stick multiplexer's signals | |
376 | * are routed to MMC controller | |
377 | */ | |
378 | MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL; | |
379 | ||
52e405ea | 380 | err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED, |
1da177e4 | 381 | "MMC card detect", data); |
2687bd38 | 382 | if (err) |
1da177e4 | 383 | printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); |
1da177e4 | 384 | |
2687bd38 | 385 | return err; |
1da177e4 LT |
386 | } |
387 | ||
388 | static void mainstone_mci_setpower(struct device *dev, unsigned int vdd) | |
389 | { | |
390 | struct pxamci_platform_data* p_d = dev->platform_data; | |
391 | ||
392 | if (( 1 << vdd) & p_d->ocr_mask) { | |
393 | printk(KERN_DEBUG "%s: on\n", __FUNCTION__); | |
394 | MST_MSCWR1 |= MST_MSCWR1_MMC_ON; | |
395 | MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL; | |
396 | } else { | |
397 | printk(KERN_DEBUG "%s: off\n", __FUNCTION__); | |
398 | MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON; | |
399 | } | |
400 | } | |
401 | ||
402 | static void mainstone_mci_exit(struct device *dev, void *data) | |
403 | { | |
404 | free_irq(MAINSTONE_MMC_IRQ, data); | |
405 | } | |
406 | ||
407 | static struct pxamci_platform_data mainstone_mci_platform_data = { | |
408 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | |
409 | .init = mainstone_mci_init, | |
410 | .setpower = mainstone_mci_setpower, | |
411 | .exit = mainstone_mci_exit, | |
412 | }; | |
413 | ||
6f475c01 NP |
414 | static void mainstone_irda_transceiver_mode(struct device *dev, int mode) |
415 | { | |
416 | unsigned long flags; | |
417 | ||
418 | local_irq_save(flags); | |
419 | if (mode & IR_SIRMODE) { | |
420 | MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR; | |
421 | } else if (mode & IR_FIRMODE) { | |
422 | MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR; | |
423 | } | |
424 | if (mode & IR_OFF) { | |
425 | MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF; | |
426 | } else { | |
427 | MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL; | |
428 | } | |
429 | local_irq_restore(flags); | |
430 | } | |
431 | ||
432 | static struct pxaficp_platform_data mainstone_ficp_platform_data = { | |
433 | .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF, | |
434 | .transceiver_mode = mainstone_irda_transceiver_mode, | |
435 | }; | |
436 | ||
74ec71e1 TP |
437 | static struct platform_device *platform_devices[] __initdata = { |
438 | &smc91x_device, | |
439 | &mst_audio_device, | |
440 | &mst_flash_device[0], | |
441 | &mst_flash_device[1], | |
442 | }; | |
443 | ||
81f280e2 RP |
444 | static int mainstone_ohci_init(struct device *dev) |
445 | { | |
446 | /* setup Port1 GPIO pin. */ | |
447 | pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */ | |
448 | pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */ | |
449 | ||
450 | /* Set the Power Control Polarity Low and Power Sense | |
451 | Polarity Low to active low. */ | |
452 | UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & | |
453 | ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE); | |
454 | ||
455 | return 0; | |
456 | } | |
457 | ||
458 | static struct pxaohci_platform_data mainstone_ohci_platform_data = { | |
459 | .port_mode = PMM_PERPORT_MODE, | |
460 | .init = mainstone_ohci_init, | |
461 | }; | |
462 | ||
1da177e4 LT |
463 | static void __init mainstone_init(void) |
464 | { | |
74ec71e1 TP |
465 | int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */ |
466 | ||
467 | mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; | |
468 | mst_flash_data[1].width = 4; | |
469 | ||
470 | /* Compensate for SW7 which swaps the flash banks */ | |
471 | mst_flash_data[SW7].name = "processor-flash"; | |
472 | mst_flash_data[SW7 ^ 1].name = "mainboard-flash"; | |
473 | ||
474 | printk(KERN_NOTICE "Mainstone configured to boot from %s\n", | |
475 | mst_flash_data[0].name); | |
476 | ||
5b2e98cd JH |
477 | /* system bus arbiter setting |
478 | * - Core_Park | |
479 | * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4 | |
480 | */ | |
481 | ARB_CNTRL = ARB_CORE_PARK | 0x234; | |
482 | ||
1da177e4 LT |
483 | /* |
484 | * On Mainstone, we route AC97_SYSCLK via GPIO45 to | |
485 | * the audio daughter card | |
486 | */ | |
487 | pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD); | |
488 | ||
39cbd489 RK |
489 | GPSR(GPIO48_nPOE) = |
490 | GPIO_bit(GPIO48_nPOE) | | |
491 | GPIO_bit(GPIO49_nPWE) | | |
492 | GPIO_bit(GPIO50_nPIOR) | | |
493 | GPIO_bit(GPIO51_nPIOW) | | |
494 | GPIO_bit(GPIO85_nPCE_1) | | |
495 | GPIO_bit(GPIO54_nPCE_2); | |
496 | ||
497 | pxa_gpio_mode(GPIO48_nPOE_MD); | |
498 | pxa_gpio_mode(GPIO49_nPWE_MD); | |
499 | pxa_gpio_mode(GPIO50_nPIOR_MD); | |
500 | pxa_gpio_mode(GPIO51_nPIOW_MD); | |
501 | pxa_gpio_mode(GPIO85_nPCE_1_MD); | |
502 | pxa_gpio_mode(GPIO54_nPCE_2_MD); | |
503 | pxa_gpio_mode(GPIO79_pSKTSEL_MD); | |
504 | pxa_gpio_mode(GPIO55_nPREG_MD); | |
505 | pxa_gpio_mode(GPIO56_nPWAIT_MD); | |
506 | pxa_gpio_mode(GPIO57_nIOIS16_MD); | |
507 | ||
74ec71e1 | 508 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
1da177e4 LT |
509 | |
510 | /* reading Mainstone's "Virtual Configuration Register" | |
511 | might be handy to select LCD type here */ | |
512 | if (0) | |
d14b272b | 513 | mainstone_pxafb_info.modes = &toshiba_ltm04c380k_mode; |
1da177e4 | 514 | else |
d14b272b RP |
515 | mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode; |
516 | ||
517 | set_pxa_fb_info(&mainstone_pxafb_info); | |
3777f774 | 518 | mainstone_backlight_register(); |
1da177e4 LT |
519 | |
520 | pxa_set_mci_info(&mainstone_mci_platform_data); | |
6f475c01 | 521 | pxa_set_ficp_info(&mainstone_ficp_platform_data); |
81f280e2 | 522 | pxa_set_ohci_info(&mainstone_ohci_platform_data); |
1da177e4 LT |
523 | } |
524 | ||
525 | ||
526 | static struct map_desc mainstone_io_desc[] __initdata = { | |
6f9182eb DS |
527 | { /* CPLD */ |
528 | .virtual = MST_FPGA_VIRT, | |
529 | .pfn = __phys_to_pfn(MST_FPGA_PHYS), | |
530 | .length = 0x00100000, | |
531 | .type = MT_DEVICE | |
532 | } | |
1da177e4 LT |
533 | }; |
534 | ||
535 | static void __init mainstone_map_io(void) | |
536 | { | |
537 | pxa_map_io(); | |
538 | iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc)); | |
539 | ||
540 | /* initialize sleep mode regs (wake-up sources, etc) */ | |
541 | PGSR0 = 0x00008800; | |
542 | PGSR1 = 0x00000002; | |
543 | PGSR2 = 0x0001FC00; | |
544 | PGSR3 = 0x00001F81; | |
545 | PWER = 0xC0000002; | |
546 | PRER = 0x00000002; | |
547 | PFER = 0x00000002; | |
8775420d TP |
548 | /* for use I SRAM as framebuffer. */ |
549 | PSLR |= 0xF04; | |
550 | PCFR = 0x66; | |
551 | /* For Keypad wakeup. */ | |
552 | KPC &=~KPC_ASACT; | |
553 | KPC |=KPC_AS; | |
554 | PKWR = 0x000FD000; | |
555 | /* Need read PKWR back after set it. */ | |
556 | PKWR; | |
1da177e4 LT |
557 | } |
558 | ||
559 | MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)") | |
e9dea0c6 | 560 | /* Maintainer: MontaVista Software Inc. */ |
e9dea0c6 | 561 | .phys_io = 0x40000000, |
a7d14f87 | 562 | .boot_params = 0xa0000100, /* BLOB boot parameter setting */ |
68070bde | 563 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, |
e9dea0c6 RK |
564 | .map_io = mainstone_map_io, |
565 | .init_irq = mainstone_init_irq, | |
1da177e4 | 566 | .timer = &pxa_timer, |
e9dea0c6 | 567 | .init_machine = mainstone_init, |
1da177e4 | 568 | MACHINE_END |