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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/pxa27x.c | |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Nov 05, 2002 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * Code specific to PXA27x aka Bulverde. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
2f8163ba | 14 | #include <linux/gpio.h> |
157d2644 | 15 | #include <linux/gpio-pxa.h> |
1da177e4 LT |
16 | #include <linux/module.h> |
17 | #include <linux/kernel.h> | |
18 | #include <linux/init.h> | |
32f17997 | 19 | #include <linux/irqchip.h> |
95d9ffbe | 20 | #include <linux/suspend.h> |
d052d1be | 21 | #include <linux/platform_device.h> |
2eaa03b5 | 22 | #include <linux/syscore_ops.h> |
ad68bb9f | 23 | #include <linux/io.h> |
a3f4c927 | 24 | #include <linux/irq.h> |
b459396e | 25 | #include <linux/i2c/pxa-i2c.h> |
1da177e4 | 26 | |
851982c1 | 27 | #include <asm/mach/map.h> |
a09e64fb | 28 | #include <mach/hardware.h> |
1da177e4 | 29 | #include <asm/irq.h> |
2c74a0ce | 30 | #include <asm/suspend.h> |
a09e64fb | 31 | #include <mach/irqs.h> |
4c25c5d2 | 32 | #include "pxa27x.h" |
afd2fc02 | 33 | #include <mach/reset.h> |
293b2da1 | 34 | #include <linux/platform_data/usb-ohci-pxa27x.h> |
4c25c5d2 | 35 | #include "pm.h" |
a09e64fb | 36 | #include <mach/dma.h> |
ad68bb9f MV |
37 | #include <mach/smemc.h> |
38 | ||
1da177e4 | 39 | #include "generic.h" |
46c41e62 | 40 | #include "devices.h" |
48a17db2 RJ |
41 | #include <linux/clk-provider.h> |
42 | #include <linux/clkdev.h> | |
1da177e4 | 43 | |
0cb0b0d3 EM |
44 | void pxa27x_clear_otgph(void) |
45 | { | |
46 | if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH)) | |
47 | PSSR |= PSSR_OTGPH; | |
48 | } | |
49 | EXPORT_SYMBOL(pxa27x_clear_otgph); | |
50 | ||
fb1bf8cd | 51 | static unsigned long ac97_reset_config[] = { |
3b4bc7bc | 52 | GPIO113_AC97_nRESET_GPIO_HIGH, |
5e16e3cb | 53 | GPIO113_AC97_nRESET, |
3b4bc7bc | 54 | GPIO95_AC97_nRESET_GPIO_HIGH, |
5e16e3cb | 55 | GPIO95_AC97_nRESET, |
fb1bf8cd EM |
56 | }; |
57 | ||
053fe0f1 | 58 | void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio) |
fb1bf8cd | 59 | { |
053fe0f1 MD |
60 | /* |
61 | * This helper function is used to work around a bug in the pxa27x's | |
62 | * ac97 controller during a warm reset. The configuration of the | |
63 | * reset_gpio is changed as follows: | |
64 | * to_gpio == true: configured to generic output gpio and driven high | |
65 | * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET | |
66 | */ | |
67 | ||
fb1bf8cd | 68 | if (reset_gpio == 113) |
053fe0f1 MD |
69 | pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] : |
70 | &ac97_reset_config[1], 1); | |
fb1bf8cd EM |
71 | |
72 | if (reset_gpio == 95) | |
053fe0f1 MD |
73 | pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] : |
74 | &ac97_reset_config[3], 1); | |
fb1bf8cd | 75 | } |
053fe0f1 | 76 | EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset); |
fb1bf8cd | 77 | |
a8fa3f0c NP |
78 | #ifdef CONFIG_PM |
79 | ||
711be5cc EM |
80 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
81 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | |
82 | ||
d082d36e MR |
83 | /* |
84 | * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM | |
85 | */ | |
86 | static unsigned int pwrmode = PWRMODE_SLEEP; | |
87 | ||
54c09889 | 88 | int pxa27x_set_pwrmode(unsigned int mode) |
d082d36e MR |
89 | { |
90 | switch (mode) { | |
91 | case PWRMODE_SLEEP: | |
92 | case PWRMODE_DEEPSLEEP: | |
93 | pwrmode = mode; | |
94 | return 0; | |
95 | } | |
96 | ||
97 | return -EINVAL; | |
98 | } | |
99 | ||
711be5cc EM |
100 | /* |
101 | * List of global PXA peripheral registers to preserve. | |
102 | * More ones like CP and general purpose register values are preserved | |
103 | * with the stack pointer in sleep.S. | |
104 | */ | |
5a3d9651 | 105 | enum { |
711be5cc | 106 | SLEEP_SAVE_PSTR, |
711be5cc | 107 | SLEEP_SAVE_MDREFR, |
5a3d9651 | 108 | SLEEP_SAVE_PCFR, |
649de51b | 109 | SLEEP_SAVE_COUNT |
711be5cc EM |
110 | }; |
111 | ||
112 | void pxa27x_cpu_pm_save(unsigned long *sleep_save) | |
113 | { | |
ad68bb9f | 114 | sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR); |
5a3d9651 | 115 | SAVE(PCFR); |
711be5cc | 116 | |
711be5cc | 117 | SAVE(PSTR); |
711be5cc EM |
118 | } |
119 | ||
120 | void pxa27x_cpu_pm_restore(unsigned long *sleep_save) | |
121 | { | |
ad68bb9f | 122 | __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR); |
5a3d9651 | 123 | RESTORE(PCFR); |
711be5cc EM |
124 | |
125 | PSSR = PSSR_RDH | PSSR_PH; | |
126 | ||
711be5cc EM |
127 | RESTORE(PSTR); |
128 | } | |
129 | ||
130 | void pxa27x_cpu_pm_enter(suspend_state_t state) | |
8775420d TP |
131 | { |
132 | extern void pxa_cpu_standby(void); | |
a9503d21 RK |
133 | #ifndef CONFIG_IWMMXT |
134 | u64 acc0; | |
135 | ||
343c1cdb AB |
136 | asm volatile(".arch_extension xscale\n\t" |
137 | "mra %Q0, %R0, acc0" : "=r" (acc0)); | |
a9503d21 | 138 | #endif |
8775420d | 139 | |
8775420d TP |
140 | /* ensure voltage-change sequencer not initiated, which hangs */ |
141 | PCFR &= ~PCFR_FVC; | |
142 | ||
143 | /* Clear edge-detect status register. */ | |
144 | PEDR = 0xDF12FE1B; | |
145 | ||
dc38e2ad RK |
146 | /* Clear reset status */ |
147 | RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; | |
148 | ||
8775420d | 149 | switch (state) { |
26705ca4 TP |
150 | case PM_SUSPEND_STANDBY: |
151 | pxa_cpu_standby(); | |
152 | break; | |
8775420d | 153 | case PM_SUSPEND_MEM: |
2c74a0ce | 154 | cpu_suspend(pwrmode, pxa27x_finish_suspend); |
a9503d21 | 155 | #ifndef CONFIG_IWMMXT |
343c1cdb AB |
156 | asm volatile(".arch_extension xscale\n\t" |
157 | "mar acc0, %Q0, %R0" : "=r" (acc0)); | |
a9503d21 | 158 | #endif |
8775420d TP |
159 | break; |
160 | } | |
161 | } | |
1da177e4 | 162 | |
711be5cc | 163 | static int pxa27x_cpu_pm_valid(suspend_state_t state) |
88dfe98c RK |
164 | { |
165 | return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; | |
166 | } | |
167 | ||
4104980a RK |
168 | static int pxa27x_cpu_pm_prepare(void) |
169 | { | |
170 | /* set resume return address */ | |
64fc2a94 | 171 | PSPR = __pa_symbol(cpu_resume); |
4104980a RK |
172 | return 0; |
173 | } | |
174 | ||
175 | static void pxa27x_cpu_pm_finish(void) | |
176 | { | |
177 | /* ensure not to come back here if it wasn't intended */ | |
178 | PSPR = 0; | |
179 | } | |
180 | ||
711be5cc | 181 | static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = { |
649de51b | 182 | .save_count = SLEEP_SAVE_COUNT, |
711be5cc EM |
183 | .save = pxa27x_cpu_pm_save, |
184 | .restore = pxa27x_cpu_pm_restore, | |
185 | .valid = pxa27x_cpu_pm_valid, | |
186 | .enter = pxa27x_cpu_pm_enter, | |
4104980a RK |
187 | .prepare = pxa27x_cpu_pm_prepare, |
188 | .finish = pxa27x_cpu_pm_finish, | |
e176bb05 | 189 | }; |
711be5cc EM |
190 | |
191 | static void __init pxa27x_init_pm(void) | |
192 | { | |
193 | pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; | |
194 | } | |
f79299ca | 195 | #else |
196 | static inline void pxa27x_init_pm(void) {} | |
a8fa3f0c NP |
197 | #endif |
198 | ||
c95530c7 | 199 | /* PXA27x: Various gpios can issue wakeup events. This logic only |
200 | * handles the simple cases, not the WEMUX2 and WEMUX3 options | |
201 | */ | |
a3f4c927 | 202 | static int pxa27x_set_wake(struct irq_data *d, unsigned int on) |
c95530c7 | 203 | { |
4929f5a8 | 204 | int gpio = pxa_irq_to_gpio(d->irq); |
c95530c7 | 205 | uint32_t mask; |
206 | ||
c0a596d6 | 207 | if (gpio >= 0 && gpio < 128) |
208 | return gpio_set_wake(gpio, on); | |
c95530c7 | 209 | |
a3f4c927 | 210 | if (d->irq == IRQ_KEYPAD) |
c0a596d6 | 211 | return keypad_set_wake(on); |
c95530c7 | 212 | |
a3f4c927 | 213 | switch (d->irq) { |
c95530c7 | 214 | case IRQ_RTCAlrm: |
215 | mask = PWER_RTC; | |
216 | break; | |
217 | case IRQ_USB: | |
218 | mask = 1u << 26; | |
219 | break; | |
220 | default: | |
221 | return -EINVAL; | |
222 | } | |
223 | ||
c95530c7 | 224 | if (on) |
225 | PWER |= mask; | |
226 | else | |
227 | PWER &=~mask; | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
232 | void __init pxa27x_init_irq(void) | |
233 | { | |
b9e25ace | 234 | pxa_init_irq(34, pxa27x_set_wake); |
c95530c7 | 235 | } |
236 | ||
32f17997 RJ |
237 | static int __init |
238 | pxa27x_dt_init_irq(struct device_node *node, struct device_node *parent) | |
ef6dbda6 | 239 | { |
32f17997 RJ |
240 | pxa_dt_irq_init(pxa27x_set_wake); |
241 | set_handle_irq(ichp_handle_irq); | |
242 | ||
243 | return 0; | |
ef6dbda6 | 244 | } |
32f17997 | 245 | IRQCHIP_DECLARE(pxa27x_intc, "marvell,pxa-intc", pxa27x_dt_init_irq); |
ef6dbda6 | 246 | |
851982c1 MV |
247 | static struct map_desc pxa27x_io_desc[] __initdata = { |
248 | { /* Mem Ctl */ | |
97b09da4 | 249 | .virtual = (unsigned long)SMEMC_VIRT, |
ad68bb9f | 250 | .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), |
0e32986c | 251 | .length = SMEMC_SIZE, |
851982c1 | 252 | .type = MT_DEVICE |
b10f1c83 LP |
253 | }, { /* UNCACHED_PHYS_0 */ |
254 | .virtual = UNCACHED_PHYS_0, | |
255 | .pfn = __phys_to_pfn(0x00000000), | |
256 | .length = UNCACHED_PHYS_0_SIZE, | |
257 | .type = MT_DEVICE | |
851982c1 MV |
258 | }, |
259 | }; | |
260 | ||
261 | void __init pxa27x_map_io(void) | |
262 | { | |
263 | pxa_map_io(); | |
264 | iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc)); | |
265 | pxa27x_get_clk_frequency_khz(1); | |
266 | } | |
267 | ||
1da177e4 LT |
268 | /* |
269 | * device registration specific to PXA27x. | |
270 | */ | |
9ba63c4f | 271 | void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) |
b7a36701 | 272 | { |
bc3a5959 PZ |
273 | local_irq_disable(); |
274 | PCFR |= PCFR_PI2CEN; | |
275 | local_irq_enable(); | |
14758220 | 276 | pxa_register_device(&pxa27x_device_i2c_power, info); |
b7a36701 MR |
277 | } |
278 | ||
b95ace54 | 279 | static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = { |
b8f649f1 HZ |
280 | .irq_base = PXA_GPIO_TO_IRQ(0), |
281 | .gpio_set_wake = gpio_set_wake, | |
b95ace54 RJ |
282 | }; |
283 | ||
1da177e4 | 284 | static struct platform_device *devices[] __initdata = { |
7a857620 | 285 | &pxa27x_device_udc, |
09a5358d | 286 | &pxa_device_pmu, |
e09d02e1 | 287 | &pxa_device_i2s, |
f0fba2ad LG |
288 | &pxa_device_asoc_ssp1, |
289 | &pxa_device_asoc_ssp2, | |
290 | &pxa_device_asoc_ssp3, | |
291 | &pxa_device_asoc_platform, | |
e09d02e1 | 292 | &pxa_device_rtc, |
d8e0db11 | 293 | &pxa27x_device_ssp1, |
294 | &pxa27x_device_ssp2, | |
295 | &pxa27x_device_ssp3, | |
75540c1a | 296 | &pxa27x_device_pwm0, |
297 | &pxa27x_device_pwm1, | |
1da177e4 LT |
298 | }; |
299 | ||
300 | static int __init pxa27x_init(void) | |
301 | { | |
2eaa03b5 | 302 | int ret = 0; |
c0165504 | 303 | |
e176bb05 | 304 | if (cpu_is_pxa27x()) { |
04fef228 EM |
305 | |
306 | reset_status = RCSR; | |
307 | ||
711be5cc | 308 | pxa27x_init_pm(); |
f79299ca | 309 | |
2eaa03b5 RW |
310 | register_syscore_ops(&pxa_irq_syscore_ops); |
311 | register_syscore_ops(&pxa2xx_mfp_syscore_ops); | |
c0165504 | 312 | |
24e32a55 RJ |
313 | if (!of_have_populated_dt()) { |
314 | pxa_register_device(&pxa27x_device_gpio, | |
315 | &pxa27x_gpio_info); | |
72b195cb | 316 | pxa2xx_set_dmac_info(32, 75); |
24e32a55 RJ |
317 | ret = platform_add_devices(devices, |
318 | ARRAY_SIZE(devices)); | |
319 | } | |
e176bb05 | 320 | } |
c0165504 | 321 | |
e176bb05 | 322 | return ret; |
1da177e4 LT |
323 | } |
324 | ||
1c104e0e | 325 | postcore_initcall(pxa27x_init); |