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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/pxa27x.c | |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Nov 05, 2002 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * Code specific to PXA27x aka Bulverde. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
95d9ffbe | 17 | #include <linux/suspend.h> |
d052d1be | 18 | #include <linux/platform_device.h> |
c0165504 | 19 | #include <linux/sysdev.h> |
1da177e4 | 20 | |
be509729 | 21 | #include <asm/arch/hardware.h> |
1da177e4 | 22 | #include <asm/irq.h> |
cd49104d | 23 | #include <asm/arch/irqs.h> |
1da177e4 | 24 | #include <asm/arch/pxa-regs.h> |
8785a8fb | 25 | #include <asm/arch/pxa2xx-regs.h> |
c0a596d6 | 26 | #include <asm/arch/mfp-pxa27x.h> |
81f280e2 | 27 | #include <asm/arch/ohci.h> |
e176bb05 | 28 | #include <asm/arch/pm.h> |
f53f066c | 29 | #include <asm/arch/dma.h> |
b7a36701 | 30 | #include <asm/arch/i2c.h> |
1da177e4 LT |
31 | |
32 | #include "generic.h" | |
46c41e62 | 33 | #include "devices.h" |
a6dba20c | 34 | #include "clock.h" |
1da177e4 LT |
35 | |
36 | /* Crystal clock: 13MHz */ | |
37 | #define BASE_CLK 13000000 | |
38 | ||
39 | /* | |
40 | * Get the clock frequency as reflected by CCSR and the turbo flag. | |
41 | * We assume these values have been applied via a fcs. | |
42 | * If info is not 0 we also display the current settings. | |
43 | */ | |
15a40333 | 44 | unsigned int pxa27x_get_clk_frequency_khz(int info) |
1da177e4 LT |
45 | { |
46 | unsigned long ccsr, clkcfg; | |
47 | unsigned int l, L, m, M, n2, N, S; | |
48 | int cccr_a, t, ht, b; | |
49 | ||
50 | ccsr = CCSR; | |
51 | cccr_a = CCCR & (1 << 25); | |
52 | ||
53 | /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ | |
54 | asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); | |
afe5df20 | 55 | t = clkcfg & (1 << 0); |
1da177e4 LT |
56 | ht = clkcfg & (1 << 2); |
57 | b = clkcfg & (1 << 3); | |
58 | ||
59 | l = ccsr & 0x1f; | |
60 | n2 = (ccsr>>7) & 0xf; | |
61 | m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; | |
62 | ||
63 | L = l * BASE_CLK; | |
64 | N = (L * n2) / 2; | |
65 | M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); | |
66 | S = (b) ? L : (L/2); | |
67 | ||
68 | if (info) { | |
69 | printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", | |
70 | L / 1000000, (L % 1000000) / 10000, l ); | |
71 | printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", | |
72 | N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5, | |
73 | (t) ? "" : "in" ); | |
74 | printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n", | |
75 | M / 1000000, (M % 1000000) / 10000, m ); | |
76 | printk( KERN_INFO "System bus clock: %d.%02dMHz \n", | |
77 | S / 1000000, (S % 1000000) / 10000 ); | |
78 | } | |
79 | ||
80 | return (t) ? (N/1000) : (L/1000); | |
81 | } | |
82 | ||
83 | /* | |
84 | * Return the current mem clock frequency in units of 10kHz as | |
85 | * reflected by CCCR[A], B, and L | |
86 | */ | |
15a40333 | 87 | unsigned int pxa27x_get_memclk_frequency_10khz(void) |
1da177e4 LT |
88 | { |
89 | unsigned long ccsr, clkcfg; | |
90 | unsigned int l, L, m, M; | |
91 | int cccr_a, b; | |
92 | ||
93 | ccsr = CCSR; | |
94 | cccr_a = CCCR & (1 << 25); | |
95 | ||
96 | /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ | |
97 | asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); | |
98 | b = clkcfg & (1 << 3); | |
99 | ||
100 | l = ccsr & 0x1f; | |
101 | m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; | |
102 | ||
103 | L = l * BASE_CLK; | |
104 | M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); | |
105 | ||
106 | return (M / 10000); | |
107 | } | |
108 | ||
109 | /* | |
110 | * Return the current LCD clock frequency in units of 10kHz as | |
111 | */ | |
a88a447d | 112 | static unsigned int pxa27x_get_lcdclk_frequency_10khz(void) |
1da177e4 LT |
113 | { |
114 | unsigned long ccsr; | |
115 | unsigned int l, L, k, K; | |
116 | ||
117 | ccsr = CCSR; | |
118 | ||
119 | l = ccsr & 0x1f; | |
120 | k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4; | |
121 | ||
122 | L = l * BASE_CLK; | |
123 | K = L / k; | |
124 | ||
125 | return (K / 10000); | |
126 | } | |
127 | ||
a6dba20c RK |
128 | static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk) |
129 | { | |
130 | return pxa27x_get_lcdclk_frequency_10khz() * 10000; | |
131 | } | |
132 | ||
133 | static const struct clkops clk_pxa27x_lcd_ops = { | |
134 | .enable = clk_cken_enable, | |
135 | .disable = clk_cken_disable, | |
136 | .getrate = clk_pxa27x_lcd_getrate, | |
137 | }; | |
138 | ||
139 | static struct clk pxa27x_clks[] = { | |
140 | INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev), | |
141 | INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL), | |
142 | ||
a6dba20c RK |
143 | INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), |
144 | INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), | |
435b6e94 | 145 | INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL), |
a6dba20c RK |
146 | |
147 | INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev), | |
148 | INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), | |
7a857620 | 149 | INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa27x_device_udc.dev), |
a6dba20c RK |
150 | INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev), |
151 | INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev), | |
152 | ||
8854cb49 | 153 | INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev), |
a6dba20c | 154 | INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), |
37320980 | 155 | INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), |
a6dba20c | 156 | |
d8e0db11 | 157 | INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), |
158 | INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), | |
159 | INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), | |
75540c1a | 160 | INIT_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev), |
161 | INIT_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev), | |
d8e0db11 | 162 | |
27b98a67 MB |
163 | INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), |
164 | INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL), | |
165 | ||
a6dba20c | 166 | /* |
a6dba20c RK |
167 | INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), |
168 | INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL), | |
169 | INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL), | |
170 | INIT_CKEN("IMCLK", IM, 0, 0, NULL), | |
171 | INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL), | |
172 | */ | |
173 | }; | |
174 | ||
a8fa3f0c NP |
175 | #ifdef CONFIG_PM |
176 | ||
711be5cc EM |
177 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
178 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | |
179 | ||
711be5cc EM |
180 | /* |
181 | * List of global PXA peripheral registers to preserve. | |
182 | * More ones like CP and general purpose register values are preserved | |
183 | * with the stack pointer in sleep.S. | |
184 | */ | |
649de51b | 185 | enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3, |
711be5cc EM |
186 | |
187 | SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, | |
188 | SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, | |
189 | SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, | |
190 | SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U, | |
191 | ||
192 | SLEEP_SAVE_PSTR, | |
193 | ||
711be5cc EM |
194 | SLEEP_SAVE_CKEN, |
195 | ||
196 | SLEEP_SAVE_MDREFR, | |
197 | SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER, | |
198 | SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR, | |
199 | ||
649de51b | 200 | SLEEP_SAVE_COUNT |
711be5cc EM |
201 | }; |
202 | ||
203 | void pxa27x_cpu_pm_save(unsigned long *sleep_save) | |
204 | { | |
711be5cc EM |
205 | SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3); |
206 | ||
207 | SAVE(GAFR0_L); SAVE(GAFR0_U); | |
208 | SAVE(GAFR1_L); SAVE(GAFR1_U); | |
209 | SAVE(GAFR2_L); SAVE(GAFR2_U); | |
210 | SAVE(GAFR3_L); SAVE(GAFR3_U); | |
211 | ||
212 | SAVE(MDREFR); | |
213 | SAVE(PWER); SAVE(PCFR); SAVE(PRER); | |
214 | SAVE(PFER); SAVE(PKWR); | |
215 | ||
711be5cc EM |
216 | SAVE(CKEN); |
217 | SAVE(PSTR); | |
711be5cc EM |
218 | } |
219 | ||
220 | void pxa27x_cpu_pm_restore(unsigned long *sleep_save) | |
221 | { | |
222 | /* ensure not to come back here if it wasn't intended */ | |
223 | PSPR = 0; | |
224 | ||
225 | /* restore registers */ | |
711be5cc EM |
226 | RESTORE(GAFR0_L); RESTORE(GAFR0_U); |
227 | RESTORE(GAFR1_L); RESTORE(GAFR1_U); | |
228 | RESTORE(GAFR2_L); RESTORE(GAFR2_U); | |
229 | RESTORE(GAFR3_L); RESTORE(GAFR3_U); | |
711be5cc EM |
230 | RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3); |
231 | ||
232 | RESTORE(MDREFR); | |
233 | RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER); | |
234 | RESTORE(PFER); RESTORE(PKWR); | |
235 | ||
236 | PSSR = PSSR_RDH | PSSR_PH; | |
237 | ||
238 | RESTORE(CKEN); | |
239 | ||
711be5cc EM |
240 | RESTORE(PSTR); |
241 | } | |
242 | ||
243 | void pxa27x_cpu_pm_enter(suspend_state_t state) | |
8775420d TP |
244 | { |
245 | extern void pxa_cpu_standby(void); | |
8775420d | 246 | |
8775420d TP |
247 | /* ensure voltage-change sequencer not initiated, which hangs */ |
248 | PCFR &= ~PCFR_FVC; | |
249 | ||
250 | /* Clear edge-detect status register. */ | |
251 | PEDR = 0xDF12FE1B; | |
252 | ||
dc38e2ad RK |
253 | /* Clear reset status */ |
254 | RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; | |
255 | ||
8775420d | 256 | switch (state) { |
26705ca4 TP |
257 | case PM_SUSPEND_STANDBY: |
258 | pxa_cpu_standby(); | |
259 | break; | |
8775420d TP |
260 | case PM_SUSPEND_MEM: |
261 | /* set resume return address */ | |
262 | PSPR = virt_to_phys(pxa_cpu_resume); | |
b750a093 | 263 | pxa27x_cpu_suspend(PWRMODE_SLEEP); |
8775420d TP |
264 | break; |
265 | } | |
266 | } | |
1da177e4 | 267 | |
711be5cc | 268 | static int pxa27x_cpu_pm_valid(suspend_state_t state) |
88dfe98c RK |
269 | { |
270 | return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; | |
271 | } | |
272 | ||
711be5cc | 273 | static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = { |
649de51b | 274 | .save_count = SLEEP_SAVE_COUNT, |
711be5cc EM |
275 | .save = pxa27x_cpu_pm_save, |
276 | .restore = pxa27x_cpu_pm_restore, | |
277 | .valid = pxa27x_cpu_pm_valid, | |
278 | .enter = pxa27x_cpu_pm_enter, | |
e176bb05 | 279 | }; |
711be5cc EM |
280 | |
281 | static void __init pxa27x_init_pm(void) | |
282 | { | |
283 | pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; | |
284 | } | |
f79299ca | 285 | #else |
286 | static inline void pxa27x_init_pm(void) {} | |
a8fa3f0c NP |
287 | #endif |
288 | ||
c95530c7 | 289 | /* PXA27x: Various gpios can issue wakeup events. This logic only |
290 | * handles the simple cases, not the WEMUX2 and WEMUX3 options | |
291 | */ | |
c95530c7 | 292 | static int pxa27x_set_wake(unsigned int irq, unsigned int on) |
293 | { | |
294 | int gpio = IRQ_TO_GPIO(irq); | |
295 | uint32_t mask; | |
296 | ||
c0a596d6 | 297 | if (gpio >= 0 && gpio < 128) |
298 | return gpio_set_wake(gpio, on); | |
c95530c7 | 299 | |
c0a596d6 | 300 | if (irq == IRQ_KEYPAD) |
301 | return keypad_set_wake(on); | |
c95530c7 | 302 | |
303 | switch (irq) { | |
304 | case IRQ_RTCAlrm: | |
305 | mask = PWER_RTC; | |
306 | break; | |
307 | case IRQ_USB: | |
308 | mask = 1u << 26; | |
309 | break; | |
310 | default: | |
311 | return -EINVAL; | |
312 | } | |
313 | ||
c95530c7 | 314 | if (on) |
315 | PWER |= mask; | |
316 | else | |
317 | PWER &=~mask; | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
322 | void __init pxa27x_init_irq(void) | |
323 | { | |
b9e25ace | 324 | pxa_init_irq(34, pxa27x_set_wake); |
325 | pxa_init_gpio(128, pxa27x_set_wake); | |
c95530c7 | 326 | } |
327 | ||
1da177e4 LT |
328 | /* |
329 | * device registration specific to PXA27x. | |
330 | */ | |
331 | ||
34f3231f RK |
332 | static struct resource i2c_power_resources[] = { |
333 | { | |
334 | .start = 0x40f00180, | |
335 | .end = 0x40f001a3, | |
336 | .flags = IORESOURCE_MEM, | |
337 | }, { | |
338 | .start = IRQ_PWRI2C, | |
339 | .end = IRQ_PWRI2C, | |
340 | .flags = IORESOURCE_IRQ, | |
341 | }, | |
342 | }; | |
343 | ||
00dc4f94 | 344 | struct platform_device pxa27x_device_i2c_power = { |
34f3231f RK |
345 | .name = "pxa2xx-i2c", |
346 | .id = 1, | |
347 | .resource = i2c_power_resources, | |
348 | .num_resources = ARRAY_SIZE(i2c_power_resources), | |
349 | }; | |
350 | ||
b7a36701 MR |
351 | void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info) |
352 | { | |
bc3a5959 PZ |
353 | local_irq_disable(); |
354 | PCFR |= PCFR_PI2CEN; | |
355 | local_irq_enable(); | |
b7a36701 MR |
356 | pxa27x_device_i2c_power.dev.platform_data = info; |
357 | } | |
358 | ||
1da177e4 | 359 | static struct platform_device *devices[] __initdata = { |
7a857620 | 360 | &pxa27x_device_udc, |
e09d02e1 EM |
361 | &pxa_device_ffuart, |
362 | &pxa_device_btuart, | |
363 | &pxa_device_stuart, | |
e09d02e1 | 364 | &pxa_device_i2s, |
e09d02e1 EM |
365 | &pxa_device_rtc, |
366 | &pxa27x_device_i2c_power, | |
d8e0db11 | 367 | &pxa27x_device_ssp1, |
368 | &pxa27x_device_ssp2, | |
369 | &pxa27x_device_ssp3, | |
75540c1a | 370 | &pxa27x_device_pwm0, |
371 | &pxa27x_device_pwm1, | |
1da177e4 LT |
372 | }; |
373 | ||
c0165504 | 374 | static struct sys_device pxa27x_sysdev[] = { |
375 | { | |
c0165504 | 376 | .cls = &pxa_irq_sysclass, |
16dfdbf0 | 377 | }, { |
378 | .cls = &pxa_gpio_sysclass, | |
c0165504 | 379 | }, |
380 | }; | |
381 | ||
1da177e4 LT |
382 | static int __init pxa27x_init(void) |
383 | { | |
c0165504 | 384 | int i, ret = 0; |
385 | ||
e176bb05 | 386 | if (cpu_is_pxa27x()) { |
a6dba20c RK |
387 | clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); |
388 | ||
f53f066c EM |
389 | if ((ret = pxa_init_dma(32))) |
390 | return ret; | |
f79299ca | 391 | |
711be5cc | 392 | pxa27x_init_pm(); |
f79299ca | 393 | |
c0165504 | 394 | for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) { |
395 | ret = sysdev_register(&pxa27x_sysdev[i]); | |
396 | if (ret) | |
397 | pr_err("failed to register sysdev[%d]\n", i); | |
398 | } | |
399 | ||
e176bb05 RK |
400 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); |
401 | } | |
c0165504 | 402 | |
e176bb05 | 403 | return ret; |
1da177e4 LT |
404 | } |
405 | ||
1c104e0e | 406 | postcore_initcall(pxa27x_init); |