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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/pxa27x.c | |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Nov 05, 2002 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * Code specific to PXA27x aka Bulverde. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
95d9ffbe | 17 | #include <linux/suspend.h> |
d052d1be | 18 | #include <linux/platform_device.h> |
2eaa03b5 | 19 | #include <linux/syscore_ops.h> |
ad68bb9f | 20 | #include <linux/io.h> |
a3f4c927 | 21 | #include <linux/irq.h> |
b459396e | 22 | #include <linux/i2c/pxa-i2c.h> |
1da177e4 | 23 | |
851982c1 | 24 | #include <asm/mach/map.h> |
a09e64fb | 25 | #include <mach/hardware.h> |
1da177e4 | 26 | #include <asm/irq.h> |
2c74a0ce | 27 | #include <asm/suspend.h> |
a09e64fb | 28 | #include <mach/irqs.h> |
a58fbcd8 | 29 | #include <mach/gpio.h> |
51c62982 | 30 | #include <mach/pxa27x.h> |
afd2fc02 | 31 | #include <mach/reset.h> |
a09e64fb RK |
32 | #include <mach/ohci.h> |
33 | #include <mach/pm.h> | |
34 | #include <mach/dma.h> | |
ad68bb9f MV |
35 | #include <mach/smemc.h> |
36 | ||
1da177e4 | 37 | #include "generic.h" |
46c41e62 | 38 | #include "devices.h" |
a6dba20c | 39 | #include "clock.h" |
1da177e4 | 40 | |
0cb0b0d3 EM |
41 | void pxa27x_clear_otgph(void) |
42 | { | |
43 | if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH)) | |
44 | PSSR |= PSSR_OTGPH; | |
45 | } | |
46 | EXPORT_SYMBOL(pxa27x_clear_otgph); | |
47 | ||
fb1bf8cd | 48 | static unsigned long ac97_reset_config[] = { |
fb1bf8cd | 49 | GPIO113_GPIO, |
5e16e3cb EM |
50 | GPIO113_AC97_nRESET, |
51 | GPIO95_GPIO, | |
52 | GPIO95_AC97_nRESET, | |
fb1bf8cd EM |
53 | }; |
54 | ||
55 | void pxa27x_assert_ac97reset(int reset_gpio, int on) | |
56 | { | |
57 | if (reset_gpio == 113) | |
58 | pxa2xx_mfp_config(on ? &ac97_reset_config[0] : | |
59 | &ac97_reset_config[1], 1); | |
60 | ||
61 | if (reset_gpio == 95) | |
62 | pxa2xx_mfp_config(on ? &ac97_reset_config[2] : | |
63 | &ac97_reset_config[3], 1); | |
64 | } | |
65 | EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset); | |
66 | ||
1da177e4 LT |
67 | /* Crystal clock: 13MHz */ |
68 | #define BASE_CLK 13000000 | |
69 | ||
70 | /* | |
71 | * Get the clock frequency as reflected by CCSR and the turbo flag. | |
72 | * We assume these values have been applied via a fcs. | |
73 | * If info is not 0 we also display the current settings. | |
74 | */ | |
15a40333 | 75 | unsigned int pxa27x_get_clk_frequency_khz(int info) |
1da177e4 LT |
76 | { |
77 | unsigned long ccsr, clkcfg; | |
78 | unsigned int l, L, m, M, n2, N, S; | |
79 | int cccr_a, t, ht, b; | |
80 | ||
81 | ccsr = CCSR; | |
82 | cccr_a = CCCR & (1 << 25); | |
83 | ||
84 | /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ | |
85 | asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); | |
afe5df20 | 86 | t = clkcfg & (1 << 0); |
1da177e4 LT |
87 | ht = clkcfg & (1 << 2); |
88 | b = clkcfg & (1 << 3); | |
89 | ||
90 | l = ccsr & 0x1f; | |
91 | n2 = (ccsr>>7) & 0xf; | |
92 | m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; | |
93 | ||
94 | L = l * BASE_CLK; | |
95 | N = (L * n2) / 2; | |
96 | M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); | |
97 | S = (b) ? L : (L/2); | |
98 | ||
99 | if (info) { | |
100 | printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", | |
101 | L / 1000000, (L % 1000000) / 10000, l ); | |
102 | printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", | |
103 | N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5, | |
104 | (t) ? "" : "in" ); | |
105 | printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n", | |
106 | M / 1000000, (M % 1000000) / 10000, m ); | |
107 | printk( KERN_INFO "System bus clock: %d.%02dMHz \n", | |
108 | S / 1000000, (S % 1000000) / 10000 ); | |
109 | } | |
110 | ||
111 | return (t) ? (N/1000) : (L/1000); | |
112 | } | |
113 | ||
114 | /* | |
2a125dd5 | 115 | * Return the current mem clock frequency as reflected by CCCR[A], B, and L |
1da177e4 | 116 | */ |
2a125dd5 | 117 | static unsigned long clk_pxa27x_mem_getrate(struct clk *clk) |
1da177e4 LT |
118 | { |
119 | unsigned long ccsr, clkcfg; | |
120 | unsigned int l, L, m, M; | |
121 | int cccr_a, b; | |
122 | ||
123 | ccsr = CCSR; | |
124 | cccr_a = CCCR & (1 << 25); | |
125 | ||
126 | /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ | |
127 | asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); | |
128 | b = clkcfg & (1 << 3); | |
129 | ||
130 | l = ccsr & 0x1f; | |
131 | m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; | |
132 | ||
133 | L = l * BASE_CLK; | |
134 | M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); | |
135 | ||
2a125dd5 | 136 | return M; |
1da177e4 LT |
137 | } |
138 | ||
2a125dd5 EM |
139 | static const struct clkops clk_pxa27x_mem_ops = { |
140 | .enable = clk_dummy_enable, | |
141 | .disable = clk_dummy_disable, | |
142 | .getrate = clk_pxa27x_mem_getrate, | |
143 | }; | |
144 | ||
1da177e4 LT |
145 | /* |
146 | * Return the current LCD clock frequency in units of 10kHz as | |
147 | */ | |
a88a447d | 148 | static unsigned int pxa27x_get_lcdclk_frequency_10khz(void) |
1da177e4 LT |
149 | { |
150 | unsigned long ccsr; | |
151 | unsigned int l, L, k, K; | |
152 | ||
153 | ccsr = CCSR; | |
154 | ||
155 | l = ccsr & 0x1f; | |
156 | k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4; | |
157 | ||
158 | L = l * BASE_CLK; | |
159 | K = L / k; | |
160 | ||
161 | return (K / 10000); | |
162 | } | |
163 | ||
a6dba20c RK |
164 | static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk) |
165 | { | |
166 | return pxa27x_get_lcdclk_frequency_10khz() * 10000; | |
167 | } | |
168 | ||
169 | static const struct clkops clk_pxa27x_lcd_ops = { | |
4029813c EM |
170 | .enable = clk_pxa2xx_cken_enable, |
171 | .disable = clk_pxa2xx_cken_disable, | |
a6dba20c RK |
172 | .getrate = clk_pxa27x_lcd_getrate, |
173 | }; | |
174 | ||
4029813c EM |
175 | static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1); |
176 | static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1); | |
177 | static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1); | |
178 | static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0); | |
179 | static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0); | |
180 | static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5); | |
181 | static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0); | |
182 | static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0); | |
183 | static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0); | |
184 | static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0); | |
185 | static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0); | |
186 | static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0); | |
187 | static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0); | |
188 | static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0); | |
189 | static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0); | |
190 | static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0); | |
191 | static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0); | |
192 | static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0); | |
193 | static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0); | |
194 | static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0); | |
195 | static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0); | |
196 | static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0); | |
197 | static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0); | |
198 | ||
8c3abc7d RK |
199 | static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops); |
200 | static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops); | |
2a125dd5 | 201 | static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0); |
8c3abc7d RK |
202 | |
203 | static struct clk_lookup pxa27x_clkregs[] = { | |
204 | INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL), | |
205 | INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL), | |
206 | INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL), | |
207 | INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL), | |
208 | INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL), | |
209 | INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL), | |
210 | INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL), | |
211 | INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL), | |
212 | INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL), | |
213 | INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"), | |
214 | INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"), | |
215 | INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL), | |
216 | INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL), | |
217 | INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL), | |
218 | INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL), | |
219 | INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL), | |
220 | INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL), | |
221 | INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL), | |
222 | INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL), | |
223 | INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"), | |
224 | INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"), | |
225 | INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"), | |
226 | INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"), | |
227 | INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"), | |
228 | INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), | |
229 | INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), | |
2a125dd5 | 230 | INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL), |
a6dba20c RK |
231 | }; |
232 | ||
a8fa3f0c NP |
233 | #ifdef CONFIG_PM |
234 | ||
711be5cc EM |
235 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
236 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | |
237 | ||
d082d36e MR |
238 | /* |
239 | * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM | |
240 | */ | |
241 | static unsigned int pwrmode = PWRMODE_SLEEP; | |
242 | ||
243 | int __init pxa27x_set_pwrmode(unsigned int mode) | |
244 | { | |
245 | switch (mode) { | |
246 | case PWRMODE_SLEEP: | |
247 | case PWRMODE_DEEPSLEEP: | |
248 | pwrmode = mode; | |
249 | return 0; | |
250 | } | |
251 | ||
252 | return -EINVAL; | |
253 | } | |
254 | ||
711be5cc EM |
255 | /* |
256 | * List of global PXA peripheral registers to preserve. | |
257 | * More ones like CP and general purpose register values are preserved | |
258 | * with the stack pointer in sleep.S. | |
259 | */ | |
5a3d9651 | 260 | enum { |
711be5cc | 261 | SLEEP_SAVE_PSTR, |
711be5cc | 262 | SLEEP_SAVE_MDREFR, |
5a3d9651 | 263 | SLEEP_SAVE_PCFR, |
649de51b | 264 | SLEEP_SAVE_COUNT |
711be5cc EM |
265 | }; |
266 | ||
267 | void pxa27x_cpu_pm_save(unsigned long *sleep_save) | |
268 | { | |
ad68bb9f | 269 | sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR); |
5a3d9651 | 270 | SAVE(PCFR); |
711be5cc | 271 | |
711be5cc | 272 | SAVE(PSTR); |
711be5cc EM |
273 | } |
274 | ||
275 | void pxa27x_cpu_pm_restore(unsigned long *sleep_save) | |
276 | { | |
ad68bb9f | 277 | __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR); |
5a3d9651 | 278 | RESTORE(PCFR); |
711be5cc EM |
279 | |
280 | PSSR = PSSR_RDH | PSSR_PH; | |
281 | ||
711be5cc EM |
282 | RESTORE(PSTR); |
283 | } | |
284 | ||
285 | void pxa27x_cpu_pm_enter(suspend_state_t state) | |
8775420d TP |
286 | { |
287 | extern void pxa_cpu_standby(void); | |
a9503d21 RK |
288 | #ifndef CONFIG_IWMMXT |
289 | u64 acc0; | |
290 | ||
291 | asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0)); | |
292 | #endif | |
8775420d | 293 | |
8775420d TP |
294 | /* ensure voltage-change sequencer not initiated, which hangs */ |
295 | PCFR &= ~PCFR_FVC; | |
296 | ||
297 | /* Clear edge-detect status register. */ | |
298 | PEDR = 0xDF12FE1B; | |
299 | ||
dc38e2ad RK |
300 | /* Clear reset status */ |
301 | RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; | |
302 | ||
8775420d | 303 | switch (state) { |
26705ca4 TP |
304 | case PM_SUSPEND_STANDBY: |
305 | pxa_cpu_standby(); | |
306 | break; | |
8775420d | 307 | case PM_SUSPEND_MEM: |
2c74a0ce | 308 | cpu_suspend(pwrmode, pxa27x_finish_suspend); |
a9503d21 RK |
309 | #ifndef CONFIG_IWMMXT |
310 | asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0)); | |
311 | #endif | |
8775420d TP |
312 | break; |
313 | } | |
314 | } | |
1da177e4 | 315 | |
711be5cc | 316 | static int pxa27x_cpu_pm_valid(suspend_state_t state) |
88dfe98c RK |
317 | { |
318 | return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; | |
319 | } | |
320 | ||
4104980a RK |
321 | static int pxa27x_cpu_pm_prepare(void) |
322 | { | |
323 | /* set resume return address */ | |
4f5ad99b | 324 | PSPR = virt_to_phys(cpu_resume); |
4104980a RK |
325 | return 0; |
326 | } | |
327 | ||
328 | static void pxa27x_cpu_pm_finish(void) | |
329 | { | |
330 | /* ensure not to come back here if it wasn't intended */ | |
331 | PSPR = 0; | |
332 | } | |
333 | ||
711be5cc | 334 | static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = { |
649de51b | 335 | .save_count = SLEEP_SAVE_COUNT, |
711be5cc EM |
336 | .save = pxa27x_cpu_pm_save, |
337 | .restore = pxa27x_cpu_pm_restore, | |
338 | .valid = pxa27x_cpu_pm_valid, | |
339 | .enter = pxa27x_cpu_pm_enter, | |
4104980a RK |
340 | .prepare = pxa27x_cpu_pm_prepare, |
341 | .finish = pxa27x_cpu_pm_finish, | |
e176bb05 | 342 | }; |
711be5cc EM |
343 | |
344 | static void __init pxa27x_init_pm(void) | |
345 | { | |
346 | pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; | |
347 | } | |
f79299ca | 348 | #else |
349 | static inline void pxa27x_init_pm(void) {} | |
a8fa3f0c NP |
350 | #endif |
351 | ||
c95530c7 | 352 | /* PXA27x: Various gpios can issue wakeup events. This logic only |
353 | * handles the simple cases, not the WEMUX2 and WEMUX3 options | |
354 | */ | |
a3f4c927 | 355 | static int pxa27x_set_wake(struct irq_data *d, unsigned int on) |
c95530c7 | 356 | { |
7db6a7fa | 357 | int gpio = irq_to_gpio(d->irq); |
c95530c7 | 358 | uint32_t mask; |
359 | ||
c0a596d6 | 360 | if (gpio >= 0 && gpio < 128) |
361 | return gpio_set_wake(gpio, on); | |
c95530c7 | 362 | |
a3f4c927 | 363 | if (d->irq == IRQ_KEYPAD) |
c0a596d6 | 364 | return keypad_set_wake(on); |
c95530c7 | 365 | |
a3f4c927 | 366 | switch (d->irq) { |
c95530c7 | 367 | case IRQ_RTCAlrm: |
368 | mask = PWER_RTC; | |
369 | break; | |
370 | case IRQ_USB: | |
371 | mask = 1u << 26; | |
372 | break; | |
373 | default: | |
374 | return -EINVAL; | |
375 | } | |
376 | ||
c95530c7 | 377 | if (on) |
378 | PWER |= mask; | |
379 | else | |
380 | PWER &=~mask; | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
385 | void __init pxa27x_init_irq(void) | |
386 | { | |
b9e25ace | 387 | pxa_init_irq(34, pxa27x_set_wake); |
a58fbcd8 | 388 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake); |
c95530c7 | 389 | } |
390 | ||
851982c1 MV |
391 | static struct map_desc pxa27x_io_desc[] __initdata = { |
392 | { /* Mem Ctl */ | |
ad68bb9f MV |
393 | .virtual = SMEMC_VIRT, |
394 | .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), | |
851982c1 MV |
395 | .length = 0x00200000, |
396 | .type = MT_DEVICE | |
397 | }, { /* IMem ctl */ | |
398 | .virtual = 0xfe000000, | |
399 | .pfn = __phys_to_pfn(0x58000000), | |
400 | .length = 0x00100000, | |
401 | .type = MT_DEVICE | |
402 | }, | |
403 | }; | |
404 | ||
405 | void __init pxa27x_map_io(void) | |
406 | { | |
407 | pxa_map_io(); | |
408 | iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc)); | |
409 | pxa27x_get_clk_frequency_khz(1); | |
410 | } | |
411 | ||
1da177e4 LT |
412 | /* |
413 | * device registration specific to PXA27x. | |
414 | */ | |
9ba63c4f | 415 | void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) |
b7a36701 | 416 | { |
bc3a5959 PZ |
417 | local_irq_disable(); |
418 | PCFR |= PCFR_PI2CEN; | |
419 | local_irq_enable(); | |
14758220 | 420 | pxa_register_device(&pxa27x_device_i2c_power, info); |
b7a36701 MR |
421 | } |
422 | ||
1da177e4 | 423 | static struct platform_device *devices[] __initdata = { |
7a857620 | 424 | &pxa27x_device_udc, |
09a5358d | 425 | &pxa_device_pmu, |
e09d02e1 | 426 | &pxa_device_i2s, |
f0fba2ad LG |
427 | &pxa_device_asoc_ssp1, |
428 | &pxa_device_asoc_ssp2, | |
429 | &pxa_device_asoc_ssp3, | |
430 | &pxa_device_asoc_platform, | |
72493146 | 431 | &sa1100_device_rtc, |
e09d02e1 | 432 | &pxa_device_rtc, |
d8e0db11 | 433 | &pxa27x_device_ssp1, |
434 | &pxa27x_device_ssp2, | |
435 | &pxa27x_device_ssp3, | |
75540c1a | 436 | &pxa27x_device_pwm0, |
437 | &pxa27x_device_pwm1, | |
1da177e4 LT |
438 | }; |
439 | ||
440 | static int __init pxa27x_init(void) | |
441 | { | |
2eaa03b5 | 442 | int ret = 0; |
c0165504 | 443 | |
e176bb05 | 444 | if (cpu_is_pxa27x()) { |
04fef228 EM |
445 | |
446 | reset_status = RCSR; | |
447 | ||
0a0300dc | 448 | clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs)); |
a6dba20c | 449 | |
fef1f99a | 450 | if ((ret = pxa_init_dma(IRQ_DMA, 32))) |
f53f066c | 451 | return ret; |
f79299ca | 452 | |
711be5cc | 453 | pxa27x_init_pm(); |
f79299ca | 454 | |
2eaa03b5 RW |
455 | register_syscore_ops(&pxa_irq_syscore_ops); |
456 | register_syscore_ops(&pxa2xx_mfp_syscore_ops); | |
457 | register_syscore_ops(&pxa_gpio_syscore_ops); | |
458 | register_syscore_ops(&pxa2xx_clock_syscore_ops); | |
c0165504 | 459 | |
e176bb05 RK |
460 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); |
461 | } | |
c0165504 | 462 | |
e176bb05 | 463 | return ret; |
1da177e4 LT |
464 | } |
465 | ||
1c104e0e | 466 | postcore_initcall(pxa27x_init); |