[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-pxa / pxa27x.c

/*
 *  linux/arch/arm/mach-pxa/pxa27x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Nov 05, 2002
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA27x aka Bulverde.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <mach/irqs.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-regs.h>
#include <mach/mfp-pxa27x.h>
#include <mach/reset.h>
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/i2c.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

void pxa27x_clear_otgph(void)
{
	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
		PSSR |= PSSR_OTGPH;
}
EXPORT_SYMBOL(pxa27x_clear_otgph);

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa27x_get_clk_frequency_khz(int info)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M, n2, N, S;
       	int cccr_a, t, ht, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	t  = clkcfg & (1 << 0);
	ht = clkcfg & (1 << 2);
	b  = clkcfg & (1 << 3);

	l  = ccsr & 0x1f;
	n2 = (ccsr>>7) & 0xf;
	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L  = l * BASE_CLK;
	N  = (L * n2) / 2;
	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	S  = (b) ? L : (L/2);

	if (info) {
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
			(t) ? "" : "in" );
		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
			S / 1000000, (S % 1000000) / 10000 );
	}

	return (t) ? (N/1000) : (L/1000);
}

/*
 * Return the current mem clock frequency in units of 10kHz as
 * reflected by CCCR[A], B, and L
 */
unsigned int pxa27x_get_memclk_frequency_10khz(void)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M;
       	int cccr_a, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	b = clkcfg & (1 << 3);

	l = ccsr & 0x1f;
	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L = l * BASE_CLK;
	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));

	return (M / 10000);
}

/*
 * Return the current LCD clock frequency in units of 10kHz as
 */
static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
{
	unsigned long ccsr;
	unsigned int l, L, k, K;

	ccsr = CCSR;

	l = ccsr & 0x1f;
	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;

	L = l * BASE_CLK;
	K = L / k;

	return (K / 10000);
}

static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
{
	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
}

static const struct clkops clk_pxa27x_lcd_ops = {
	.enable		= clk_cken_enable,
	.disable	= clk_cken_disable,
	.getrate	= clk_pxa27x_lcd_getrate,
};

static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1);
static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0);
static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0);
static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5);
static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0);
static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0);
static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0);
static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0);
static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0);
static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
static DEFINE_CKEN(pxa27x_im, IM, 0, 0);
static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0);

static struct clk_lookup pxa27x_clkregs[] = {
	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
};

#ifdef CONFIG_PM

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */
enum {
	SLEEP_SAVE_PSTR,
	SLEEP_SAVE_CKEN,
	SLEEP_SAVE_MDREFR,
	SLEEP_SAVE_PCFR,
	SLEEP_SAVE_COUNT
};

void pxa27x_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(MDREFR);
	SAVE(PCFR);

	SAVE(CKEN);
	SAVE(PSTR);
}

void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
{
	RESTORE(MDREFR);
	RESTORE(PCFR);

	PSSR = PSSR_RDH | PSSR_PH;

	RESTORE(CKEN);
	RESTORE(PSTR);
}

void pxa27x_cpu_pm_enter(suspend_state_t state)
{
	extern void pxa_cpu_standby(void);

	/* ensure voltage-change sequencer not initiated, which hangs */
	PCFR &= ~PCFR_FVC;

	/* Clear edge-detect status register. */
	PEDR = 0xDF12FE1B;

	/* Clear reset status */
	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa_cpu_standby();
		break;
	case PM_SUSPEND_MEM:
		pxa27x_cpu_suspend(PWRMODE_SLEEP);
		break;
	}
}

static int pxa27x_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static int pxa27x_cpu_pm_prepare(void)
{
	/* set resume return address */
	PSPR = virt_to_phys(pxa_cpu_resume);
	return 0;
}

static void pxa27x_cpu_pm_finish(void)
{
	/* ensure not to come back here if it wasn't intended */
	PSPR = 0;
}

static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.save		= pxa27x_cpu_pm_save,
	.restore	= pxa27x_cpu_pm_restore,
	.valid		= pxa27x_cpu_pm_valid,
	.enter		= pxa27x_cpu_pm_enter,
	.prepare	= pxa27x_cpu_pm_prepare,
	.finish		= pxa27x_cpu_pm_finish,
};

static void __init pxa27x_init_pm(void)
{
	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
}
#else
static inline void pxa27x_init_pm(void) {}
#endif

/* PXA27x:  Various gpios can issue wakeup events.  This logic only
 * handles the simple cases, not the WEMUX2 and WEMUX3 options
 */
static int pxa27x_set_wake(unsigned int irq, unsigned int on)
{
	int gpio = IRQ_TO_GPIO(irq);
	uint32_t mask;

	if (gpio >= 0 && gpio < 128)
		return gpio_set_wake(gpio, on);

	if (irq == IRQ_KEYPAD)
		return keypad_set_wake(on);

	switch (irq) {
	case IRQ_RTCAlrm:
		mask = PWER_RTC;
		break;
	case IRQ_USB:
		mask = 1u << 26;
		break;
	default:
		return -EINVAL;
	}

	if (on)
		PWER |= mask;
	else
		PWER &=~mask;

	return 0;
}

void __init pxa27x_init_irq(void)
{
	pxa_init_irq(34, pxa27x_set_wake);
	pxa_init_gpio(121, pxa27x_set_wake);
}

/*
 * device registration specific to PXA27x.
 */
void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	local_irq_disable();
	PCFR |= PCFR_PI2CEN;
	local_irq_enable();
	pxa_register_device(&pxa27x_device_i2c_power, info);
}

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_ffuart,
	&pxa_device_btuart,
	&pxa_device_stuart,
	&pxa_device_i2s,
	&sa1100_device_rtc,
	&pxa_device_rtc,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static struct sys_device pxa27x_sysdev[] = {
	{
		.cls	= &pxa_irq_sysclass,
	}, {
		.cls	= &pxa2xx_mfp_sysclass,
	}, {
		.cls	= &pxa_gpio_sysclass,
	},
};

static int __init pxa27x_init(void)
{
	int i, ret = 0;

	if (cpu_is_pxa27x()) {

		reset_status = RCSR;

		clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));

		if ((ret = pxa_init_dma(32)))
			return ret;

		pxa27x_init_pm();

		for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
			ret = sysdev_register(&pxa27x_sysdev[i]);
			if (ret)
				pr_err("failed to register sysdev[%d]\n", i);
		}

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa27x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa27x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Nov 05, 2002
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA27x aka Bulverde.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
1da177e4 LT	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
95d9ffbe	17	#include <linux/suspend.h>
d052d1be	18	#include <linux/platform_device.h>
c0165504	19	#include <linux/sysdev.h>
1da177e4	20
a09e64fb	21	#include <mach/hardware.h>
1da177e4	22	#include <asm/irq.h>
a09e64fb RK	23	#include <mach/irqs.h>
	24	#include <mach/pxa-regs.h>
	25	#include <mach/pxa2xx-regs.h>
	26	#include <mach/mfp-pxa27x.h>
afd2fc02	27	#include <mach/reset.h>
a09e64fb RK	28	#include <mach/ohci.h>
	29	#include <mach/pm.h>
	30	#include <mach/dma.h>
	31	#include <mach/i2c.h>
1da177e4 LT	32
1da177e4 LT	33	#include "generic.h"
46c41e62	34	#include "devices.h"
a6dba20c	35	#include "clock.h"
1da177e4	36
0cb0b0d3 EM	37	void pxa27x_clear_otgph(void)
	38	{
	39	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
	40	PSSR \|= PSSR_OTGPH;
	41	}
	42	EXPORT_SYMBOL(pxa27x_clear_otgph);
	43
1da177e4 LT	44	/* Crystal clock: 13MHz */
	45	#define BASE_CLK 13000000
	46
	47	/*
	48	* Get the clock frequency as reflected by CCSR and the turbo flag.
	49	* We assume these values have been applied via a fcs.
	50	* If info is not 0 we also display the current settings.
	51	*/
15a40333	52	unsigned int pxa27x_get_clk_frequency_khz(int info)
1da177e4 LT	53	{
	54	unsigned long ccsr, clkcfg;
	55	unsigned int l, L, m, M, n2, N, S;
	56	int cccr_a, t, ht, b;
	57
	58	ccsr = CCSR;
	59	cccr_a = CCCR & (1 << 25);
	60
	61	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	62	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
afe5df20	63	t = clkcfg & (1 << 0);
1da177e4 LT	64	ht = clkcfg & (1 << 2);
	65	b = clkcfg & (1 << 3);
	66
	67	l = ccsr & 0x1f;
	68	n2 = (ccsr>>7) & 0xf;
	69	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	70
	71	L = l * BASE_CLK;
	72	N = (L * n2) / 2;
	73	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	74	S = (b) ? L : (L/2);
	75
	76	if (info) {
	77	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	78	L / 1000000, (L % 1000000) / 10000, l );
	79	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	80	N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
	81	(t) ? "" : "in" );
	82	printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
	83	M / 1000000, (M % 1000000) / 10000, m );
	84	printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
	85	S / 1000000, (S % 1000000) / 10000 );
	86	}
	87
	88	return (t) ? (N/1000) : (L/1000);
	89	}
	90
	91	/*
	92	* Return the current mem clock frequency in units of 10kHz as
	93	* reflected by CCCR[A], B, and L
	94	*/
15a40333	95	unsigned int pxa27x_get_memclk_frequency_10khz(void)
1da177e4 LT	96	{
	97	unsigned long ccsr, clkcfg;
	98	unsigned int l, L, m, M;
	99	int cccr_a, b;
	100
	101	ccsr = CCSR;
	102	cccr_a = CCCR & (1 << 25);
	103
	104	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	105	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	106	b = clkcfg & (1 << 3);
	107
	108	l = ccsr & 0x1f;
	109	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	110
	111	L = l * BASE_CLK;
	112	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	113
	114	return (M / 10000);
	115	}
	116
	117	/*
	118	* Return the current LCD clock frequency in units of 10kHz as
	119	*/
a88a447d	120	static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
1da177e4 LT	121	{
	122	unsigned long ccsr;
	123	unsigned int l, L, k, K;
	124
	125	ccsr = CCSR;
	126
	127	l = ccsr & 0x1f;
	128	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
	129
	130	L = l * BASE_CLK;
	131	K = L / k;
	132
	133	return (K / 10000);
	134	}
	135
a6dba20c RK	136	static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
	137	{
	138	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
	139	}
	140
	141	static const struct clkops clk_pxa27x_lcd_ops = {
	142	.enable = clk_cken_enable,
	143	.disable = clk_cken_disable,
	144	.getrate = clk_pxa27x_lcd_getrate,
	145	};
	146
8c3abc7d RK	147	static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
	148	static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
	149	static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
	150	static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
	151	static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1);
	152	static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0);
	153	static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0);
	154	static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5);
	155	static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0);
	156	static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0);
	157	static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
	158	static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
	159	static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
	160	static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
	161	static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
	162	static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
	163	static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
	164	static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
	165	static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0);
	166	static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
	167	static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0);
	168	static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0);
	169	static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
	170	static DEFINE_CKEN(pxa27x_im, IM, 0, 0);
	171	static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0);
	172
	173	static struct clk_lookup pxa27x_clkregs[] = {
	174	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
	175	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
	176	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
	177	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
	178	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
	179	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
	180	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
	181	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
	182	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
	183	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
	184	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
	185	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
	186	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
	187	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
	188	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
	189	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
	190	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
	191	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
	192	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
	193	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
	194	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
	195	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
	196	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
	197	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
	198	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
	199	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
a6dba20c RK	200	};
a6dba20c RK	201
a8fa3f0c NP	202	#ifdef CONFIG_PM
a8fa3f0c NP	203
711be5cc EM	204	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
	205	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
	206
711be5cc EM	207	/*
	208	* List of global PXA peripheral registers to preserve.
	209	* More ones like CP and general purpose register values are preserved
	210	* with the stack pointer in sleep.S.
	211	*/
5a3d9651	212	enum {
711be5cc	213	SLEEP_SAVE_PSTR,
711be5cc	214	SLEEP_SAVE_CKEN,
711be5cc	215	SLEEP_SAVE_MDREFR,
5a3d9651	216	SLEEP_SAVE_PCFR,
649de51b	217	SLEEP_SAVE_COUNT
711be5cc EM	218	};
	219
	220	void pxa27x_cpu_pm_save(unsigned long *sleep_save)
	221	{
711be5cc	222	SAVE(MDREFR);
5a3d9651	223	SAVE(PCFR);
711be5cc	224
711be5cc EM	225	SAVE(CKEN);
711be5cc EM	226	SAVE(PSTR);
711be5cc EM	227	}
	228
	229	void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
	230	{
711be5cc	231	RESTORE(MDREFR);
5a3d9651	232	RESTORE(PCFR);
711be5cc EM	233
	234	PSSR = PSSR_RDH \| PSSR_PH;
	235
	236	RESTORE(CKEN);
711be5cc EM	237	RESTORE(PSTR);
	238	}
	239
	240	void pxa27x_cpu_pm_enter(suspend_state_t state)
8775420d TP	241	{
8775420d TP	242	extern void pxa_cpu_standby(void);
8775420d	243
8775420d TP	244	/* ensure voltage-change sequencer not initiated, which hangs */
	245	PCFR &= ~PCFR_FVC;
	246
	247	/* Clear edge-detect status register. */
	248	PEDR = 0xDF12FE1B;
	249
dc38e2ad RK	250	/* Clear reset status */
	251	RCSR = RCSR_HWR \| RCSR_WDR \| RCSR_SMR \| RCSR_GPR;
	252
8775420d	253	switch (state) {
26705ca4 TP	254	case PM_SUSPEND_STANDBY:
	255	pxa_cpu_standby();
	256	break;
8775420d	257	case PM_SUSPEND_MEM:
b750a093	258	pxa27x_cpu_suspend(PWRMODE_SLEEP);
8775420d TP	259	break;
	260	}
	261	}
1da177e4	262
711be5cc	263	static int pxa27x_cpu_pm_valid(suspend_state_t state)
88dfe98c RK	264	{
	265	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	266	}
	267
4104980a RK	268	static int pxa27x_cpu_pm_prepare(void)
	269	{
	270	/* set resume return address */
	271	PSPR = virt_to_phys(pxa_cpu_resume);
	272	return 0;
	273	}
	274
	275	static void pxa27x_cpu_pm_finish(void)
	276	{
	277	/* ensure not to come back here if it wasn't intended */
	278	PSPR = 0;
	279	}
	280
711be5cc	281	static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
649de51b	282	.save_count = SLEEP_SAVE_COUNT,
711be5cc EM	283	.save = pxa27x_cpu_pm_save,
	284	.restore = pxa27x_cpu_pm_restore,
	285	.valid = pxa27x_cpu_pm_valid,
	286	.enter = pxa27x_cpu_pm_enter,
4104980a RK	287	.prepare = pxa27x_cpu_pm_prepare,
4104980a RK	288	.finish = pxa27x_cpu_pm_finish,
e176bb05	289	};
711be5cc EM	290
	291	static void __init pxa27x_init_pm(void)
	292	{
	293	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
	294	}
f79299ca	295	#else
f79299ca	296	static inline void pxa27x_init_pm(void) {}
a8fa3f0c NP	297	#endif
a8fa3f0c NP	298
c95530c7	299	/* PXA27x: Various gpios can issue wakeup events. This logic only
	300	* handles the simple cases, not the WEMUX2 and WEMUX3 options
	301	*/
c95530c7	302	static int pxa27x_set_wake(unsigned int irq, unsigned int on)
	303	{
	304	int gpio = IRQ_TO_GPIO(irq);
	305	uint32_t mask;
	306
c0a596d6	307	if (gpio >= 0 && gpio < 128)
c0a596d6	308	return gpio_set_wake(gpio, on);
c95530c7	309
c0a596d6	310	if (irq == IRQ_KEYPAD)
c0a596d6	311	return keypad_set_wake(on);
c95530c7	312
	313	switch (irq) {
	314	case IRQ_RTCAlrm:
	315	mask = PWER_RTC;
	316	break;
	317	case IRQ_USB:
	318	mask = 1u << 26;
	319	break;
	320	default:
	321	return -EINVAL;
	322	}
	323
c95530c7	324	if (on)
	325	PWER \|= mask;
	326	else
	327	PWER &=~mask;
	328
	329	return 0;
	330	}
	331
	332	void __init pxa27x_init_irq(void)
	333	{
b9e25ace	334	pxa_init_irq(34, pxa27x_set_wake);
ddd244dd	335	pxa_init_gpio(121, pxa27x_set_wake);
c95530c7	336	}
c95530c7	337
1da177e4 LT	338	/*
	339	* device registration specific to PXA27x.
	340	*/
9ba63c4f	341	void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
b7a36701	342	{
bc3a5959 PZ	343	local_irq_disable();
	344	PCFR \|= PCFR_PI2CEN;
	345	local_irq_enable();
14758220	346	pxa_register_device(&pxa27x_device_i2c_power, info);
b7a36701 MR	347	}
b7a36701 MR	348
1da177e4	349	static struct platform_device *devices[] __initdata = {
7a857620	350	&pxa27x_device_udc,
e09d02e1 EM	351	&pxa_device_ffuart,
	352	&pxa_device_btuart,
	353	&pxa_device_stuart,
e09d02e1	354	&pxa_device_i2s,
72493146	355	&sa1100_device_rtc,
e09d02e1	356	&pxa_device_rtc,
d8e0db11	357	&pxa27x_device_ssp1,
	358	&pxa27x_device_ssp2,
	359	&pxa27x_device_ssp3,
75540c1a	360	&pxa27x_device_pwm0,
75540c1a	361	&pxa27x_device_pwm1,
1da177e4 LT	362	};
1da177e4 LT	363
c0165504	364	static struct sys_device pxa27x_sysdev[] = {
c0165504	365	{
c0165504	366	.cls = &pxa_irq_sysclass,
5a3d9651 EM	367	}, {
5a3d9651 EM	368	.cls = &pxa2xx_mfp_sysclass,
16dfdbf0	369	}, {
16dfdbf0	370	.cls = &pxa_gpio_sysclass,
c0165504	371	},
	372	};
	373
1da177e4 LT	374	static int __init pxa27x_init(void)
1da177e4 LT	375	{
c0165504	376	int i, ret = 0;
c0165504	377
e176bb05	378	if (cpu_is_pxa27x()) {
04fef228 EM	379
	380	reset_status = RCSR;
	381
8c3abc7d	382	clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
a6dba20c	383
f53f066c EM	384	if ((ret = pxa_init_dma(32)))
f53f066c EM	385	return ret;
f79299ca	386
711be5cc	387	pxa27x_init_pm();
f79299ca	388
c0165504	389	for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
	390	ret = sysdev_register(&pxa27x_sysdev[i]);
	391	if (ret)
	392	pr_err("failed to register sysdev[%d]\n", i);
	393	}
	394
e176bb05 RK	395	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
e176bb05 RK	396	}
c0165504	397
e176bb05	398	return ret;
1da177e4 LT	399	}
1da177e4 LT	400
1c104e0e	401	postcore_initcall(pxa27x_init);