[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-pxa / pxa27x.c

/*
 *  linux/arch/arm/mach-pxa/pxa27x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Nov 05, 2002
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA27x aka Bulverde.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/platform_device.h>

#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/ohci.h>
#include <asm/arch/pm.h>

#include "generic.h"

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int get_clk_frequency_khz( int info)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M, n2, N, S;
       	int cccr_a, t, ht, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	t  = clkcfg & (1 << 0);
	ht = clkcfg & (1 << 2);
	b  = clkcfg & (1 << 3);

	l  = ccsr & 0x1f;
	n2 = (ccsr>>7) & 0xf;
	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L  = l * BASE_CLK;
	N  = (L * n2) / 2;
	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	S  = (b) ? L : (L/2);

	if (info) {
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
			(t) ? "" : "in" );
		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
			S / 1000000, (S % 1000000) / 10000 );
	}

	return (t) ? (N/1000) : (L/1000);
}

/*
 * Return the current mem clock frequency in units of 10kHz as
 * reflected by CCCR[A], B, and L
 */
unsigned int get_memclk_frequency_10khz(void)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M;
       	int cccr_a, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	b = clkcfg & (1 << 3);

	l = ccsr & 0x1f;
	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L = l * BASE_CLK;
	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));

	return (M / 10000);
}

/*
 * Return the current LCD clock frequency in units of 10kHz as
 */
unsigned int get_lcdclk_frequency_10khz(void)
{
	unsigned long ccsr;
	unsigned int l, L, k, K;

	ccsr = CCSR;

	l = ccsr & 0x1f;
	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;

	L = l * BASE_CLK;
	K = L / k;

	return (K / 10000);
}

EXPORT_SYMBOL(get_clk_frequency_khz);
EXPORT_SYMBOL(get_memclk_frequency_10khz);
EXPORT_SYMBOL(get_lcdclk_frequency_10khz);

#ifdef CONFIG_PM

int pxa_pm_prepare(suspend_state_t state)
{
	switch (state) {
	case PM_SUSPEND_MEM:
	case PM_SUSPEND_STANDBY:
		return 0;
	default:
		return -EINVAL;
	}
}

void pxa_cpu_pm_enter(suspend_state_t state)
{
	extern void pxa_cpu_standby(void);
	extern void pxa_cpu_suspend(unsigned int);
	extern void pxa_cpu_resume(void);

	if (state == PM_SUSPEND_STANDBY)
		CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) | (1 << CKEN_LCD) | (1 << CKEN_PWM0);
	else
		CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER);

	/* ensure voltage-change sequencer not initiated, which hangs */
	PCFR &= ~PCFR_FVC;

	/* Clear edge-detect status register. */
	PEDR = 0xDF12FE1B;

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa_cpu_standby();
		break;
	case PM_SUSPEND_MEM:
		/* set resume return address */
		PSPR = virt_to_phys(pxa_cpu_resume);
		pxa_cpu_suspend(PWRMODE_SLEEP);
		break;
	}
}

static struct pm_ops pxa27x_pm_ops = {
	.prepare	= pxa_pm_prepare,
	.enter		= pxa_pm_enter,
	.valid		= pm_valid_only_mem,
};
#endif

/*
 * device registration specific to PXA27x.
 */

static u64 pxa27x_dmamask = 0xffffffffUL;

static struct resource pxa27x_ohci_resources[] = {
	[0] = {
		.start  = 0x4C000000,
		.end    = 0x4C00ff6f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = IRQ_USBH1,
		.end    = IRQ_USBH1,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device ohci_device = {
	.name		= "pxa27x-ohci",
	.id		= -1,
	.dev		= {
		.dma_mask = &pxa27x_dmamask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources  = ARRAY_SIZE(pxa27x_ohci_resources),
	.resource       = pxa27x_ohci_resources,
};

void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
{
	ohci_device.dev.platform_data = info;
}

static struct platform_device *devices[] __initdata = {
	&ohci_device,
};

static int __init pxa27x_init(void)
{
	int ret = 0;
	if (cpu_is_pxa27x()) {
#ifdef CONFIG_PM
		pm_set_ops(&pxa27x_pm_ops);
#endif
		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}
	return ret;
}

subsys_initcall(pxa27x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa27x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Nov 05, 2002
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA27x aka Bulverde.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
1da177e4 LT	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
	17	#include <linux/pm.h>
d052d1be	18	#include <linux/platform_device.h>
1da177e4 LT	19
	20	#include <asm/hardware.h>
	21	#include <asm/irq.h>
	22	#include <asm/arch/pxa-regs.h>
81f280e2	23	#include <asm/arch/ohci.h>
e176bb05	24	#include <asm/arch/pm.h>
1da177e4 LT	25
	26	#include "generic.h"
	27
	28	/* Crystal clock: 13MHz */
	29	#define BASE_CLK 13000000
	30
	31	/*
	32	* Get the clock frequency as reflected by CCSR and the turbo flag.
	33	* We assume these values have been applied via a fcs.
	34	* If info is not 0 we also display the current settings.
	35	*/
	36	unsigned int get_clk_frequency_khz( int info)
	37	{
	38	unsigned long ccsr, clkcfg;
	39	unsigned int l, L, m, M, n2, N, S;
	40	int cccr_a, t, ht, b;
	41
	42	ccsr = CCSR;
	43	cccr_a = CCCR & (1 << 25);
	44
	45	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	46	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
afe5df20	47	t = clkcfg & (1 << 0);
1da177e4 LT	48	ht = clkcfg & (1 << 2);
	49	b = clkcfg & (1 << 3);
	50
	51	l = ccsr & 0x1f;
	52	n2 = (ccsr>>7) & 0xf;
	53	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	54
	55	L = l * BASE_CLK;
	56	N = (L * n2) / 2;
	57	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	58	S = (b) ? L : (L/2);
	59
	60	if (info) {
	61	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	62	L / 1000000, (L % 1000000) / 10000, l );
	63	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	64	N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
	65	(t) ? "" : "in" );
	66	printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
	67	M / 1000000, (M % 1000000) / 10000, m );
	68	printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
	69	S / 1000000, (S % 1000000) / 10000 );
	70	}
	71
	72	return (t) ? (N/1000) : (L/1000);
	73	}
	74
	75	/*
	76	* Return the current mem clock frequency in units of 10kHz as
	77	* reflected by CCCR[A], B, and L
	78	*/
	79	unsigned int get_memclk_frequency_10khz(void)
	80	{
	81	unsigned long ccsr, clkcfg;
	82	unsigned int l, L, m, M;
	83	int cccr_a, b;
	84
	85	ccsr = CCSR;
	86	cccr_a = CCCR & (1 << 25);
	87
	88	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	89	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	90	b = clkcfg & (1 << 3);
	91
	92	l = ccsr & 0x1f;
	93	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	94
	95	L = l * BASE_CLK;
	96	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	97
	98	return (M / 10000);
	99	}
	100
	101	/*
	102	* Return the current LCD clock frequency in units of 10kHz as
	103	*/
	104	unsigned int get_lcdclk_frequency_10khz(void)
	105	{
	106	unsigned long ccsr;
	107	unsigned int l, L, k, K;
	108
	109	ccsr = CCSR;
	110
	111	l = ccsr & 0x1f;
112	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
113
114	L = l * BASE_CLK;
115	K = L / k;
116
117	return (K / 10000);
118	}
119
120	EXPORT_SYMBOL(get_clk_frequency_khz);
121	EXPORT_SYMBOL(get_memclk_frequency_10khz);
122	EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
123
a8fa3f0c NP	124	#ifdef CONFIG_PM
a8fa3f0c NP	125
e176bb05	126	int pxa_pm_prepare(suspend_state_t state)
8775420d TP	127	{
	128	switch (state) {
	129	case PM_SUSPEND_MEM:
26705ca4	130	case PM_SUSPEND_STANDBY:
8775420d TP	131	return 0;
	132	default:
	133	return -EINVAL;
	134	}
	135	}
	136
	137	void pxa_cpu_pm_enter(suspend_state_t state)
	138	{
	139	extern void pxa_cpu_standby(void);
	140	extern void pxa_cpu_suspend(unsigned int);
	141	extern void pxa_cpu_resume(void);
	142
26705ca4	143	if (state == PM_SUSPEND_STANDBY)
1f750a78	144	CKEN = (1 << CKEN_MEMC) \| (1 << CKEN_OSTIMER) \| (1 << CKEN_LCD) \| (1 << CKEN_PWM0);
26705ca4	145	else
1f750a78	146	CKEN = (1 << CKEN_MEMC) \| (1 << CKEN_OSTIMER);
8775420d TP	147
	148	/* ensure voltage-change sequencer not initiated, which hangs */
	149	PCFR &= ~PCFR_FVC;
	150
	151	/* Clear edge-detect status register. */
	152	PEDR = 0xDF12FE1B;
	153
	154	switch (state) {
26705ca4 TP	155	case PM_SUSPEND_STANDBY:
	156	pxa_cpu_standby();
	157	break;
8775420d TP	158	case PM_SUSPEND_MEM:
	159	/* set resume return address */
	160	PSPR = virt_to_phys(pxa_cpu_resume);
80a18573	161	pxa_cpu_suspend(PWRMODE_SLEEP);
8775420d TP	162	break;
	163	}
	164	}
1da177e4	165
e176bb05 RK	166	static struct pm_ops pxa27x_pm_ops = {
	167	.prepare = pxa_pm_prepare,
	168	.enter = pxa_pm_enter,
	169	.valid = pm_valid_only_mem,
	170	};
a8fa3f0c NP	171	#endif
a8fa3f0c NP	172
1da177e4 LT	173	/*
	174	* device registration specific to PXA27x.
	175	*/
	176
	177	static u64 pxa27x_dmamask = 0xffffffffUL;
	178
	179	static struct resource pxa27x_ohci_resources[] = {
	180	[0] = {
	181	.start = 0x4C000000,
	182	.end = 0x4C00ff6f,
	183	.flags = IORESOURCE_MEM,
	184	},
	185	[1] = {
	186	.start = IRQ_USBH1,
	187	.end = IRQ_USBH1,
	188	.flags = IORESOURCE_IRQ,
	189	},
	190	};
	191
	192	static struct platform_device ohci_device = {
	193	.name = "pxa27x-ohci",
	194	.id = -1,
	195	.dev = {
	196	.dma_mask = &pxa27x_dmamask,
	197	.coherent_dma_mask = 0xffffffff,
	198	},
	199	.num_resources = ARRAY_SIZE(pxa27x_ohci_resources),
	200	.resource = pxa27x_ohci_resources,
	201	};
	202
81f280e2 RP	203	void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
	204	{
	205	ohci_device.dev.platform_data = info;
	206	}
	207
1da177e4 LT	208	static struct platform_device *devices[] __initdata = {
	209	&ohci_device,
	210	};
	211
	212	static int __init pxa27x_init(void)
	213	{
e176bb05 RK	214	int ret = 0;
	215	if (cpu_is_pxa27x()) {
	216	#ifdef CONFIG_PM
	217	pm_set_ops(&pxa27x_pm_ops);
	218	#endif
	219	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	220	}
	221	return ret;
1da177e4 LT	222	}
	223
	224	subsys_initcall(pxa27x_init);