[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-pxa / pxa3xx.c

/*
 * linux/arch/arm/mach-pxa/pxa3xx.c
 *
 * code specific to pxa3xx aka Monahans
 *
 * Copyright (C) 2006 Marvell International Ltd.
 *
 * 2007-09-02: eric miao <eric.miao@marvell.com>
 *             initial version
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sysdev.h>

#include <mach/hardware.h>
#include <mach/gpio.h>
#include <mach/pxa3xx-regs.h>
#include <mach/reset.h>
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/ssp.h>
#include <mach/regs-intc.h>
#include <plat/i2c.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/* Ring Oscillator Clock: 60MHz */
#define RO_CLK		60000000

#define ACCR_D0CS	(1 << 26)
#define ACCR_PCCE	(1 << 11)

#define PECR_IE(n)	((1 << ((n) * 2)) << 28)
#define PECR_IS(n)	((1 << ((n) * 2)) << 29)

/* crystal frequency to static memory controller multiplier (SMCFS) */
static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };

/* crystal frequency to HSIO bus frequency multiplier (HSS) */
static unsigned char hss_mult[4] = { 8, 12, 16, 0 };

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa3xx_get_clk_frequency_khz(int info)
{
	unsigned long acsr, xclkcfg;
	unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;

	/* Read XCLKCFG register turbo bit */
	__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
	t = xclkcfg & 0x1;

	acsr = ACSR;

	xl  = acsr & 0x1f;
	xn  = (acsr >> 8) & 0x7;
	hss = (acsr >> 14) & 0x3;

	XL = xl * BASE_CLK;
	XN = xn * XL;

	ro = acsr & ACCR_D0CS;

	CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
	HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;

	if (info) {
		pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
			RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
			(ro) ? "" : "in");
		pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
			XL / 1000000, (XL % 1000000) / 10000, xl);
		pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
			XN / 1000000, (XN % 1000000) / 10000, xn,
			(t) ? "" : "in");
		pr_info("HSIO bus clock: %d.%02dMHz\n",
			HSS / 1000000, (HSS % 1000000) / 10000);
	}

	return CLK / 1000;
}

/*
 * Return the current static memory controller clock frequency
 * in units of 10kHz
 */
unsigned int pxa3xx_get_memclk_frequency_10khz(void)
{
	unsigned long acsr;
	unsigned int smcfs, clk = 0;

	acsr = ACSR;

	smcfs = (acsr >> 23) & 0x7;
	clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;

	return (clk / 10000);
}

void pxa3xx_clear_reset_status(unsigned int mask)
{
	/* RESET_STATUS_* has a 1:1 mapping with ARSR */
	ARSR = mask;
}

/*
 * Return the current AC97 clock frequency.
 */
static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
{
	unsigned long rate = 312000000;
	unsigned long ac97_div;

	ac97_div = AC97_DIV;

	/* This may loose precision for some rates but won't for the
	 * standard 24.576MHz.
	 */
	rate /= (ac97_div >> 12) & 0x7fff;
	rate *= (ac97_div & 0xfff);

	return rate;
}

/*
 * Return the current HSIO bus clock frequency
 */
static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
{
	unsigned long acsr;
	unsigned int hss, hsio_clk;

	acsr = ACSR;

	hss = (acsr >> 14) & 0x3;
	hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;

	return hsio_clk;
}

void clk_pxa3xx_cken_enable(struct clk *clk)
{
	unsigned long mask = 1ul << (clk->cken & 0x1f);

	if (clk->cken < 32)
		CKENA |= mask;
	else
		CKENB |= mask;
}

void clk_pxa3xx_cken_disable(struct clk *clk)
{
	unsigned long mask = 1ul << (clk->cken & 0x1f);

	if (clk->cken < 32)
		CKENA &= ~mask;
	else
		CKENB &= ~mask;
}

const struct clkops clk_pxa3xx_cken_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
};

static const struct clkops clk_pxa3xx_hsio_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
	.getrate	= clk_pxa3xx_hsio_getrate,
};

static const struct clkops clk_pxa3xx_ac97_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
	.getrate	= clk_pxa3xx_ac97_getrate,
};

static void clk_pout_enable(struct clk *clk)
{
	OSCC |= OSCC_PEN;
}

static void clk_pout_disable(struct clk *clk)
{
	OSCC &= ~OSCC_PEN;
}

static const struct clkops clk_pout_ops = {
	.enable		= clk_pout_enable,
	.disable	= clk_pout_disable,
};

static void clk_dummy_enable(struct clk *clk)
{
}

static void clk_dummy_disable(struct clk *clk)
{
}

static const struct clkops clk_dummy_ops = {
	.enable		= clk_dummy_enable,
	.disable	= clk_dummy_disable,
};

static struct clk clk_pxa3xx_pout = {
	.ops		= &clk_pout_ops,
	.rate		= 13000000,
	.delay		= 70,
};

static struct clk clk_dummy = {
	.ops		= &clk_dummy_ops,
};

static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);

static struct clk_lookup pxa3xx_clkregs[] = {
	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	/* Power I2C clock is always on */
	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
	INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"),
	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
};

#ifdef CONFIG_PM

#define ISRAM_START	0x5c000000
#define ISRAM_SIZE	SZ_256K

static void __iomem *sram;
static unsigned long wakeup_src;

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

enum {	SLEEP_SAVE_CKENA,
	SLEEP_SAVE_CKENB,
	SLEEP_SAVE_ACCR,

	SLEEP_SAVE_COUNT,
};

static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(CKENA);
	SAVE(CKENB);
	SAVE(ACCR);
}

static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
{
	RESTORE(ACCR);
	RESTORE(CKENA);
	RESTORE(CKENB);
}

/*
 * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 * memory controller has to be reinitialised, so we place some code
 * in the SRAM to perform this function.
 *
 * We disable FIQs across the standby - otherwise, we might receive a
 * FIQ while the SDRAM is unavailable.
 */
static void pxa3xx_cpu_standby(unsigned int pwrmode)
{
	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);

	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
		    pm_enter_standby_end - pm_enter_standby_start);

	AD2D0SR = ~0;
	AD2D1SR = ~0;
	AD2D0ER = wakeup_src;
	AD2D1ER = 0;
	ASCR = ASCR;
	ARSR = ARSR;

	local_fiq_disable();
	fn(pwrmode);
	local_fiq_enable();

	AD2D0ER = 0;
	AD2D1ER = 0;
}

/*
 * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 * PXA3xx development kits assumes that the resuming process continues
 * with the address stored within the first 4 bytes of SDRAM. The PSPR
 * register is used privately by BootROM and OBM, and _must_ be set to
 * 0x5c014000 for the moment.
 */
static void pxa3xx_cpu_pm_suspend(void)
{
	volatile unsigned long *p = (volatile void *)0xc0000000;
	unsigned long saved_data = *p;

	extern void pxa3xx_cpu_suspend(void);
	extern void pxa3xx_cpu_resume(void);

	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);

	/* clear and setup wakeup source */
	AD3SR = ~0;
	AD3ER = wakeup_src;
	ASCR = ASCR;
	ARSR = ARSR;

	PCFR |= (1u << 13);			/* L1_DIS */
	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */

	PSPR = 0x5c014000;

	/* overwrite with the resume address */
	*p = virt_to_phys(pxa3xx_cpu_resume);

	pxa3xx_cpu_suspend();

	*p = saved_data;

	AD3ER = 0;
}

static void pxa3xx_cpu_pm_enter(suspend_state_t state)
{
	/*
	 * Don't sleep if no wakeup sources are defined
	 */
	if (wakeup_src == 0) {
		printk(KERN_ERR "Not suspending: no wakeup sources\n");
		return;
	}

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
		break;

	case PM_SUSPEND_MEM:
		pxa3xx_cpu_pm_suspend();
		break;
	}
}

static int pxa3xx_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.save		= pxa3xx_cpu_pm_save,
	.restore	= pxa3xx_cpu_pm_restore,
	.valid		= pxa3xx_cpu_pm_valid,
	.enter		= pxa3xx_cpu_pm_enter,
};

static void __init pxa3xx_init_pm(void)
{
	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	if (!sram) {
		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
		return;
	}

	/*
	 * Since we copy wakeup code into the SRAM, we need to ensure
	 * that it is preserved over the low power modes.  Note: bit 8
	 * is undocumented in the developer manual, but must be set.
	 */
	AD1R |= ADXR_L2 | ADXR_R0;
	AD2R |= ADXR_L2 | ADXR_R0;
	AD3R |= ADXR_L2 | ADXR_R0;

	/*
	 * Clear the resume enable registers.
	 */
	AD1D0ER = 0;
	AD2D0ER = 0;
	AD2D1ER = 0;
	AD3ER = 0;

	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
}

static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
{
	unsigned long flags, mask = 0;

	switch (irq) {
	case IRQ_SSP3:
		mask = ADXER_MFP_WSSP3;
		break;
	case IRQ_MSL:
		mask = ADXER_WMSL0;
		break;
	case IRQ_USBH2:
	case IRQ_USBH1:
		mask = ADXER_WUSBH;
		break;
	case IRQ_KEYPAD:
		mask = ADXER_WKP;
		break;
	case IRQ_AC97:
		mask = ADXER_MFP_WAC97;
		break;
	case IRQ_USIM:
		mask = ADXER_WUSIM0;
		break;
	case IRQ_SSP2:
		mask = ADXER_MFP_WSSP2;
		break;
	case IRQ_I2C:
		mask = ADXER_MFP_WI2C;
		break;
	case IRQ_STUART:
		mask = ADXER_MFP_WUART3;
		break;
	case IRQ_BTUART:
		mask = ADXER_MFP_WUART2;
		break;
	case IRQ_FFUART:
		mask = ADXER_MFP_WUART1;
		break;
	case IRQ_MMC:
		mask = ADXER_MFP_WMMC1;
		break;
	case IRQ_SSP:
		mask = ADXER_MFP_WSSP1;
		break;
	case IRQ_RTCAlrm:
		mask = ADXER_WRTC;
		break;
	case IRQ_SSP4:
		mask = ADXER_MFP_WSSP4;
		break;
	case IRQ_TSI:
		mask = ADXER_WTSI;
		break;
	case IRQ_USIM2:
		mask = ADXER_WUSIM1;
		break;
	case IRQ_MMC2:
		mask = ADXER_MFP_WMMC2;
		break;
	case IRQ_NAND:
		mask = ADXER_MFP_WFLASH;
		break;
	case IRQ_USB2:
		mask = ADXER_WUSB2;
		break;
	case IRQ_WAKEUP0:
		mask = ADXER_WEXTWAKE0;
		break;
	case IRQ_WAKEUP1:
		mask = ADXER_WEXTWAKE1;
		break;
	case IRQ_MMC3:
		mask = ADXER_MFP_GEN12;
		break;
	default:
		return -EINVAL;
	}

	local_irq_save(flags);
	if (on)
		wakeup_src |= mask;
	else
		wakeup_src &= ~mask;
	local_irq_restore(flags);

	return 0;
}
#else
static inline void pxa3xx_init_pm(void) {}
#define pxa3xx_set_wake	NULL
#endif

static void pxa_ack_ext_wakeup(unsigned int irq)
{
	PECR |= PECR_IS(irq - IRQ_WAKEUP0);
}

static void pxa_mask_ext_wakeup(unsigned int irq)
{
	ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f));
	PECR &= ~PECR_IE(irq - IRQ_WAKEUP0);
}

static void pxa_unmask_ext_wakeup(unsigned int irq)
{
	ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f);
	PECR |= PECR_IE(irq - IRQ_WAKEUP0);
}

static struct irq_chip pxa_ext_wakeup_chip = {
	.name		= "WAKEUP",
	.ack		= pxa_ack_ext_wakeup,
	.mask		= pxa_mask_ext_wakeup,
	.unmask		= pxa_unmask_ext_wakeup,
};

static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
{
	int irq;

	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
		set_irq_chip(irq, &pxa_ext_wakeup_chip);
		set_irq_handler(irq, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	pxa_ext_wakeup_chip.set_wake = fn;
}

void __init pxa3xx_init_irq(void)
{
	/* enable CP6 access */
	u32 value;
	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	value |= (1 << 6);
	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));

	pxa_init_irq(56, pxa3xx_set_wake);
	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
	pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
}

/*
 * device registration specific to PXA3xx.
 */

void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	pxa_register_device(&pxa3xx_device_i2c_power, info);
}

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_i2s,
	&sa1100_device_rtc,
	&pxa_device_rtc,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa3xx_device_ssp4,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static struct sys_device pxa3xx_sysdev[] = {
	{
		.cls	= &pxa_irq_sysclass,
	}, {
		.cls	= &pxa3xx_mfp_sysclass,
	}, {
		.cls	= &pxa_gpio_sysclass,
	},
};

static int __init pxa3xx_init(void)
{
	int i, ret = 0;

	if (cpu_is_pxa3xx()) {

		reset_status = ARSR;

		/*
		 * clear RDH bit every time after reset
		 *
		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
		 * preserve them here in case they will be referenced later
		 */
		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);

		clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
			return ret;

		pxa3xx_init_pm();

		for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
			ret = sysdev_register(&pxa3xx_sysdev[i]);
			if (ret)
				pr_err("failed to register sysdev[%d]\n", i);
		}

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa3xx_init);
Commit	Line	Data
2c8086a5	1	/*
	2	* linux/arch/arm/mach-pxa/pxa3xx.c
	3	*
	4	* code specific to pxa3xx aka Monahans
	5	*
	6	* Copyright (C) 2006 Marvell International Ltd.
	7	*
e9bba8ee	8	* 2007-09-02: eric miao <eric.miao@marvell.com>
2c8086a5	9	* initial version
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/pm.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/irq.h>
7b5dea12	22	#include <linux/io.h>
c0165504	23	#include <linux/sysdev.h>
2c8086a5	24
a09e64fb	25	#include <mach/hardware.h>
a58fbcd8	26	#include <mach/gpio.h>
a09e64fb	27	#include <mach/pxa3xx-regs.h>
afd2fc02	28	#include <mach/reset.h>
a09e64fb RK	29	#include <mach/ohci.h>
	30	#include <mach/pm.h>
	31	#include <mach/dma.h>
	32	#include <mach/ssp.h>
bf293aec	33	#include <mach/regs-intc.h>
f0a83701	34	#include <plat/i2c.h>
2c8086a5	35
	36	#include "generic.h"
	37	#include "devices.h"
	38	#include "clock.h"
	39
	40	/* Crystal clock: 13MHz */
	41	#define BASE_CLK 13000000
	42
	43	/* Ring Oscillator Clock: 60MHz */
	44	#define RO_CLK 60000000
	45
	46	#define ACCR_D0CS (1 << 26)
c4d1fb62	47	#define ACCR_PCCE (1 << 11)
2c8086a5	48
bf293aec MR	49	#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
	50	#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
	51
2c8086a5	52	/* crystal frequency to static memory controller multiplier (SMCFS) */
	53	static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
	54
	55	/* crystal frequency to HSIO bus frequency multiplier (HSS) */
	56	static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
	57
	58	/*
	59	* Get the clock frequency as reflected by CCSR and the turbo flag.
	60	* We assume these values have been applied via a fcs.
	61	* If info is not 0 we also display the current settings.
	62	*/
	63	unsigned int pxa3xx_get_clk_frequency_khz(int info)
	64	{
	65	unsigned long acsr, xclkcfg;
	66	unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
	67
	68	/* Read XCLKCFG register turbo bit */
	69	__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
	70	t = xclkcfg & 0x1;
	71
	72	acsr = ACSR;
	73
	74	xl = acsr & 0x1f;
	75	xn = (acsr >> 8) & 0x7;
	76	hss = (acsr >> 14) & 0x3;
	77
	78	XL = xl * BASE_CLK;
	79	XN = xn * XL;
	80
	81	ro = acsr & ACCR_D0CS;
	82
	83	CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
	84	HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
	85
	86	if (info) {
	87	pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
	88	RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
	89	(ro) ? "" : "in");
	90	pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
	91	XL / 1000000, (XL % 1000000) / 10000, xl);
	92	pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
	93	XN / 1000000, (XN % 1000000) / 10000, xn,
	94	(t) ? "" : "in");
	95	pr_info("HSIO bus clock: %d.%02dMHz\n",
	96	HSS / 1000000, (HSS % 1000000) / 10000);
	97	}
	98
6232be32	99	return CLK / 1000;
2c8086a5	100	}
	101
	102	/*
	103	* Return the current static memory controller clock frequency
	104	* in units of 10kHz
	105	*/
	106	unsigned int pxa3xx_get_memclk_frequency_10khz(void)
	107	{
	108	unsigned long acsr;
	109	unsigned int smcfs, clk = 0;
	110
	111	acsr = ACSR;
	112
	113	smcfs = (acsr >> 23) & 0x7;
	114	clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
	115
	116	return (clk / 10000);
	117	}
	118
04fef228 EM	119	void pxa3xx_clear_reset_status(unsigned int mask)
	120	{
	121	/* RESET_STATUS_* has a 1:1 mapping with ARSR */
	122	ARSR = mask;
	123	}
	124
60bfe7fa MB	125	/*
	126	* Return the current AC97 clock frequency.
	127	*/
	128	static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
	129	{
	130	unsigned long rate = 312000000;
	131	unsigned long ac97_div;
	132
	133	ac97_div = AC97_DIV;
	134
	135	/* This may loose precision for some rates but won't for the
	136	* standard 24.576MHz.
	137	*/
	138	rate /= (ac97_div >> 12) & 0x7fff;
	139	rate *= (ac97_div & 0xfff);
	140
	141	return rate;
	142	}
	143
2c8086a5	144	/*
	145	* Return the current HSIO bus clock frequency
	146	*/
	147	static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
	148	{
	149	unsigned long acsr;
	150	unsigned int hss, hsio_clk;
	151
	152	acsr = ACSR;
	153
	154	hss = (acsr >> 14) & 0x3;
	155	hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
	156
	157	return hsio_clk;
	158	}
	159
7a2c5cb0	160	void clk_pxa3xx_cken_enable(struct clk *clk)
2c8086a5	161	{
	162	unsigned long mask = 1ul << (clk->cken & 0x1f);
	163
2c8086a5	164	if (clk->cken < 32)
	165	CKENA \|= mask;
	166	else
	167	CKENB \|= mask;
2c8086a5	168	}
2c8086a5	169
7a2c5cb0	170	void clk_pxa3xx_cken_disable(struct clk *clk)
2c8086a5	171	{
	172	unsigned long mask = 1ul << (clk->cken & 0x1f);
	173
2c8086a5	174	if (clk->cken < 32)
	175	CKENA &= ~mask;
	176	else
	177	CKENB &= ~mask;
2c8086a5	178	}
2c8086a5	179
7a2c5cb0	180	const struct clkops clk_pxa3xx_cken_ops = {
2a0d7187	181	.enable = clk_pxa3xx_cken_enable,
	182	.disable = clk_pxa3xx_cken_disable,
	183	};
	184
2c8086a5	185	static const struct clkops clk_pxa3xx_hsio_ops = {
	186	.enable = clk_pxa3xx_cken_enable,
	187	.disable = clk_pxa3xx_cken_disable,
	188	.getrate = clk_pxa3xx_hsio_getrate,
	189	};
	190
60bfe7fa MB	191	static const struct clkops clk_pxa3xx_ac97_ops = {
	192	.enable = clk_pxa3xx_cken_enable,
	193	.disable = clk_pxa3xx_cken_disable,
	194	.getrate = clk_pxa3xx_ac97_getrate,
	195	};
	196
dcc88a17 MB	197	static void clk_pout_enable(struct clk *clk)
	198	{
	199	OSCC \|= OSCC_PEN;
	200	}
	201
	202	static void clk_pout_disable(struct clk *clk)
	203	{
	204	OSCC &= ~OSCC_PEN;
	205	}
	206
	207	static const struct clkops clk_pout_ops = {
	208	.enable = clk_pout_enable,
	209	.disable = clk_pout_disable,
	210	};
	211
9ba63c4f MR	212	static void clk_dummy_enable(struct clk *clk)
	213	{
	214	}
	215
	216	static void clk_dummy_disable(struct clk *clk)
	217	{
	218	}
	219
	220	static const struct clkops clk_dummy_ops = {
	221	.enable = clk_dummy_enable,
	222	.disable = clk_dummy_disable,
	223	};
	224
8c3abc7d RK	225	static struct clk clk_pxa3xx_pout = {
	226	.ops = &clk_pout_ops,
	227	.rate = 13000000,
	228	.delay = 70,
	229	};
d8e0db11	230
8c3abc7d RK	231	static struct clk clk_dummy = {
	232	.ops = &clk_dummy_ops,
	233	};
fafc9d3f	234
8c3abc7d RK	235	static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
	236	static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
	237	static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
	238	static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
	239	static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
	240	static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
	241	static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
	242	static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
	243	static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
e68750ae	244	static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
8c3abc7d RK	245	static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
	246	static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
	247	static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
	248	static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
	249	static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
	250	static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
	251	static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
	252	static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
	253	static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
	254
	255	static struct clk_lookup pxa3xx_clkregs[] = {
	256	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	257	/* Power I2C clock is always on */
5c68b099	258	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
8c3abc7d RK	259	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	260	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	261	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	262	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	263	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	264	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	265	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	266	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	267	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	268	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
e68750ae	269	INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"),
8c3abc7d RK	270	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	271	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
	272	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
	273	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
	274	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
	275	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	276	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	277	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	278	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
2c8086a5	279	};
2c8086a5	280
7b5dea12	281	#ifdef CONFIG_PM
7b5dea12 RK	282
	283	#define ISRAM_START 0x5c000000
	284	#define ISRAM_SIZE SZ_256K
	285
	286	static void __iomem *sram;
	287	static unsigned long wakeup_src;
	288
c4d1fb62	289	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
c4d1fb62	290	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
7b5dea12	291
649de51b	292	enum { SLEEP_SAVE_CKENA,
c4d1fb62	293	SLEEP_SAVE_CKENB,
c4d1fb62	294	SLEEP_SAVE_ACCR,
7b5dea12	295
649de51b	296	SLEEP_SAVE_COUNT,
c4d1fb62	297	};
	298
	299	static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
	300	{
	301	SAVE(CKENA);
	302	SAVE(CKENB);
	303	SAVE(ACCR);
7b5dea12 RK	304	}
	305
	306	static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
	307	{
c4d1fb62	308	RESTORE(ACCR);
	309	RESTORE(CKENA);
	310	RESTORE(CKENB);
7b5dea12 RK	311	}
	312
	313	/*
	314	* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
	315	* memory controller has to be reinitialised, so we place some code
	316	* in the SRAM to perform this function.
	317	*
	318	* We disable FIQs across the standby - otherwise, we might receive a
	319	* FIQ while the SDRAM is unavailable.
	320	*/
	321	static void pxa3xx_cpu_standby(unsigned int pwrmode)
	322	{
	323	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	324	void (fn)(unsigned int) = (void __force )(sram + 0x8000);
	325
	326	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
	327	pm_enter_standby_end - pm_enter_standby_start);
	328
	329	AD2D0SR = ~0;
	330	AD2D1SR = ~0;
	331	AD2D0ER = wakeup_src;
	332	AD2D1ER = 0;
	333	ASCR = ASCR;
	334	ARSR = ARSR;
	335
	336	local_fiq_disable();
	337	fn(pwrmode);
	338	local_fiq_enable();
	339
	340	AD2D0ER = 0;
	341	AD2D1ER = 0;
7b5dea12 RK	342	}
7b5dea12 RK	343
c4d1fb62	344	/*
	345	* NOTE: currently, the OBM (OEM Boot Module) binary comes along with
	346	* PXA3xx development kits assumes that the resuming process continues
	347	* with the address stored within the first 4 bytes of SDRAM. The PSPR
	348	* register is used privately by BootROM and OBM, and _must_ be set to
	349	* 0x5c014000 for the moment.
	350	*/
	351	static void pxa3xx_cpu_pm_suspend(void)
	352	{
	353	volatile unsigned long p = (volatile void )0xc0000000;
	354	unsigned long saved_data = *p;
	355
	356	extern void pxa3xx_cpu_suspend(void);
	357	extern void pxa3xx_cpu_resume(void);
	358
	359	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	360	CKENA \|= (1 << CKEN_BOOT) \| (1 << CKEN_TPM);
	361	CKENB \|= 1 << (CKEN_HSIO2 & 0x1f);
	362
	363	/* clear and setup wakeup source */
	364	AD3SR = ~0;
	365	AD3ER = wakeup_src;
	366	ASCR = ASCR;
	367	ARSR = ARSR;
	368
	369	PCFR \|= (1u << 13); /* L1_DIS */
	370	PCFR &= ~((1u << 12) \| (1u << 1)); /* L0_EN \| SL_ROD */
	371
	372	PSPR = 0x5c014000;
	373
	374	/* overwrite with the resume address */
	375	*p = virt_to_phys(pxa3xx_cpu_resume);
	376
	377	pxa3xx_cpu_suspend();
	378
	379	*p = saved_data;
	380
	381	AD3ER = 0;
	382	}
	383
7b5dea12 RK	384	static void pxa3xx_cpu_pm_enter(suspend_state_t state)
	385	{
	386	/*
	387	* Don't sleep if no wakeup sources are defined
	388	*/
b86a5da8 MB	389	if (wakeup_src == 0) {
b86a5da8 MB	390	printk(KERN_ERR "Not suspending: no wakeup sources\n");
7b5dea12	391	return;
b86a5da8	392	}
7b5dea12 RK	393
	394	switch (state) {
	395	case PM_SUSPEND_STANDBY:
	396	pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
	397	break;
	398
	399	case PM_SUSPEND_MEM:
c4d1fb62	400	pxa3xx_cpu_pm_suspend();
7b5dea12 RK	401	break;
	402	}
	403	}
	404
	405	static int pxa3xx_cpu_pm_valid(suspend_state_t state)
	406	{
	407	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	408	}
	409
	410	static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
649de51b	411	.save_count = SLEEP_SAVE_COUNT,
7b5dea12 RK	412	.save = pxa3xx_cpu_pm_save,
	413	.restore = pxa3xx_cpu_pm_restore,
	414	.valid = pxa3xx_cpu_pm_valid,
	415	.enter = pxa3xx_cpu_pm_enter,
2c8086a5	416	};
2c8086a5	417
7b5dea12 RK	418	static void __init pxa3xx_init_pm(void)
	419	{
	420	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	421	if (!sram) {
	422	printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
	423	return;
	424	}
	425
	426	/*
	427	* Since we copy wakeup code into the SRAM, we need to ensure
	428	* that it is preserved over the low power modes. Note: bit 8
	429	* is undocumented in the developer manual, but must be set.
	430	*/
	431	AD1R \|= ADXR_L2 \| ADXR_R0;
	432	AD2R \|= ADXR_L2 \| ADXR_R0;
	433	AD3R \|= ADXR_L2 \| ADXR_R0;
	434
	435	/*
	436	* Clear the resume enable registers.
	437	*/
	438	AD1D0ER = 0;
	439	AD2D0ER = 0;
	440	AD2D1ER = 0;
	441	AD3ER = 0;
	442
	443	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
	444	}
	445
	446	static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
	447	{
	448	unsigned long flags, mask = 0;
	449
	450	switch (irq) {
	451	case IRQ_SSP3:
	452	mask = ADXER_MFP_WSSP3;
	453	break;
	454	case IRQ_MSL:
	455	mask = ADXER_WMSL0;
	456	break;
	457	case IRQ_USBH2:
	458	case IRQ_USBH1:
	459	mask = ADXER_WUSBH;
	460	break;
	461	case IRQ_KEYPAD:
	462	mask = ADXER_WKP;
	463	break;
	464	case IRQ_AC97:
	465	mask = ADXER_MFP_WAC97;
	466	break;
	467	case IRQ_USIM:
	468	mask = ADXER_WUSIM0;
	469	break;
	470	case IRQ_SSP2:
	471	mask = ADXER_MFP_WSSP2;
	472	break;
	473	case IRQ_I2C:
	474	mask = ADXER_MFP_WI2C;
	475	break;
	476	case IRQ_STUART:
	477	mask = ADXER_MFP_WUART3;
	478	break;
	479	case IRQ_BTUART:
	480	mask = ADXER_MFP_WUART2;
	481	break;
482	case IRQ_FFUART:
483	mask = ADXER_MFP_WUART1;
484	break;
485	case IRQ_MMC:
486	mask = ADXER_MFP_WMMC1;
487	break;
488	case IRQ_SSP:
489	mask = ADXER_MFP_WSSP1;
490	break;
491	case IRQ_RTCAlrm:
492	mask = ADXER_WRTC;
493	break;
494	case IRQ_SSP4:
495	mask = ADXER_MFP_WSSP4;
496	break;
497	case IRQ_TSI:
498	mask = ADXER_WTSI;
499	break;
500	case IRQ_USIM2:
501	mask = ADXER_WUSIM1;
502	break;
503	case IRQ_MMC2:
504	mask = ADXER_MFP_WMMC2;
505	break;
506	case IRQ_NAND:
507	mask = ADXER_MFP_WFLASH;
508	break;
509	case IRQ_USB2:
510	mask = ADXER_WUSB2;
511	break;
512	case IRQ_WAKEUP0:
513	mask = ADXER_WEXTWAKE0;
514	break;
515	case IRQ_WAKEUP1:
516	mask = ADXER_WEXTWAKE1;
517	break;
518	case IRQ_MMC3:
519	mask = ADXER_MFP_GEN12;
520	break;
e1217707 MB	521	default:
e1217707 MB	522	return -EINVAL;
7b5dea12 RK	523	}
	524
	525	local_irq_save(flags);
	526	if (on)
	527	wakeup_src \|= mask;
	528	else
	529	wakeup_src &= ~mask;
	530	local_irq_restore(flags);
	531
	532	return 0;
	533	}
7b5dea12 RK	534	#else
7b5dea12 RK	535	static inline void pxa3xx_init_pm(void) {}
b9e25ace	536	#define pxa3xx_set_wake NULL
7b5dea12 RK	537	#endif
7b5dea12 RK	538
bf293aec MR	539	static void pxa_ack_ext_wakeup(unsigned int irq)
	540	{
	541	PECR \|= PECR_IS(irq - IRQ_WAKEUP0);
	542	}
	543
	544	static void pxa_mask_ext_wakeup(unsigned int irq)
	545	{
	546	ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f));
	547	PECR &= ~PECR_IE(irq - IRQ_WAKEUP0);
	548	}
	549
	550	static void pxa_unmask_ext_wakeup(unsigned int irq)
	551	{
	552	ICMR2 \|= 1 << ((irq - PXA_IRQ(0)) & 0x1f);
	553	PECR \|= PECR_IE(irq - IRQ_WAKEUP0);
	554	}
	555
	556	static struct irq_chip pxa_ext_wakeup_chip = {
	557	.name = "WAKEUP",
	558	.ack = pxa_ack_ext_wakeup,
	559	.mask = pxa_mask_ext_wakeup,
	560	.unmask = pxa_unmask_ext_wakeup,
	561	};
	562
	563	static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
	564	{
	565	int irq;
	566
	567	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
	568	set_irq_chip(irq, &pxa_ext_wakeup_chip);
	569	set_irq_handler(irq, handle_edge_irq);
	570	set_irq_flags(irq, IRQF_VALID);
	571	}
	572
	573	pxa_ext_wakeup_chip.set_wake = fn;
	574	}
	575
2c8086a5	576	void __init pxa3xx_init_irq(void)
	577	{
	578	/* enable CP6 access */
	579	u32 value;
	580	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	581	value \|= (1 << 6);
	582	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
	583
b9e25ace	584	pxa_init_irq(56, pxa3xx_set_wake);
bf293aec	585	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
a58fbcd8	586	pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
2c8086a5	587	}
	588
	589	/*
	590	* device registration specific to PXA3xx.
	591	*/
	592
9ba63c4f MR	593	void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
9ba63c4f MR	594	{
14758220	595	pxa_register_device(&pxa3xx_device_i2c_power, info);
9ba63c4f MR	596	}
9ba63c4f MR	597
2c8086a5	598	static struct platform_device *devices[] __initdata = {
94c35a6b	599	&pxa27x_device_udc,
2c8086a5	600	&pxa_device_i2s,
72493146	601	&sa1100_device_rtc,
2c8086a5	602	&pxa_device_rtc,
d8e0db11	603	&pxa27x_device_ssp1,
	604	&pxa27x_device_ssp2,
	605	&pxa27x_device_ssp3,
	606	&pxa3xx_device_ssp4,
75540c1a	607	&pxa27x_device_pwm0,
75540c1a	608	&pxa27x_device_pwm1,
2c8086a5	609	};
2c8086a5	610
c0165504	611	static struct sys_device pxa3xx_sysdev[] = {
c0165504	612	{
c0165504	613	.cls = &pxa_irq_sysclass,
4be35e23	614	}, {
4be35e23	615	.cls = &pxa3xx_mfp_sysclass,
16dfdbf0	616	}, {
16dfdbf0	617	.cls = &pxa_gpio_sysclass,
c0165504	618	},
	619	};
	620
2c8086a5	621	static int __init pxa3xx_init(void)
2c8086a5	622	{
c0165504	623	int i, ret = 0;
2c8086a5	624
2c8086a5	625	if (cpu_is_pxa3xx()) {
04fef228 EM	626
	627	reset_status = ARSR;
	628
86260f98 DK	629	/*
	630	* clear RDH bit every time after reset
	631	*
	632	* Note: the last 3 bits DxS are write-1-to-clear so carefully
	633	* preserve them here in case they will be referenced later
	634	*/
	635	ASCR &= ~(ASCR_RDH \| ASCR_D1S \| ASCR_D2S \| ASCR_D3S);
	636
8c3abc7d	637	clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
2c8086a5	638
fef1f99a	639	if ((ret = pxa_init_dma(IRQ_DMA, 32)))
2c8086a5	640	return ret;
2c8086a5	641
7b5dea12 RK	642	pxa3xx_init_pm();
7b5dea12 RK	643
c0165504	644	for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
	645	ret = sysdev_register(&pxa3xx_sysdev[i]);
	646	if (ret)
	647	pr_err("failed to register sysdev[%d]\n", i);
	648	}
	649
	650	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
2c8086a5	651	}
c0165504	652
c0165504	653	return ret;
2c8086a5	654	}
2c8086a5	655
1c104e0e	656	postcore_initcall(pxa3xx_init);