[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-pxa / pxa3xx.c

/*
 * linux/arch/arm/mach-pxa/pxa3xx.c
 *
 * code specific to pxa3xx aka Monahans
 *
 * Copyright (C) 2006 Marvell International Ltd.
 *
 * 2007-09-02: eric miao <eric.miao@marvell.com>
 *             initial version
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
#include <linux/i2c/pxa-i2c.h>

#include <asm/mach/map.h>
#include <asm/suspend.h>
#include <mach/hardware.h>
#include <mach/pxa3xx-regs.h>
#include <mach/reset.h>
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/smemc.h>
#include <mach/irqs.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

#define PECR_IE(n)	((1 << ((n) * 2)) << 28)
#define PECR_IS(n)	((1 << ((n) * 2)) << 29)

extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));

static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0);

static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);

static struct clk_lookup pxa3xx_clkregs[] = {
	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	/* Power I2C clock is always on */
	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
	INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
	INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL),
	INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
};

#ifdef CONFIG_PM

#define ISRAM_START	0x5c000000
#define ISRAM_SIZE	SZ_256K

static void __iomem *sram;
static unsigned long wakeup_src;

/*
 * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 * memory controller has to be reinitialised, so we place some code
 * in the SRAM to perform this function.
 *
 * We disable FIQs across the standby - otherwise, we might receive a
 * FIQ while the SDRAM is unavailable.
 */
static void pxa3xx_cpu_standby(unsigned int pwrmode)
{
	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);

	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
		    pm_enter_standby_end - pm_enter_standby_start);

	AD2D0SR = ~0;
	AD2D1SR = ~0;
	AD2D0ER = wakeup_src;
	AD2D1ER = 0;
	ASCR = ASCR;
	ARSR = ARSR;

	local_fiq_disable();
	fn(pwrmode);
	local_fiq_enable();

	AD2D0ER = 0;
	AD2D1ER = 0;
}

/*
 * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 * PXA3xx development kits assumes that the resuming process continues
 * with the address stored within the first 4 bytes of SDRAM. The PSPR
 * register is used privately by BootROM and OBM, and _must_ be set to
 * 0x5c014000 for the moment.
 */
static void pxa3xx_cpu_pm_suspend(void)
{
	volatile unsigned long *p = (volatile void *)0xc0000000;
	unsigned long saved_data = *p;
#ifndef CONFIG_IWMMXT
	u64 acc0;

	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
#endif

	extern int pxa3xx_finish_suspend(unsigned long);

	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);

	/* clear and setup wakeup source */
	AD3SR = ~0;
	AD3ER = wakeup_src;
	ASCR = ASCR;
	ARSR = ARSR;

	PCFR |= (1u << 13);			/* L1_DIS */
	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */

	PSPR = 0x5c014000;

	/* overwrite with the resume address */
	*p = virt_to_phys(cpu_resume);

	cpu_suspend(0, pxa3xx_finish_suspend);

	*p = saved_data;

	AD3ER = 0;

#ifndef CONFIG_IWMMXT
	asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
#endif
}

static void pxa3xx_cpu_pm_enter(suspend_state_t state)
{
	/*
	 * Don't sleep if no wakeup sources are defined
	 */
	if (wakeup_src == 0) {
		printk(KERN_ERR "Not suspending: no wakeup sources\n");
		return;
	}

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
		break;

	case PM_SUSPEND_MEM:
		pxa3xx_cpu_pm_suspend();
		break;
	}
}

static int pxa3xx_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
	.valid		= pxa3xx_cpu_pm_valid,
	.enter		= pxa3xx_cpu_pm_enter,
};

static void __init pxa3xx_init_pm(void)
{
	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	if (!sram) {
		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
		return;
	}

	/*
	 * Since we copy wakeup code into the SRAM, we need to ensure
	 * that it is preserved over the low power modes.  Note: bit 8
	 * is undocumented in the developer manual, but must be set.
	 */
	AD1R |= ADXR_L2 | ADXR_R0;
	AD2R |= ADXR_L2 | ADXR_R0;
	AD3R |= ADXR_L2 | ADXR_R0;

	/*
	 * Clear the resume enable registers.
	 */
	AD1D0ER = 0;
	AD2D0ER = 0;
	AD2D1ER = 0;
	AD3ER = 0;

	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
}

static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
{
	unsigned long flags, mask = 0;

	switch (d->irq) {
	case IRQ_SSP3:
		mask = ADXER_MFP_WSSP3;
		break;
	case IRQ_MSL:
		mask = ADXER_WMSL0;
		break;
	case IRQ_USBH2:
	case IRQ_USBH1:
		mask = ADXER_WUSBH;
		break;
	case IRQ_KEYPAD:
		mask = ADXER_WKP;
		break;
	case IRQ_AC97:
		mask = ADXER_MFP_WAC97;
		break;
	case IRQ_USIM:
		mask = ADXER_WUSIM0;
		break;
	case IRQ_SSP2:
		mask = ADXER_MFP_WSSP2;
		break;
	case IRQ_I2C:
		mask = ADXER_MFP_WI2C;
		break;
	case IRQ_STUART:
		mask = ADXER_MFP_WUART3;
		break;
	case IRQ_BTUART:
		mask = ADXER_MFP_WUART2;
		break;
	case IRQ_FFUART:
		mask = ADXER_MFP_WUART1;
		break;
	case IRQ_MMC:
		mask = ADXER_MFP_WMMC1;
		break;
	case IRQ_SSP:
		mask = ADXER_MFP_WSSP1;
		break;
	case IRQ_RTCAlrm:
		mask = ADXER_WRTC;
		break;
	case IRQ_SSP4:
		mask = ADXER_MFP_WSSP4;
		break;
	case IRQ_TSI:
		mask = ADXER_WTSI;
		break;
	case IRQ_USIM2:
		mask = ADXER_WUSIM1;
		break;
	case IRQ_MMC2:
		mask = ADXER_MFP_WMMC2;
		break;
	case IRQ_NAND:
		mask = ADXER_MFP_WFLASH;
		break;
	case IRQ_USB2:
		mask = ADXER_WUSB2;
		break;
	case IRQ_WAKEUP0:
		mask = ADXER_WEXTWAKE0;
		break;
	case IRQ_WAKEUP1:
		mask = ADXER_WEXTWAKE1;
		break;
	case IRQ_MMC3:
		mask = ADXER_MFP_GEN12;
		break;
	default:
		return -EINVAL;
	}

	local_irq_save(flags);
	if (on)
		wakeup_src |= mask;
	else
		wakeup_src &= ~mask;
	local_irq_restore(flags);

	return 0;
}
#else
static inline void pxa3xx_init_pm(void) {}
#define pxa3xx_set_wake	NULL
#endif

static void pxa_ack_ext_wakeup(struct irq_data *d)
{
	PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
}

static void pxa_mask_ext_wakeup(struct irq_data *d)
{
	pxa_mask_irq(d);
	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
}

static void pxa_unmask_ext_wakeup(struct irq_data *d)
{
	pxa_unmask_irq(d);
	PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
}

static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
{
	if (flow_type & IRQ_TYPE_EDGE_RISING)
		PWER |= 1 << (d->irq - IRQ_WAKEUP0);

	if (flow_type & IRQ_TYPE_EDGE_FALLING)
		PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);

	return 0;
}

static struct irq_chip pxa_ext_wakeup_chip = {
	.name		= "WAKEUP",
	.irq_ack	= pxa_ack_ext_wakeup,
	.irq_mask	= pxa_mask_ext_wakeup,
	.irq_unmask	= pxa_unmask_ext_wakeup,
	.irq_set_type	= pxa_set_ext_wakeup_type,
};

static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
					   unsigned int))
{
	int irq;

	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
		irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
					 handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	pxa_ext_wakeup_chip.irq_set_wake = fn;
}

static void __init __pxa3xx_init_irq(void)
{
	/* enable CP6 access */
	u32 value;
	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	value |= (1 << 6);
	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));

	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
}

void __init pxa3xx_init_irq(void)
{
	__pxa3xx_init_irq();
	pxa_init_irq(56, pxa3xx_set_wake);
}

void __init pxa3xx_dt_init_irq(void)
{
	__pxa3xx_init_irq();
	pxa_dt_irq_init(pxa3xx_set_wake);
}

static struct map_desc pxa3xx_io_desc[] __initdata = {
	{	/* Mem Ctl */
		.virtual	= (unsigned long)SMEMC_VIRT,
		.pfn		= __phys_to_pfn(PXA3XX_SMEMC_BASE),
		.length		= 0x00200000,
		.type		= MT_DEVICE
	}
};

void __init pxa3xx_map_io(void)
{
	pxa_map_io();
	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
	pxa3xx_get_clk_frequency_khz(1);
}

/*
 * device registration specific to PXA3xx.
 */

void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	pxa_register_device(&pxa3xx_device_i2c_power, info);
}

static struct platform_device *devices[] __initdata = {
	&pxa_device_gpio,
	&pxa27x_device_udc,
	&pxa_device_pmu,
	&pxa_device_i2s,
	&pxa_device_asoc_ssp1,
	&pxa_device_asoc_ssp2,
	&pxa_device_asoc_ssp3,
	&pxa_device_asoc_ssp4,
	&pxa_device_asoc_platform,
	&sa1100_device_rtc,
	&pxa_device_rtc,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa3xx_device_ssp4,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static int __init pxa3xx_init(void)
{
	int ret = 0;

	if (cpu_is_pxa3xx()) {

		reset_status = ARSR;

		/*
		 * clear RDH bit every time after reset
		 *
		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
		 * preserve them here in case they will be referenced later
		 */
		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);

		clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
			return ret;

		pxa3xx_init_pm();

		register_syscore_ops(&pxa_irq_syscore_ops);
		register_syscore_ops(&pxa3xx_mfp_syscore_ops);
		register_syscore_ops(&pxa3xx_clock_syscore_ops);

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa3xx_init);
Commit	Line	Data
2c8086a5	1	/*
	2	* linux/arch/arm/mach-pxa/pxa3xx.c
	3	*
	4	* code specific to pxa3xx aka Monahans
	5	*
	6	* Copyright (C) 2006 Marvell International Ltd.
	7	*
e9bba8ee	8	* 2007-09-02: eric miao <eric.miao@marvell.com>
2c8086a5	9	* initial version
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
2c8086a5	15	#include <linux/module.h>
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
	18	#include <linux/pm.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/irq.h>
7b5dea12	21	#include <linux/io.h>
2eaa03b5	22	#include <linux/syscore_ops.h>
b459396e	23	#include <linux/i2c/pxa-i2c.h>
2c8086a5	24
851982c1	25	#include <asm/mach/map.h>
2c74a0ce	26	#include <asm/suspend.h>
a09e64fb RK	27	#include <mach/hardware.h>
a09e64fb RK	28	#include <mach/pxa3xx-regs.h>
afd2fc02	29	#include <mach/reset.h>
a09e64fb RK	30	#include <mach/ohci.h>
	31	#include <mach/pm.h>
	32	#include <mach/dma.h>
ad68bb9f	33	#include <mach/smemc.h>
4e611091	34	#include <mach/irqs.h>
2c8086a5	35
	36	#include "generic.h"
	37	#include "devices.h"
	38	#include "clock.h"
	39
bf293aec MR	40	#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
	41	#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
	42
089d0362 DM	43	extern void __init pxa_dt_irq_init(int (fn)(struct irq_data , unsigned int));
089d0362 DM	44
8c3abc7d RK	45	static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
	46	static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
	47	static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
	48	static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
	49	static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
	50	static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
e68750ae	51	static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
8c3abc7d RK	52	static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
	53	static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
	54	static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
	55	static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
	56	static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
	57	static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
	58	static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
	59	static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
	60	static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
389eda15	61	static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0);
8c3abc7d	62
2e8581e7	63	static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
c085052b	64	static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
2e8581e7 EM	65	static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
2e8581e7 EM	66	static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
4029813c	67	static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
2e8581e7	68
8c3abc7d RK	69	static struct clk_lookup pxa3xx_clkregs[] = {
	70	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	71	/* Power I2C clock is always on */
5c68b099	72	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
8c3abc7d RK	73	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	74	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	75	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	76	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	77	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	78	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	79	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	80	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	81	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	82	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
69f22be7	83	INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
8c3abc7d RK	84	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	85	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
	86	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
	87	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
	88	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
	89	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	90	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	91	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	92	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
c085052b	93	INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
389eda15	94	INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL),
3e12ec77	95	INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
2c8086a5	96	};
2c8086a5	97
7b5dea12	98	#ifdef CONFIG_PM
7b5dea12 RK	99
	100	#define ISRAM_START 0x5c000000
	101	#define ISRAM_SIZE SZ_256K
	102
	103	static void __iomem *sram;
	104	static unsigned long wakeup_src;
	105
7b5dea12 RK	106	/*
	107	* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
	108	* memory controller has to be reinitialised, so we place some code
	109	* in the SRAM to perform this function.
	110	*
	111	* We disable FIQs across the standby - otherwise, we might receive a
	112	* FIQ while the SDRAM is unavailable.
	113	*/
	114	static void pxa3xx_cpu_standby(unsigned int pwrmode)
	115	{
	116	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	117	void (fn)(unsigned int) = (void __force )(sram + 0x8000);
	118
	119	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
	120	pm_enter_standby_end - pm_enter_standby_start);
	121
	122	AD2D0SR = ~0;
	123	AD2D1SR = ~0;
	124	AD2D0ER = wakeup_src;
	125	AD2D1ER = 0;
	126	ASCR = ASCR;
	127	ARSR = ARSR;
	128
	129	local_fiq_disable();
	130	fn(pwrmode);
	131	local_fiq_enable();
	132
	133	AD2D0ER = 0;
	134	AD2D1ER = 0;
7b5dea12 RK	135	}
7b5dea12 RK	136
c4d1fb62	137	/*
	138	* NOTE: currently, the OBM (OEM Boot Module) binary comes along with
	139	* PXA3xx development kits assumes that the resuming process continues
	140	* with the address stored within the first 4 bytes of SDRAM. The PSPR
	141	* register is used privately by BootROM and OBM, and _must_ be set to
	142	* 0x5c014000 for the moment.
	143	*/
	144	static void pxa3xx_cpu_pm_suspend(void)
	145	{
	146	volatile unsigned long p = (volatile void )0xc0000000;
	147	unsigned long saved_data = *p;
a9503d21 RK	148	#ifndef CONFIG_IWMMXT
a9503d21 RK	149	u64 acc0;
c4d1fb62	150
a9503d21 RK	151	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
	152	#endif
	153
29cb3cd2	154	extern int pxa3xx_finish_suspend(unsigned long);
c4d1fb62	155
	156	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	157	CKENA \|= (1 << CKEN_BOOT) \| (1 << CKEN_TPM);
	158	CKENB \|= 1 << (CKEN_HSIO2 & 0x1f);
	159
	160	/* clear and setup wakeup source */
	161	AD3SR = ~0;
	162	AD3ER = wakeup_src;
	163	ASCR = ASCR;
	164	ARSR = ARSR;
	165
	166	PCFR \|= (1u << 13); /* L1_DIS */
	167	PCFR &= ~((1u << 12) \| (1u << 1)); /* L0_EN \| SL_ROD */
	168
	169	PSPR = 0x5c014000;
	170
	171	/* overwrite with the resume address */
4f5ad99b	172	*p = virt_to_phys(cpu_resume);
c4d1fb62	173
2c74a0ce	174	cpu_suspend(0, pxa3xx_finish_suspend);
c4d1fb62	175
	176	*p = saved_data;
	177
	178	AD3ER = 0;
a9503d21 RK	179
	180	#ifndef CONFIG_IWMMXT
	181	asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
	182	#endif
c4d1fb62	183	}
c4d1fb62	184
7b5dea12 RK	185	static void pxa3xx_cpu_pm_enter(suspend_state_t state)
	186	{
	187	/*
	188	* Don't sleep if no wakeup sources are defined
	189	*/
b86a5da8 MB	190	if (wakeup_src == 0) {
b86a5da8 MB	191	printk(KERN_ERR "Not suspending: no wakeup sources\n");
7b5dea12	192	return;
b86a5da8	193	}
7b5dea12 RK	194
	195	switch (state) {
	196	case PM_SUSPEND_STANDBY:
	197	pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
	198	break;
	199
	200	case PM_SUSPEND_MEM:
c4d1fb62	201	pxa3xx_cpu_pm_suspend();
7b5dea12 RK	202	break;
	203	}
	204	}
	205
	206	static int pxa3xx_cpu_pm_valid(suspend_state_t state)
	207	{
	208	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	209	}
	210
	211	static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
7b5dea12 RK	212	.valid = pxa3xx_cpu_pm_valid,
7b5dea12 RK	213	.enter = pxa3xx_cpu_pm_enter,
2c8086a5	214	};
2c8086a5	215
7b5dea12 RK	216	static void __init pxa3xx_init_pm(void)
	217	{
	218	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	219	if (!sram) {
	220	printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
	221	return;
	222	}
	223
	224	/*
	225	* Since we copy wakeup code into the SRAM, we need to ensure
	226	* that it is preserved over the low power modes. Note: bit 8
	227	* is undocumented in the developer manual, but must be set.
	228	*/
	229	AD1R \|= ADXR_L2 \| ADXR_R0;
	230	AD2R \|= ADXR_L2 \| ADXR_R0;
	231	AD3R \|= ADXR_L2 \| ADXR_R0;
	232
	233	/*
	234	* Clear the resume enable registers.
	235	*/
	236	AD1D0ER = 0;
	237	AD2D0ER = 0;
	238	AD2D1ER = 0;
	239	AD3ER = 0;
	240
	241	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
	242	}
	243
a3f4c927	244	static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
7b5dea12 RK	245	{
	246	unsigned long flags, mask = 0;
	247
a3f4c927	248	switch (d->irq) {
7b5dea12 RK	249	case IRQ_SSP3:
	250	mask = ADXER_MFP_WSSP3;
	251	break;
	252	case IRQ_MSL:
	253	mask = ADXER_WMSL0;
	254	break;
	255	case IRQ_USBH2:
	256	case IRQ_USBH1:
	257	mask = ADXER_WUSBH;
	258	break;
	259	case IRQ_KEYPAD:
	260	mask = ADXER_WKP;
	261	break;
	262	case IRQ_AC97:
	263	mask = ADXER_MFP_WAC97;
	264	break;
	265	case IRQ_USIM:
	266	mask = ADXER_WUSIM0;
	267	break;
	268	case IRQ_SSP2:
	269	mask = ADXER_MFP_WSSP2;
	270	break;
	271	case IRQ_I2C:
	272	mask = ADXER_MFP_WI2C;
	273	break;
	274	case IRQ_STUART:
	275	mask = ADXER_MFP_WUART3;
	276	break;
	277	case IRQ_BTUART:
	278	mask = ADXER_MFP_WUART2;
	279	break;
	280	case IRQ_FFUART:
	281	mask = ADXER_MFP_WUART1;
	282	break;
	283	case IRQ_MMC:
	284	mask = ADXER_MFP_WMMC1;
	285	break;
	286	case IRQ_SSP:
	287	mask = ADXER_MFP_WSSP1;
	288	break;
	289	case IRQ_RTCAlrm:
	290	mask = ADXER_WRTC;
	291	break;
	292	case IRQ_SSP4:
	293	mask = ADXER_MFP_WSSP4;
	294	break;
	295	case IRQ_TSI:
	296	mask = ADXER_WTSI;
	297	break;
	298	case IRQ_USIM2:
	299	mask = ADXER_WUSIM1;
	300	break;
	301	case IRQ_MMC2:
	302	mask = ADXER_MFP_WMMC2;
	303	break;
	304	case IRQ_NAND:
	305	mask = ADXER_MFP_WFLASH;
	306	break;
	307	case IRQ_USB2:
	308	mask = ADXER_WUSB2;
	309	break;
	310	case IRQ_WAKEUP0:
	311	mask = ADXER_WEXTWAKE0;
	312	break;
313	case IRQ_WAKEUP1:
314	mask = ADXER_WEXTWAKE1;
315	break;
316	case IRQ_MMC3:
317	mask = ADXER_MFP_GEN12;
318	break;
e1217707 MB	319	default:
e1217707 MB	320	return -EINVAL;
7b5dea12 RK	321	}
	322
	323	local_irq_save(flags);
	324	if (on)
	325	wakeup_src \|= mask;
	326	else
	327	wakeup_src &= ~mask;
	328	local_irq_restore(flags);
	329
	330	return 0;
	331	}
7b5dea12 RK	332	#else
7b5dea12 RK	333	static inline void pxa3xx_init_pm(void) {}
b9e25ace	334	#define pxa3xx_set_wake NULL
7b5dea12 RK	335	#endif
7b5dea12 RK	336
a3f4c927	337	static void pxa_ack_ext_wakeup(struct irq_data *d)
bf293aec	338	{
a3f4c927	339	PECR \|= PECR_IS(d->irq - IRQ_WAKEUP0);
bf293aec MR	340	}
bf293aec MR	341
a3f4c927	342	static void pxa_mask_ext_wakeup(struct irq_data *d)
bf293aec	343	{
5d284e35	344	pxa_mask_irq(d);
a3f4c927	345	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
bf293aec MR	346	}
bf293aec MR	347
a3f4c927	348	static void pxa_unmask_ext_wakeup(struct irq_data *d)
bf293aec	349	{
5d284e35	350	pxa_unmask_irq(d);
a3f4c927	351	PECR \|= PECR_IE(d->irq - IRQ_WAKEUP0);
bf293aec MR	352	}
bf293aec MR	353
a3f4c927	354	static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
12882096 IG	355	{
12882096 IG	356	if (flow_type & IRQ_TYPE_EDGE_RISING)
a3f4c927	357	PWER \|= 1 << (d->irq - IRQ_WAKEUP0);
12882096 IG	358
12882096 IG	359	if (flow_type & IRQ_TYPE_EDGE_FALLING)
a3f4c927	360	PWER \|= 1 << (d->irq - IRQ_WAKEUP0 + 2);
12882096 IG	361
	362	return 0;
	363	}
	364
bf293aec MR	365	static struct irq_chip pxa_ext_wakeup_chip = {
bf293aec MR	366	.name = "WAKEUP",
a3f4c927 LB	367	.irq_ack = pxa_ack_ext_wakeup,
	368	.irq_mask = pxa_mask_ext_wakeup,
	369	.irq_unmask = pxa_unmask_ext_wakeup,
	370	.irq_set_type = pxa_set_ext_wakeup_type,
bf293aec MR	371	};
bf293aec MR	372
157d2644 HZ	373	static void __init pxa_init_ext_wakeup_irq(int (fn)(struct irq_data ,
157d2644 HZ	374	unsigned int))
bf293aec MR	375	{
	376	int irq;
	377
	378	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
f38c02f3 TG	379	irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
f38c02f3 TG	380	handle_edge_irq);
bf293aec MR	381	set_irq_flags(irq, IRQF_VALID);
	382	}
	383
a3f4c927	384	pxa_ext_wakeup_chip.irq_set_wake = fn;
bf293aec MR	385	}
bf293aec MR	386
089d0362	387	static void __init __pxa3xx_init_irq(void)
2c8086a5	388	{
	389	/* enable CP6 access */
	390	u32 value;
	391	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	392	value \|= (1 << 6);
	393	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
	394
bf293aec	395	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
2c8086a5	396	}
2c8086a5	397
089d0362 DM	398	void __init pxa3xx_init_irq(void)
	399	{
	400	__pxa3xx_init_irq();
	401	pxa_init_irq(56, pxa3xx_set_wake);
	402	}
	403
	404	void __init pxa3xx_dt_init_irq(void)
	405	{
	406	__pxa3xx_init_irq();
	407	pxa_dt_irq_init(pxa3xx_set_wake);
	408	}
	409
851982c1 MV	410	static struct map_desc pxa3xx_io_desc[] __initdata = {
851982c1 MV	411	{ /* Mem Ctl */
97b09da4	412	.virtual = (unsigned long)SMEMC_VIRT,
ad68bb9f	413	.pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
851982c1 MV	414	.length = 0x00200000,
	415	.type = MT_DEVICE
	416	}
	417	};
	418
	419	void __init pxa3xx_map_io(void)
	420	{
	421	pxa_map_io();
	422	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
	423	pxa3xx_get_clk_frequency_khz(1);
	424	}
	425
2c8086a5	426	/*
	427	* device registration specific to PXA3xx.
	428	*/
	429
9ba63c4f MR	430	void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
9ba63c4f MR	431	{
14758220	432	pxa_register_device(&pxa3xx_device_i2c_power, info);
9ba63c4f MR	433	}
9ba63c4f MR	434
2c8086a5	435	static struct platform_device *devices[] __initdata = {
157d2644	436	&pxa_device_gpio,
94c35a6b	437	&pxa27x_device_udc,
09a5358d	438	&pxa_device_pmu,
2c8086a5	439	&pxa_device_i2s,
f0fba2ad LG	440	&pxa_device_asoc_ssp1,
	441	&pxa_device_asoc_ssp2,
	442	&pxa_device_asoc_ssp3,
	443	&pxa_device_asoc_ssp4,
	444	&pxa_device_asoc_platform,
72493146	445	&sa1100_device_rtc,
2c8086a5	446	&pxa_device_rtc,
d8e0db11	447	&pxa27x_device_ssp1,
	448	&pxa27x_device_ssp2,
	449	&pxa27x_device_ssp3,
	450	&pxa3xx_device_ssp4,
75540c1a	451	&pxa27x_device_pwm0,
75540c1a	452	&pxa27x_device_pwm1,
2c8086a5	453	};
	454
	455	static int __init pxa3xx_init(void)
	456	{
2eaa03b5	457	int ret = 0;
2c8086a5	458
2c8086a5	459	if (cpu_is_pxa3xx()) {
04fef228 EM	460
	461	reset_status = ARSR;
	462
86260f98 DK	463	/*
	464	* clear RDH bit every time after reset
	465	*
	466	* Note: the last 3 bits DxS are write-1-to-clear so carefully
	467	* preserve them here in case they will be referenced later
	468	*/
	469	ASCR &= ~(ASCR_RDH \| ASCR_D1S \| ASCR_D2S \| ASCR_D3S);
	470
0a0300dc	471	clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
2c8086a5	472
fef1f99a	473	if ((ret = pxa_init_dma(IRQ_DMA, 32)))
2c8086a5	474	return ret;
2c8086a5	475
7b5dea12 RK	476	pxa3xx_init_pm();
7b5dea12 RK	477
2eaa03b5 RW	478	register_syscore_ops(&pxa_irq_syscore_ops);
2eaa03b5 RW	479	register_syscore_ops(&pxa3xx_mfp_syscore_ops);
2eaa03b5	480	register_syscore_ops(&pxa3xx_clock_syscore_ops);
c0165504	481
c0165504	482	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
2c8086a5	483	}
c0165504	484
c0165504	485	return ret;
2c8086a5	486	}
2c8086a5	487
1c104e0e	488	postcore_initcall(pxa3xx_init);