[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-pxa / pxa3xx.c

/*
 * linux/arch/arm/mach-pxa/pxa3xx.c
 *
 * code specific to pxa3xx aka Monahans
 *
 * Copyright (C) 2006 Marvell International Ltd.
 *
 * 2007-09-02: eric miao <eric.miao@marvell.com>
 *             initial version
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sysdev.h>

#include <mach/hardware.h>
#include <mach/gpio.h>
#include <mach/pxa3xx-regs.h>
#include <mach/reset.h>
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/ssp.h>
#include <plat/i2c.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/* Ring Oscillator Clock: 60MHz */
#define RO_CLK		60000000

#define ACCR_D0CS	(1 << 26)
#define ACCR_PCCE	(1 << 11)

/* crystal frequency to static memory controller multiplier (SMCFS) */
static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };

/* crystal frequency to HSIO bus frequency multiplier (HSS) */
static unsigned char hss_mult[4] = { 8, 12, 16, 0 };

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa3xx_get_clk_frequency_khz(int info)
{
	unsigned long acsr, xclkcfg;
	unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;

	/* Read XCLKCFG register turbo bit */
	__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
	t = xclkcfg & 0x1;

	acsr = ACSR;

	xl  = acsr & 0x1f;
	xn  = (acsr >> 8) & 0x7;
	hss = (acsr >> 14) & 0x3;

	XL = xl * BASE_CLK;
	XN = xn * XL;

	ro = acsr & ACCR_D0CS;

	CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
	HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;

	if (info) {
		pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
			RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
			(ro) ? "" : "in");
		pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
			XL / 1000000, (XL % 1000000) / 10000, xl);
		pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
			XN / 1000000, (XN % 1000000) / 10000, xn,
			(t) ? "" : "in");
		pr_info("HSIO bus clock: %d.%02dMHz\n",
			HSS / 1000000, (HSS % 1000000) / 10000);
	}

	return CLK / 1000;
}

/*
 * Return the current static memory controller clock frequency
 * in units of 10kHz
 */
unsigned int pxa3xx_get_memclk_frequency_10khz(void)
{
	unsigned long acsr;
	unsigned int smcfs, clk = 0;

	acsr = ACSR;

	smcfs = (acsr >> 23) & 0x7;
	clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;

	return (clk / 10000);
}

void pxa3xx_clear_reset_status(unsigned int mask)
{
	/* RESET_STATUS_* has a 1:1 mapping with ARSR */
	ARSR = mask;
}

/*
 * Return the current AC97 clock frequency.
 */
static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
{
	unsigned long rate = 312000000;
	unsigned long ac97_div;

	ac97_div = AC97_DIV;

	/* This may loose precision for some rates but won't for the
	 * standard 24.576MHz.
	 */
	rate /= (ac97_div >> 12) & 0x7fff;
	rate *= (ac97_div & 0xfff);

	return rate;
}

/*
 * Return the current HSIO bus clock frequency
 */
static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
{
	unsigned long acsr;
	unsigned int hss, hsio_clk;

	acsr = ACSR;

	hss = (acsr >> 14) & 0x3;
	hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;

	return hsio_clk;
}

void clk_pxa3xx_cken_enable(struct clk *clk)
{
	unsigned long mask = 1ul << (clk->cken & 0x1f);

	if (clk->cken < 32)
		CKENA |= mask;
	else
		CKENB |= mask;
}

void clk_pxa3xx_cken_disable(struct clk *clk)
{
	unsigned long mask = 1ul << (clk->cken & 0x1f);

	if (clk->cken < 32)
		CKENA &= ~mask;
	else
		CKENB &= ~mask;
}

const struct clkops clk_pxa3xx_cken_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
};

static const struct clkops clk_pxa3xx_hsio_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
	.getrate	= clk_pxa3xx_hsio_getrate,
};

static const struct clkops clk_pxa3xx_ac97_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
	.getrate	= clk_pxa3xx_ac97_getrate,
};

static void clk_pout_enable(struct clk *clk)
{
	OSCC |= OSCC_PEN;
}

static void clk_pout_disable(struct clk *clk)
{
	OSCC &= ~OSCC_PEN;
}

static const struct clkops clk_pout_ops = {
	.enable		= clk_pout_enable,
	.disable	= clk_pout_disable,
};

static void clk_dummy_enable(struct clk *clk)
{
}

static void clk_dummy_disable(struct clk *clk)
{
}

static const struct clkops clk_dummy_ops = {
	.enable		= clk_dummy_enable,
	.disable	= clk_dummy_disable,
};

static struct clk clk_pxa3xx_pout = {
	.ops		= &clk_pout_ops,
	.rate		= 13000000,
	.delay		= 70,
};

static struct clk clk_dummy = {
	.ops		= &clk_dummy_ops,
};

static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);

static struct clk_lookup pxa3xx_clkregs[] = {
	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	/* Power I2C clock is always on */
	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
	INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"),
	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
};

#ifdef CONFIG_PM

#define ISRAM_START	0x5c000000
#define ISRAM_SIZE	SZ_256K

static void __iomem *sram;
static unsigned long wakeup_src;

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

enum {	SLEEP_SAVE_CKENA,
	SLEEP_SAVE_CKENB,
	SLEEP_SAVE_ACCR,

	SLEEP_SAVE_COUNT,
};

static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(CKENA);
	SAVE(CKENB);
	SAVE(ACCR);
}

static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
{
	RESTORE(ACCR);
	RESTORE(CKENA);
	RESTORE(CKENB);
}

/*
 * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 * memory controller has to be reinitialised, so we place some code
 * in the SRAM to perform this function.
 *
 * We disable FIQs across the standby - otherwise, we might receive a
 * FIQ while the SDRAM is unavailable.
 */
static void pxa3xx_cpu_standby(unsigned int pwrmode)
{
	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);

	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
		    pm_enter_standby_end - pm_enter_standby_start);

	AD2D0SR = ~0;
	AD2D1SR = ~0;
	AD2D0ER = wakeup_src;
	AD2D1ER = 0;
	ASCR = ASCR;
	ARSR = ARSR;

	local_fiq_disable();
	fn(pwrmode);
	local_fiq_enable();

	AD2D0ER = 0;
	AD2D1ER = 0;
}

/*
 * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 * PXA3xx development kits assumes that the resuming process continues
 * with the address stored within the first 4 bytes of SDRAM. The PSPR
 * register is used privately by BootROM and OBM, and _must_ be set to
 * 0x5c014000 for the moment.
 */
static void pxa3xx_cpu_pm_suspend(void)
{
	volatile unsigned long *p = (volatile void *)0xc0000000;
	unsigned long saved_data = *p;

	extern void pxa3xx_cpu_suspend(void);
	extern void pxa3xx_cpu_resume(void);

	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);

	/* clear and setup wakeup source */
	AD3SR = ~0;
	AD3ER = wakeup_src;
	ASCR = ASCR;
	ARSR = ARSR;

	PCFR |= (1u << 13);			/* L1_DIS */
	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */

	PSPR = 0x5c014000;

	/* overwrite with the resume address */
	*p = virt_to_phys(pxa3xx_cpu_resume);

	pxa3xx_cpu_suspend();

	*p = saved_data;

	AD3ER = 0;
}

static void pxa3xx_cpu_pm_enter(suspend_state_t state)
{
	/*
	 * Don't sleep if no wakeup sources are defined
	 */
	if (wakeup_src == 0) {
		printk(KERN_ERR "Not suspending: no wakeup sources\n");
		return;
	}

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
		break;

	case PM_SUSPEND_MEM:
		pxa3xx_cpu_pm_suspend();
		break;
	}
}

static int pxa3xx_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.save		= pxa3xx_cpu_pm_save,
	.restore	= pxa3xx_cpu_pm_restore,
	.valid		= pxa3xx_cpu_pm_valid,
	.enter		= pxa3xx_cpu_pm_enter,
};

static void __init pxa3xx_init_pm(void)
{
	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	if (!sram) {
		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
		return;
	}

	/*
	 * Since we copy wakeup code into the SRAM, we need to ensure
	 * that it is preserved over the low power modes.  Note: bit 8
	 * is undocumented in the developer manual, but must be set.
	 */
	AD1R |= ADXR_L2 | ADXR_R0;
	AD2R |= ADXR_L2 | ADXR_R0;
	AD3R |= ADXR_L2 | ADXR_R0;

	/*
	 * Clear the resume enable registers.
	 */
	AD1D0ER = 0;
	AD2D0ER = 0;
	AD2D1ER = 0;
	AD3ER = 0;

	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
}

static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
{
	unsigned long flags, mask = 0;

	switch (irq) {
	case IRQ_SSP3:
		mask = ADXER_MFP_WSSP3;
		break;
	case IRQ_MSL:
		mask = ADXER_WMSL0;
		break;
	case IRQ_USBH2:
	case IRQ_USBH1:
		mask = ADXER_WUSBH;
		break;
	case IRQ_KEYPAD:
		mask = ADXER_WKP;
		break;
	case IRQ_AC97:
		mask = ADXER_MFP_WAC97;
		break;
	case IRQ_USIM:
		mask = ADXER_WUSIM0;
		break;
	case IRQ_SSP2:
		mask = ADXER_MFP_WSSP2;
		break;
	case IRQ_I2C:
		mask = ADXER_MFP_WI2C;
		break;
	case IRQ_STUART:
		mask = ADXER_MFP_WUART3;
		break;
	case IRQ_BTUART:
		mask = ADXER_MFP_WUART2;
		break;
	case IRQ_FFUART:
		mask = ADXER_MFP_WUART1;
		break;
	case IRQ_MMC:
		mask = ADXER_MFP_WMMC1;
		break;
	case IRQ_SSP:
		mask = ADXER_MFP_WSSP1;
		break;
	case IRQ_RTCAlrm:
		mask = ADXER_WRTC;
		break;
	case IRQ_SSP4:
		mask = ADXER_MFP_WSSP4;
		break;
	case IRQ_TSI:
		mask = ADXER_WTSI;
		break;
	case IRQ_USIM2:
		mask = ADXER_WUSIM1;
		break;
	case IRQ_MMC2:
		mask = ADXER_MFP_WMMC2;
		break;
	case IRQ_NAND:
		mask = ADXER_MFP_WFLASH;
		break;
	case IRQ_USB2:
		mask = ADXER_WUSB2;
		break;
	case IRQ_WAKEUP0:
		mask = ADXER_WEXTWAKE0;
		break;
	case IRQ_WAKEUP1:
		mask = ADXER_WEXTWAKE1;
		break;
	case IRQ_MMC3:
		mask = ADXER_MFP_GEN12;
		break;
	default:
		return -EINVAL;
	}

	local_irq_save(flags);
	if (on)
		wakeup_src |= mask;
	else
		wakeup_src &= ~mask;
	local_irq_restore(flags);

	return 0;
}
#else
static inline void pxa3xx_init_pm(void) {}
#define pxa3xx_set_wake	NULL
#endif

void __init pxa3xx_init_irq(void)
{
	/* enable CP6 access */
	u32 value;
	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	value |= (1 << 6);
	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));

	pxa_init_irq(56, pxa3xx_set_wake);
	pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
}

/*
 * device registration specific to PXA3xx.
 */

void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	pxa_register_device(&pxa3xx_device_i2c_power, info);
}

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_i2s,
	&sa1100_device_rtc,
	&pxa_device_rtc,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa3xx_device_ssp4,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static struct sys_device pxa3xx_sysdev[] = {
	{
		.cls	= &pxa_irq_sysclass,
	}, {
		.cls	= &pxa3xx_mfp_sysclass,
	}, {
		.cls	= &pxa_gpio_sysclass,
	},
};

static int __init pxa3xx_init(void)
{
	int i, ret = 0;

	if (cpu_is_pxa3xx()) {

		reset_status = ARSR;

		/*
		 * clear RDH bit every time after reset
		 *
		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
		 * preserve them here in case they will be referenced later
		 */
		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);

		clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
			return ret;

		pxa3xx_init_pm();

		for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
			ret = sysdev_register(&pxa3xx_sysdev[i]);
			if (ret)
				pr_err("failed to register sysdev[%d]\n", i);
		}

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa3xx_init);
Commit	Line	Data
2c8086a5	1	/*
	2	* linux/arch/arm/mach-pxa/pxa3xx.c
	3	*
	4	* code specific to pxa3xx aka Monahans
	5	*
	6	* Copyright (C) 2006 Marvell International Ltd.
	7	*
e9bba8ee	8	* 2007-09-02: eric miao <eric.miao@marvell.com>
2c8086a5	9	* initial version
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/pm.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/irq.h>
7b5dea12	22	#include <linux/io.h>
c0165504	23	#include <linux/sysdev.h>
2c8086a5	24
a09e64fb	25	#include <mach/hardware.h>
a58fbcd8	26	#include <mach/gpio.h>
a09e64fb	27	#include <mach/pxa3xx-regs.h>
afd2fc02	28	#include <mach/reset.h>
a09e64fb RK	29	#include <mach/ohci.h>
	30	#include <mach/pm.h>
	31	#include <mach/dma.h>
	32	#include <mach/ssp.h>
f0a83701	33	#include <plat/i2c.h>
2c8086a5	34
	35	#include "generic.h"
	36	#include "devices.h"
	37	#include "clock.h"
	38
	39	/* Crystal clock: 13MHz */
	40	#define BASE_CLK 13000000
	41
	42	/* Ring Oscillator Clock: 60MHz */
	43	#define RO_CLK 60000000
	44
	45	#define ACCR_D0CS (1 << 26)
c4d1fb62	46	#define ACCR_PCCE (1 << 11)
2c8086a5	47
	48	/* crystal frequency to static memory controller multiplier (SMCFS) */
	49	static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
	50
	51	/* crystal frequency to HSIO bus frequency multiplier (HSS) */
	52	static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
	53
	54	/*
	55	* Get the clock frequency as reflected by CCSR and the turbo flag.
	56	* We assume these values have been applied via a fcs.
	57	* If info is not 0 we also display the current settings.
	58	*/
	59	unsigned int pxa3xx_get_clk_frequency_khz(int info)
	60	{
	61	unsigned long acsr, xclkcfg;
	62	unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
	63
	64	/* Read XCLKCFG register turbo bit */
	65	__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
	66	t = xclkcfg & 0x1;
	67
	68	acsr = ACSR;
	69
	70	xl = acsr & 0x1f;
	71	xn = (acsr >> 8) & 0x7;
	72	hss = (acsr >> 14) & 0x3;
	73
	74	XL = xl * BASE_CLK;
	75	XN = xn * XL;
	76
	77	ro = acsr & ACCR_D0CS;
	78
	79	CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
	80	HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
	81
	82	if (info) {
	83	pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
	84	RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
	85	(ro) ? "" : "in");
	86	pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
	87	XL / 1000000, (XL % 1000000) / 10000, xl);
	88	pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
	89	XN / 1000000, (XN % 1000000) / 10000, xn,
	90	(t) ? "" : "in");
	91	pr_info("HSIO bus clock: %d.%02dMHz\n",
	92	HSS / 1000000, (HSS % 1000000) / 10000);
	93	}
	94
6232be32	95	return CLK / 1000;
2c8086a5	96	}
	97
	98	/*
	99	* Return the current static memory controller clock frequency
	100	* in units of 10kHz
	101	*/
	102	unsigned int pxa3xx_get_memclk_frequency_10khz(void)
	103	{
	104	unsigned long acsr;
	105	unsigned int smcfs, clk = 0;
	106
	107	acsr = ACSR;
	108
	109	smcfs = (acsr >> 23) & 0x7;
	110	clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
	111
	112	return (clk / 10000);
	113	}
	114
04fef228 EM	115	void pxa3xx_clear_reset_status(unsigned int mask)
	116	{
	117	/* RESET_STATUS_* has a 1:1 mapping with ARSR */
	118	ARSR = mask;
	119	}
	120
60bfe7fa MB	121	/*
	122	* Return the current AC97 clock frequency.
	123	*/
	124	static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
	125	{
	126	unsigned long rate = 312000000;
	127	unsigned long ac97_div;
	128
	129	ac97_div = AC97_DIV;
	130
	131	/* This may loose precision for some rates but won't for the
	132	* standard 24.576MHz.
	133	*/
	134	rate /= (ac97_div >> 12) & 0x7fff;
	135	rate *= (ac97_div & 0xfff);
	136
	137	return rate;
	138	}
	139
2c8086a5	140	/*
	141	* Return the current HSIO bus clock frequency
	142	*/
	143	static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
	144	{
	145	unsigned long acsr;
	146	unsigned int hss, hsio_clk;
	147
	148	acsr = ACSR;
	149
	150	hss = (acsr >> 14) & 0x3;
	151	hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
	152
	153	return hsio_clk;
	154	}
	155
7a2c5cb0	156	void clk_pxa3xx_cken_enable(struct clk *clk)
2c8086a5	157	{
	158	unsigned long mask = 1ul << (clk->cken & 0x1f);
	159
2c8086a5	160	if (clk->cken < 32)
	161	CKENA \|= mask;
	162	else
	163	CKENB \|= mask;
2c8086a5	164	}
2c8086a5	165
7a2c5cb0	166	void clk_pxa3xx_cken_disable(struct clk *clk)
2c8086a5	167	{
	168	unsigned long mask = 1ul << (clk->cken & 0x1f);
	169
2c8086a5	170	if (clk->cken < 32)
	171	CKENA &= ~mask;
	172	else
	173	CKENB &= ~mask;
2c8086a5	174	}
2c8086a5	175
7a2c5cb0	176	const struct clkops clk_pxa3xx_cken_ops = {
2a0d7187	177	.enable = clk_pxa3xx_cken_enable,
	178	.disable = clk_pxa3xx_cken_disable,
	179	};
	180
2c8086a5	181	static const struct clkops clk_pxa3xx_hsio_ops = {
	182	.enable = clk_pxa3xx_cken_enable,
	183	.disable = clk_pxa3xx_cken_disable,
	184	.getrate = clk_pxa3xx_hsio_getrate,
	185	};
	186
60bfe7fa MB	187	static const struct clkops clk_pxa3xx_ac97_ops = {
	188	.enable = clk_pxa3xx_cken_enable,
	189	.disable = clk_pxa3xx_cken_disable,
	190	.getrate = clk_pxa3xx_ac97_getrate,
	191	};
	192
dcc88a17 MB	193	static void clk_pout_enable(struct clk *clk)
	194	{
	195	OSCC \|= OSCC_PEN;
	196	}
	197
	198	static void clk_pout_disable(struct clk *clk)
	199	{
	200	OSCC &= ~OSCC_PEN;
	201	}
	202
	203	static const struct clkops clk_pout_ops = {
	204	.enable = clk_pout_enable,
	205	.disable = clk_pout_disable,
	206	};
	207
9ba63c4f MR	208	static void clk_dummy_enable(struct clk *clk)
	209	{
	210	}
	211
	212	static void clk_dummy_disable(struct clk *clk)
	213	{
	214	}
	215
	216	static const struct clkops clk_dummy_ops = {
	217	.enable = clk_dummy_enable,
	218	.disable = clk_dummy_disable,
	219	};
	220
8c3abc7d RK	221	static struct clk clk_pxa3xx_pout = {
	222	.ops = &clk_pout_ops,
	223	.rate = 13000000,
	224	.delay = 70,
	225	};
d8e0db11	226
8c3abc7d RK	227	static struct clk clk_dummy = {
	228	.ops = &clk_dummy_ops,
	229	};
fafc9d3f	230
8c3abc7d RK	231	static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
	232	static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
	233	static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
	234	static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
	235	static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
	236	static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
	237	static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
	238	static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
	239	static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
e68750ae	240	static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
8c3abc7d RK	241	static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
	242	static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
	243	static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
	244	static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
	245	static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
	246	static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
	247	static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
	248	static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
	249	static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
	250
	251	static struct clk_lookup pxa3xx_clkregs[] = {
	252	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	253	/* Power I2C clock is always on */
5c68b099	254	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
8c3abc7d RK	255	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	256	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	257	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	258	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	259	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	260	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	261	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	262	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	263	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	264	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
e68750ae	265	INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"),
8c3abc7d RK	266	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	267	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
	268	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
	269	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
	270	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
	271	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	272	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	273	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	274	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
2c8086a5	275	};
2c8086a5	276
7b5dea12	277	#ifdef CONFIG_PM
7b5dea12 RK	278
	279	#define ISRAM_START 0x5c000000
	280	#define ISRAM_SIZE SZ_256K
	281
	282	static void __iomem *sram;
	283	static unsigned long wakeup_src;
	284
c4d1fb62	285	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
c4d1fb62	286	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
7b5dea12	287
649de51b	288	enum { SLEEP_SAVE_CKENA,
c4d1fb62	289	SLEEP_SAVE_CKENB,
c4d1fb62	290	SLEEP_SAVE_ACCR,
7b5dea12	291
649de51b	292	SLEEP_SAVE_COUNT,
c4d1fb62	293	};
	294
	295	static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
	296	{
	297	SAVE(CKENA);
	298	SAVE(CKENB);
	299	SAVE(ACCR);
7b5dea12 RK	300	}
	301
	302	static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
	303	{
c4d1fb62	304	RESTORE(ACCR);
	305	RESTORE(CKENA);
	306	RESTORE(CKENB);
7b5dea12 RK	307	}
	308
	309	/*
	310	* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
	311	* memory controller has to be reinitialised, so we place some code
	312	* in the SRAM to perform this function.
	313	*
	314	* We disable FIQs across the standby - otherwise, we might receive a
	315	* FIQ while the SDRAM is unavailable.
	316	*/
	317	static void pxa3xx_cpu_standby(unsigned int pwrmode)
	318	{
	319	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	320	void (fn)(unsigned int) = (void __force )(sram + 0x8000);
	321
	322	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
	323	pm_enter_standby_end - pm_enter_standby_start);
	324
	325	AD2D0SR = ~0;
	326	AD2D1SR = ~0;
	327	AD2D0ER = wakeup_src;
	328	AD2D1ER = 0;
	329	ASCR = ASCR;
	330	ARSR = ARSR;
	331
	332	local_fiq_disable();
	333	fn(pwrmode);
	334	local_fiq_enable();
	335
	336	AD2D0ER = 0;
	337	AD2D1ER = 0;
7b5dea12 RK	338	}
7b5dea12 RK	339
c4d1fb62	340	/*
	341	* NOTE: currently, the OBM (OEM Boot Module) binary comes along with
	342	* PXA3xx development kits assumes that the resuming process continues
	343	* with the address stored within the first 4 bytes of SDRAM. The PSPR
	344	* register is used privately by BootROM and OBM, and _must_ be set to
	345	* 0x5c014000 for the moment.
	346	*/
	347	static void pxa3xx_cpu_pm_suspend(void)
	348	{
	349	volatile unsigned long p = (volatile void )0xc0000000;
	350	unsigned long saved_data = *p;
	351
	352	extern void pxa3xx_cpu_suspend(void);
	353	extern void pxa3xx_cpu_resume(void);
	354
	355	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	356	CKENA \|= (1 << CKEN_BOOT) \| (1 << CKEN_TPM);
	357	CKENB \|= 1 << (CKEN_HSIO2 & 0x1f);
	358
	359	/* clear and setup wakeup source */
	360	AD3SR = ~0;
	361	AD3ER = wakeup_src;
	362	ASCR = ASCR;
	363	ARSR = ARSR;
	364
	365	PCFR \|= (1u << 13); /* L1_DIS */
	366	PCFR &= ~((1u << 12) \| (1u << 1)); /* L0_EN \| SL_ROD */
	367
	368	PSPR = 0x5c014000;
	369
	370	/* overwrite with the resume address */
	371	*p = virt_to_phys(pxa3xx_cpu_resume);
	372
	373	pxa3xx_cpu_suspend();
	374
	375	*p = saved_data;
	376
	377	AD3ER = 0;
	378	}
	379
7b5dea12 RK	380	static void pxa3xx_cpu_pm_enter(suspend_state_t state)
	381	{
	382	/*
	383	* Don't sleep if no wakeup sources are defined
	384	*/
b86a5da8 MB	385	if (wakeup_src == 0) {
b86a5da8 MB	386	printk(KERN_ERR "Not suspending: no wakeup sources\n");
7b5dea12	387	return;
b86a5da8	388	}
7b5dea12 RK	389
	390	switch (state) {
	391	case PM_SUSPEND_STANDBY:
	392	pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
	393	break;
	394
	395	case PM_SUSPEND_MEM:
c4d1fb62	396	pxa3xx_cpu_pm_suspend();
7b5dea12 RK	397	break;
	398	}
	399	}
	400
	401	static int pxa3xx_cpu_pm_valid(suspend_state_t state)
	402	{
	403	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	404	}
	405
	406	static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
649de51b	407	.save_count = SLEEP_SAVE_COUNT,
7b5dea12 RK	408	.save = pxa3xx_cpu_pm_save,
	409	.restore = pxa3xx_cpu_pm_restore,
	410	.valid = pxa3xx_cpu_pm_valid,
	411	.enter = pxa3xx_cpu_pm_enter,
2c8086a5	412	};
2c8086a5	413
7b5dea12 RK	414	static void __init pxa3xx_init_pm(void)
	415	{
	416	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	417	if (!sram) {
	418	printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
	419	return;
	420	}
	421
	422	/*
	423	* Since we copy wakeup code into the SRAM, we need to ensure
	424	* that it is preserved over the low power modes. Note: bit 8
	425	* is undocumented in the developer manual, but must be set.
	426	*/
	427	AD1R \|= ADXR_L2 \| ADXR_R0;
	428	AD2R \|= ADXR_L2 \| ADXR_R0;
	429	AD3R \|= ADXR_L2 \| ADXR_R0;
	430
	431	/*
	432	* Clear the resume enable registers.
	433	*/
	434	AD1D0ER = 0;
	435	AD2D0ER = 0;
	436	AD2D1ER = 0;
	437	AD3ER = 0;
	438
	439	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
	440	}
	441
	442	static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
	443	{
	444	unsigned long flags, mask = 0;
	445
	446	switch (irq) {
	447	case IRQ_SSP3:
	448	mask = ADXER_MFP_WSSP3;
	449	break;
	450	case IRQ_MSL:
	451	mask = ADXER_WMSL0;
	452	break;
	453	case IRQ_USBH2:
	454	case IRQ_USBH1:
	455	mask = ADXER_WUSBH;
	456	break;
	457	case IRQ_KEYPAD:
	458	mask = ADXER_WKP;
	459	break;
	460	case IRQ_AC97:
	461	mask = ADXER_MFP_WAC97;
	462	break;
	463	case IRQ_USIM:
	464	mask = ADXER_WUSIM0;
	465	break;
	466	case IRQ_SSP2:
	467	mask = ADXER_MFP_WSSP2;
	468	break;
	469	case IRQ_I2C:
	470	mask = ADXER_MFP_WI2C;
	471	break;
	472	case IRQ_STUART:
	473	mask = ADXER_MFP_WUART3;
	474	break;
	475	case IRQ_BTUART:
	476	mask = ADXER_MFP_WUART2;
	477	break;
478	case IRQ_FFUART:
479	mask = ADXER_MFP_WUART1;
480	break;
481	case IRQ_MMC:
482	mask = ADXER_MFP_WMMC1;
483	break;
484	case IRQ_SSP:
485	mask = ADXER_MFP_WSSP1;
486	break;
487	case IRQ_RTCAlrm:
488	mask = ADXER_WRTC;
489	break;
490	case IRQ_SSP4:
491	mask = ADXER_MFP_WSSP4;
492	break;
493	case IRQ_TSI:
494	mask = ADXER_WTSI;
495	break;
496	case IRQ_USIM2:
497	mask = ADXER_WUSIM1;
498	break;
499	case IRQ_MMC2:
500	mask = ADXER_MFP_WMMC2;
501	break;
502	case IRQ_NAND:
503	mask = ADXER_MFP_WFLASH;
504	break;
505	case IRQ_USB2:
506	mask = ADXER_WUSB2;
507	break;
508	case IRQ_WAKEUP0:
509	mask = ADXER_WEXTWAKE0;
510	break;
511	case IRQ_WAKEUP1:
512	mask = ADXER_WEXTWAKE1;
513	break;
514	case IRQ_MMC3:
515	mask = ADXER_MFP_GEN12;
516	break;
e1217707 MB	517	default:
e1217707 MB	518	return -EINVAL;
7b5dea12 RK	519	}
	520
	521	local_irq_save(flags);
	522	if (on)
	523	wakeup_src \|= mask;
	524	else
	525	wakeup_src &= ~mask;
	526	local_irq_restore(flags);
	527
	528	return 0;
	529	}
7b5dea12 RK	530	#else
7b5dea12 RK	531	static inline void pxa3xx_init_pm(void) {}
b9e25ace	532	#define pxa3xx_set_wake NULL
7b5dea12 RK	533	#endif
7b5dea12 RK	534
2c8086a5	535	void __init pxa3xx_init_irq(void)
	536	{
	537	/* enable CP6 access */
	538	u32 value;
	539	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	540	value \|= (1 << 6);
	541	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
	542
b9e25ace	543	pxa_init_irq(56, pxa3xx_set_wake);
a58fbcd8	544	pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
2c8086a5	545	}
	546
	547	/*
	548	* device registration specific to PXA3xx.
	549	*/
	550
9ba63c4f MR	551	void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
9ba63c4f MR	552	{
14758220	553	pxa_register_device(&pxa3xx_device_i2c_power, info);
9ba63c4f MR	554	}
9ba63c4f MR	555
2c8086a5	556	static struct platform_device *devices[] __initdata = {
94c35a6b	557	&pxa27x_device_udc,
2c8086a5	558	&pxa_device_i2s,
72493146	559	&sa1100_device_rtc,
2c8086a5	560	&pxa_device_rtc,
d8e0db11	561	&pxa27x_device_ssp1,
	562	&pxa27x_device_ssp2,
	563	&pxa27x_device_ssp3,
	564	&pxa3xx_device_ssp4,
75540c1a	565	&pxa27x_device_pwm0,
75540c1a	566	&pxa27x_device_pwm1,
2c8086a5	567	};
2c8086a5	568
c0165504	569	static struct sys_device pxa3xx_sysdev[] = {
c0165504	570	{
c0165504	571	.cls = &pxa_irq_sysclass,
4be35e23	572	}, {
4be35e23	573	.cls = &pxa3xx_mfp_sysclass,
16dfdbf0	574	}, {
16dfdbf0	575	.cls = &pxa_gpio_sysclass,
c0165504	576	},
	577	};
	578
2c8086a5	579	static int __init pxa3xx_init(void)
2c8086a5	580	{
c0165504	581	int i, ret = 0;
2c8086a5	582
2c8086a5	583	if (cpu_is_pxa3xx()) {
04fef228 EM	584
	585	reset_status = ARSR;
	586
86260f98 DK	587	/*
	588	* clear RDH bit every time after reset
	589	*
	590	* Note: the last 3 bits DxS are write-1-to-clear so carefully
	591	* preserve them here in case they will be referenced later
	592	*/
	593	ASCR &= ~(ASCR_RDH \| ASCR_D1S \| ASCR_D2S \| ASCR_D3S);
	594
8c3abc7d	595	clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
2c8086a5	596
fef1f99a	597	if ((ret = pxa_init_dma(IRQ_DMA, 32)))
2c8086a5	598	return ret;
2c8086a5	599
7b5dea12 RK	600	pxa3xx_init_pm();
7b5dea12 RK	601
c0165504	602	for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
	603	ret = sysdev_register(&pxa3xx_sysdev[i]);
	604	if (ret)
	605	pr_err("failed to register sysdev[%d]\n", i);
	606	}
	607
	608	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
2c8086a5	609	}
c0165504	610
c0165504	611	return ret;
2c8086a5	612	}
2c8086a5	613
1c104e0e	614	postcore_initcall(pxa3xx_init);