[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-pxa / pxa3xx.c

/*
 * linux/arch/arm/mach-pxa/pxa3xx.c
 *
 * code specific to pxa3xx aka Monahans
 *
 * Copyright (C) 2006 Marvell International Ltd.
 *
 * 2007-09-02: eric miao <eric.miao@marvell.com>
 *             initial version
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sysdev.h>

#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
#include <mach/pxa3xx-regs.h>
#include <mach/reset.h>
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/regs-intc.h>
#include <mach/smemc.h>
#include <plat/i2c.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/* Ring Oscillator Clock: 60MHz */
#define RO_CLK		60000000

#define ACCR_D0CS	(1 << 26)
#define ACCR_PCCE	(1 << 11)

#define PECR_IE(n)	((1 << ((n) * 2)) << 28)
#define PECR_IS(n)	((1 << ((n) * 2)) << 29)

/* crystal frequency to static memory controller multiplier (SMCFS) */
static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };

/* crystal frequency to HSIO bus frequency multiplier (HSS) */
static unsigned char hss_mult[4] = { 8, 12, 16, 24 };

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa3xx_get_clk_frequency_khz(int info)
{
	unsigned long acsr, xclkcfg;
	unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;

	/* Read XCLKCFG register turbo bit */
	__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
	t = xclkcfg & 0x1;

	acsr = ACSR;

	xl  = acsr & 0x1f;
	xn  = (acsr >> 8) & 0x7;
	hss = (acsr >> 14) & 0x3;

	XL = xl * BASE_CLK;
	XN = xn * XL;

	ro = acsr & ACCR_D0CS;

	CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
	HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;

	if (info) {
		pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
			RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
			(ro) ? "" : "in");
		pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
			XL / 1000000, (XL % 1000000) / 10000, xl);
		pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
			XN / 1000000, (XN % 1000000) / 10000, xn,
			(t) ? "" : "in");
		pr_info("HSIO bus clock: %d.%02dMHz\n",
			HSS / 1000000, (HSS % 1000000) / 10000);
	}

	return CLK / 1000;
}

void pxa3xx_clear_reset_status(unsigned int mask)
{
	/* RESET_STATUS_* has a 1:1 mapping with ARSR */
	ARSR = mask;
}

/*
 * Return the current AC97 clock frequency.
 */
static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
{
	unsigned long rate = 312000000;
	unsigned long ac97_div;

	ac97_div = AC97_DIV;

	/* This may loose precision for some rates but won't for the
	 * standard 24.576MHz.
	 */
	rate /= (ac97_div >> 12) & 0x7fff;
	rate *= (ac97_div & 0xfff);

	return rate;
}

/*
 * Return the current HSIO bus clock frequency
 */
static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
{
	unsigned long acsr;
	unsigned int hss, hsio_clk;

	acsr = ACSR;

	hss = (acsr >> 14) & 0x3;
	hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;

	return hsio_clk;
}

void clk_pxa3xx_cken_enable(struct clk *clk)
{
	unsigned long mask = 1ul << (clk->cken & 0x1f);

	if (clk->cken < 32)
		CKENA |= mask;
	else
		CKENB |= mask;
}

void clk_pxa3xx_cken_disable(struct clk *clk)
{
	unsigned long mask = 1ul << (clk->cken & 0x1f);

	if (clk->cken < 32)
		CKENA &= ~mask;
	else
		CKENB &= ~mask;
}

const struct clkops clk_pxa3xx_cken_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
};

static const struct clkops clk_pxa3xx_hsio_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
	.getrate	= clk_pxa3xx_hsio_getrate,
};

static const struct clkops clk_pxa3xx_ac97_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
	.getrate	= clk_pxa3xx_ac97_getrate,
};

static void clk_pout_enable(struct clk *clk)
{
	OSCC |= OSCC_PEN;
}

static void clk_pout_disable(struct clk *clk)
{
	OSCC &= ~OSCC_PEN;
}

static const struct clkops clk_pout_ops = {
	.enable		= clk_pout_enable,
	.disable	= clk_pout_disable,
};

static void clk_dummy_enable(struct clk *clk)
{
}

static void clk_dummy_disable(struct clk *clk)
{
}

static const struct clkops clk_dummy_ops = {
	.enable		= clk_dummy_enable,
	.disable	= clk_dummy_disable,
};

static struct clk clk_pxa3xx_pout = {
	.ops		= &clk_pout_ops,
	.rate		= 13000000,
	.delay		= 70,
};

static struct clk clk_dummy = {
	.ops		= &clk_dummy_ops,
};

static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);

static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);

static struct clk_lookup pxa3xx_clkregs[] = {
	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	/* Power I2C clock is always on */
	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
	INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
};

#ifdef CONFIG_PM

#define ISRAM_START	0x5c000000
#define ISRAM_SIZE	SZ_256K

static void __iomem *sram;
static unsigned long wakeup_src;

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

enum {	SLEEP_SAVE_CKENA,
	SLEEP_SAVE_CKENB,
	SLEEP_SAVE_ACCR,

	SLEEP_SAVE_COUNT,
};

static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(CKENA);
	SAVE(CKENB);
	SAVE(ACCR);
}

static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
{
	RESTORE(ACCR);
	RESTORE(CKENA);
	RESTORE(CKENB);
}

/*
 * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 * memory controller has to be reinitialised, so we place some code
 * in the SRAM to perform this function.
 *
 * We disable FIQs across the standby - otherwise, we might receive a
 * FIQ while the SDRAM is unavailable.
 */
static void pxa3xx_cpu_standby(unsigned int pwrmode)
{
	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);

	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
		    pm_enter_standby_end - pm_enter_standby_start);

	AD2D0SR = ~0;
	AD2D1SR = ~0;
	AD2D0ER = wakeup_src;
	AD2D1ER = 0;
	ASCR = ASCR;
	ARSR = ARSR;

	local_fiq_disable();
	fn(pwrmode);
	local_fiq_enable();

	AD2D0ER = 0;
	AD2D1ER = 0;
}

/*
 * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 * PXA3xx development kits assumes that the resuming process continues
 * with the address stored within the first 4 bytes of SDRAM. The PSPR
 * register is used privately by BootROM and OBM, and _must_ be set to
 * 0x5c014000 for the moment.
 */
static void pxa3xx_cpu_pm_suspend(void)
{
	volatile unsigned long *p = (volatile void *)0xc0000000;
	unsigned long saved_data = *p;

	extern void pxa3xx_cpu_suspend(void);
	extern void pxa3xx_cpu_resume(void);

	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);

	/* clear and setup wakeup source */
	AD3SR = ~0;
	AD3ER = wakeup_src;
	ASCR = ASCR;
	ARSR = ARSR;

	PCFR |= (1u << 13);			/* L1_DIS */
	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */

	PSPR = 0x5c014000;

	/* overwrite with the resume address */
	*p = virt_to_phys(pxa3xx_cpu_resume);

	pxa3xx_cpu_suspend();

	*p = saved_data;

	AD3ER = 0;
}

static void pxa3xx_cpu_pm_enter(suspend_state_t state)
{
	/*
	 * Don't sleep if no wakeup sources are defined
	 */
	if (wakeup_src == 0) {
		printk(KERN_ERR "Not suspending: no wakeup sources\n");
		return;
	}

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
		break;

	case PM_SUSPEND_MEM:
		pxa3xx_cpu_pm_suspend();
		break;
	}
}

static int pxa3xx_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.save		= pxa3xx_cpu_pm_save,
	.restore	= pxa3xx_cpu_pm_restore,
	.valid		= pxa3xx_cpu_pm_valid,
	.enter		= pxa3xx_cpu_pm_enter,
};

static void __init pxa3xx_init_pm(void)
{
	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	if (!sram) {
		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
		return;
	}

	/*
	 * Since we copy wakeup code into the SRAM, we need to ensure
	 * that it is preserved over the low power modes.  Note: bit 8
	 * is undocumented in the developer manual, but must be set.
	 */
	AD1R |= ADXR_L2 | ADXR_R0;
	AD2R |= ADXR_L2 | ADXR_R0;
	AD3R |= ADXR_L2 | ADXR_R0;

	/*
	 * Clear the resume enable registers.
	 */
	AD1D0ER = 0;
	AD2D0ER = 0;
	AD2D1ER = 0;
	AD3ER = 0;

	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
}

static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
{
	unsigned long flags, mask = 0;

	switch (irq) {
	case IRQ_SSP3:
		mask = ADXER_MFP_WSSP3;
		break;
	case IRQ_MSL:
		mask = ADXER_WMSL0;
		break;
	case IRQ_USBH2:
	case IRQ_USBH1:
		mask = ADXER_WUSBH;
		break;
	case IRQ_KEYPAD:
		mask = ADXER_WKP;
		break;
	case IRQ_AC97:
		mask = ADXER_MFP_WAC97;
		break;
	case IRQ_USIM:
		mask = ADXER_WUSIM0;
		break;
	case IRQ_SSP2:
		mask = ADXER_MFP_WSSP2;
		break;
	case IRQ_I2C:
		mask = ADXER_MFP_WI2C;
		break;
	case IRQ_STUART:
		mask = ADXER_MFP_WUART3;
		break;
	case IRQ_BTUART:
		mask = ADXER_MFP_WUART2;
		break;
	case IRQ_FFUART:
		mask = ADXER_MFP_WUART1;
		break;
	case IRQ_MMC:
		mask = ADXER_MFP_WMMC1;
		break;
	case IRQ_SSP:
		mask = ADXER_MFP_WSSP1;
		break;
	case IRQ_RTCAlrm:
		mask = ADXER_WRTC;
		break;
	case IRQ_SSP4:
		mask = ADXER_MFP_WSSP4;
		break;
	case IRQ_TSI:
		mask = ADXER_WTSI;
		break;
	case IRQ_USIM2:
		mask = ADXER_WUSIM1;
		break;
	case IRQ_MMC2:
		mask = ADXER_MFP_WMMC2;
		break;
	case IRQ_NAND:
		mask = ADXER_MFP_WFLASH;
		break;
	case IRQ_USB2:
		mask = ADXER_WUSB2;
		break;
	case IRQ_WAKEUP0:
		mask = ADXER_WEXTWAKE0;
		break;
	case IRQ_WAKEUP1:
		mask = ADXER_WEXTWAKE1;
		break;
	case IRQ_MMC3:
		mask = ADXER_MFP_GEN12;
		break;
	default:
		return -EINVAL;
	}

	local_irq_save(flags);
	if (on)
		wakeup_src |= mask;
	else
		wakeup_src &= ~mask;
	local_irq_restore(flags);

	return 0;
}
#else
static inline void pxa3xx_init_pm(void) {}
#define pxa3xx_set_wake	NULL
#endif

static void pxa_ack_ext_wakeup(unsigned int irq)
{
	PECR |= PECR_IS(irq - IRQ_WAKEUP0);
}

static void pxa_mask_ext_wakeup(unsigned int irq)
{
	ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f));
	PECR &= ~PECR_IE(irq - IRQ_WAKEUP0);
}

static void pxa_unmask_ext_wakeup(unsigned int irq)
{
	ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f);
	PECR |= PECR_IE(irq - IRQ_WAKEUP0);
}

static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type)
{
	if (flow_type & IRQ_TYPE_EDGE_RISING)
		PWER |= 1 << (irq - IRQ_WAKEUP0);

	if (flow_type & IRQ_TYPE_EDGE_FALLING)
		PWER |= 1 << (irq - IRQ_WAKEUP0 + 2);

	return 0;
}

static struct irq_chip pxa_ext_wakeup_chip = {
	.name		= "WAKEUP",
	.ack		= pxa_ack_ext_wakeup,
	.mask		= pxa_mask_ext_wakeup,
	.unmask		= pxa_unmask_ext_wakeup,
	.set_type	= pxa_set_ext_wakeup_type,
};

static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
{
	int irq;

	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
		set_irq_chip(irq, &pxa_ext_wakeup_chip);
		set_irq_handler(irq, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	pxa_ext_wakeup_chip.set_wake = fn;
}

void __init pxa3xx_init_irq(void)
{
	/* enable CP6 access */
	u32 value;
	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	value |= (1 << 6);
	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));

	pxa_init_irq(56, pxa3xx_set_wake);
	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
	pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
}

static struct map_desc pxa3xx_io_desc[] __initdata = {
	{	/* Mem Ctl */
		.virtual	= SMEMC_VIRT,
		.pfn		= __phys_to_pfn(PXA3XX_SMEMC_BASE),
		.length		= 0x00200000,
		.type		= MT_DEVICE
	}
};

void __init pxa3xx_map_io(void)
{
	pxa_map_io();
	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
	pxa3xx_get_clk_frequency_khz(1);
}

/*
 * device registration specific to PXA3xx.
 */

void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	pxa_register_device(&pxa3xx_device_i2c_power, info);
}

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_pmu,
	&pxa_device_i2s,
	&pxa_device_asoc_ssp1,
	&pxa_device_asoc_ssp2,
	&pxa_device_asoc_ssp3,
	&pxa_device_asoc_ssp4,
	&pxa_device_asoc_platform,
	&sa1100_device_rtc,
	&pxa_device_rtc,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa3xx_device_ssp4,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static struct sys_device pxa3xx_sysdev[] = {
	{
		.cls	= &pxa_irq_sysclass,
	}, {
		.cls	= &pxa3xx_mfp_sysclass,
	}, {
		.cls	= &pxa_gpio_sysclass,
	},
};

static int __init pxa3xx_init(void)
{
	int i, ret = 0;

	if (cpu_is_pxa3xx()) {

		reset_status = ARSR;

		/*
		 * clear RDH bit every time after reset
		 *
		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
		 * preserve them here in case they will be referenced later
		 */
		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);

		clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
			return ret;

		pxa3xx_init_pm();

		for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
			ret = sysdev_register(&pxa3xx_sysdev[i]);
			if (ret)
				pr_err("failed to register sysdev[%d]\n", i);
		}

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa3xx_init);
Commit	Line	Data
2c8086a5	1	/*
	2	* linux/arch/arm/mach-pxa/pxa3xx.c
	3	*
	4	* code specific to pxa3xx aka Monahans
	5	*
	6	* Copyright (C) 2006 Marvell International Ltd.
	7	*
e9bba8ee	8	* 2007-09-02: eric miao <eric.miao@marvell.com>
2c8086a5	9	* initial version
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/pm.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/irq.h>
7b5dea12	22	#include <linux/io.h>
c0165504	23	#include <linux/sysdev.h>
2c8086a5	24
851982c1	25	#include <asm/mach/map.h>
a09e64fb	26	#include <mach/hardware.h>
a58fbcd8	27	#include <mach/gpio.h>
a09e64fb	28	#include <mach/pxa3xx-regs.h>
afd2fc02	29	#include <mach/reset.h>
a09e64fb RK	30	#include <mach/ohci.h>
	31	#include <mach/pm.h>
	32	#include <mach/dma.h>
bf293aec	33	#include <mach/regs-intc.h>
ad68bb9f	34	#include <mach/smemc.h>
f0a83701	35	#include <plat/i2c.h>
2c8086a5	36
	37	#include "generic.h"
	38	#include "devices.h"
	39	#include "clock.h"
	40
	41	/* Crystal clock: 13MHz */
	42	#define BASE_CLK 13000000
	43
	44	/* Ring Oscillator Clock: 60MHz */
	45	#define RO_CLK 60000000
	46
	47	#define ACCR_D0CS (1 << 26)
c4d1fb62	48	#define ACCR_PCCE (1 << 11)
2c8086a5	49
bf293aec MR	50	#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
	51	#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
	52
2c8086a5	53	/* crystal frequency to static memory controller multiplier (SMCFS) */
	54	static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
	55
	56	/* crystal frequency to HSIO bus frequency multiplier (HSS) */
5852984a	57	static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
2c8086a5	58
	59	/*
	60	* Get the clock frequency as reflected by CCSR and the turbo flag.
	61	* We assume these values have been applied via a fcs.
	62	* If info is not 0 we also display the current settings.
	63	*/
	64	unsigned int pxa3xx_get_clk_frequency_khz(int info)
	65	{
	66	unsigned long acsr, xclkcfg;
	67	unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
	68
	69	/* Read XCLKCFG register turbo bit */
	70	__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
	71	t = xclkcfg & 0x1;
	72
	73	acsr = ACSR;
	74
	75	xl = acsr & 0x1f;
	76	xn = (acsr >> 8) & 0x7;
	77	hss = (acsr >> 14) & 0x3;
	78
	79	XL = xl * BASE_CLK;
	80	XN = xn * XL;
	81
	82	ro = acsr & ACCR_D0CS;
	83
	84	CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
	85	HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
	86
	87	if (info) {
	88	pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
	89	RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
	90	(ro) ? "" : "in");
	91	pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
	92	XL / 1000000, (XL % 1000000) / 10000, xl);
	93	pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
	94	XN / 1000000, (XN % 1000000) / 10000, xn,
	95	(t) ? "" : "in");
	96	pr_info("HSIO bus clock: %d.%02dMHz\n",
	97	HSS / 1000000, (HSS % 1000000) / 10000);
	98	}
	99
6232be32	100	return CLK / 1000;
2c8086a5	101	}
2c8086a5	102
04fef228 EM	103	void pxa3xx_clear_reset_status(unsigned int mask)
	104	{
	105	/* RESET_STATUS_* has a 1:1 mapping with ARSR */
	106	ARSR = mask;
	107	}
	108
60bfe7fa MB	109	/*
	110	* Return the current AC97 clock frequency.
	111	*/
	112	static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
	113	{
	114	unsigned long rate = 312000000;
	115	unsigned long ac97_div;
	116
	117	ac97_div = AC97_DIV;
	118
	119	/* This may loose precision for some rates but won't for the
	120	* standard 24.576MHz.
	121	*/
	122	rate /= (ac97_div >> 12) & 0x7fff;
	123	rate *= (ac97_div & 0xfff);
	124
	125	return rate;
	126	}
	127
2c8086a5	128	/*
	129	* Return the current HSIO bus clock frequency
	130	*/
	131	static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
	132	{
	133	unsigned long acsr;
	134	unsigned int hss, hsio_clk;
	135
	136	acsr = ACSR;
	137
	138	hss = (acsr >> 14) & 0x3;
	139	hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
	140
	141	return hsio_clk;
	142	}
	143
7a2c5cb0	144	void clk_pxa3xx_cken_enable(struct clk *clk)
2c8086a5	145	{
	146	unsigned long mask = 1ul << (clk->cken & 0x1f);
	147
2c8086a5	148	if (clk->cken < 32)
	149	CKENA \|= mask;
	150	else
	151	CKENB \|= mask;
2c8086a5	152	}
2c8086a5	153
7a2c5cb0	154	void clk_pxa3xx_cken_disable(struct clk *clk)
2c8086a5	155	{
	156	unsigned long mask = 1ul << (clk->cken & 0x1f);
	157
2c8086a5	158	if (clk->cken < 32)
	159	CKENA &= ~mask;
	160	else
	161	CKENB &= ~mask;
2c8086a5	162	}
2c8086a5	163
7a2c5cb0	164	const struct clkops clk_pxa3xx_cken_ops = {
2a0d7187	165	.enable = clk_pxa3xx_cken_enable,
	166	.disable = clk_pxa3xx_cken_disable,
	167	};
	168
2c8086a5	169	static const struct clkops clk_pxa3xx_hsio_ops = {
	170	.enable = clk_pxa3xx_cken_enable,
	171	.disable = clk_pxa3xx_cken_disable,
	172	.getrate = clk_pxa3xx_hsio_getrate,
	173	};
	174
60bfe7fa MB	175	static const struct clkops clk_pxa3xx_ac97_ops = {
	176	.enable = clk_pxa3xx_cken_enable,
	177	.disable = clk_pxa3xx_cken_disable,
	178	.getrate = clk_pxa3xx_ac97_getrate,
	179	};
	180
dcc88a17 MB	181	static void clk_pout_enable(struct clk *clk)
	182	{
	183	OSCC \|= OSCC_PEN;
	184	}
	185
	186	static void clk_pout_disable(struct clk *clk)
	187	{
	188	OSCC &= ~OSCC_PEN;
	189	}
	190
	191	static const struct clkops clk_pout_ops = {
	192	.enable = clk_pout_enable,
	193	.disable = clk_pout_disable,
	194	};
	195
9ba63c4f MR	196	static void clk_dummy_enable(struct clk *clk)
	197	{
	198	}
	199
	200	static void clk_dummy_disable(struct clk *clk)
	201	{
	202	}
	203
	204	static const struct clkops clk_dummy_ops = {
	205	.enable = clk_dummy_enable,
	206	.disable = clk_dummy_disable,
	207	};
	208
8c3abc7d RK	209	static struct clk clk_pxa3xx_pout = {
	210	.ops = &clk_pout_ops,
	211	.rate = 13000000,
	212	.delay = 70,
	213	};
d8e0db11	214
8c3abc7d RK	215	static struct clk clk_dummy = {
	216	.ops = &clk_dummy_ops,
	217	};
fafc9d3f	218
8c3abc7d RK	219	static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
	220	static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
	221	static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
	222	static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
	223	static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
	224	static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
e68750ae	225	static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
8c3abc7d RK	226	static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
	227	static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
	228	static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
	229	static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
	230	static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
	231	static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
	232	static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
	233	static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
	234	static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
	235
2e8581e7 EM	236	static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
	237	static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
	238	static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
	239
8c3abc7d RK	240	static struct clk_lookup pxa3xx_clkregs[] = {
	241	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	242	/* Power I2C clock is always on */
5c68b099	243	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
8c3abc7d RK	244	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	245	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	246	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	247	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	248	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	249	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	250	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	251	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	252	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	253	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
69f22be7	254	INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
8c3abc7d RK	255	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	256	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
	257	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
	258	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
	259	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
	260	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	261	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	262	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	263	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
2c8086a5	264	};
2c8086a5	265
7b5dea12	266	#ifdef CONFIG_PM
7b5dea12 RK	267
	268	#define ISRAM_START 0x5c000000
	269	#define ISRAM_SIZE SZ_256K
	270
	271	static void __iomem *sram;
	272	static unsigned long wakeup_src;
	273
c4d1fb62	274	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
c4d1fb62	275	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
7b5dea12	276
649de51b	277	enum { SLEEP_SAVE_CKENA,
c4d1fb62	278	SLEEP_SAVE_CKENB,
c4d1fb62	279	SLEEP_SAVE_ACCR,
7b5dea12	280
649de51b	281	SLEEP_SAVE_COUNT,
c4d1fb62	282	};
	283
	284	static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
	285	{
	286	SAVE(CKENA);
	287	SAVE(CKENB);
	288	SAVE(ACCR);
7b5dea12 RK	289	}
	290
	291	static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
	292	{
c4d1fb62	293	RESTORE(ACCR);
	294	RESTORE(CKENA);
	295	RESTORE(CKENB);
7b5dea12 RK	296	}
	297
	298	/*
	299	* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
	300	* memory controller has to be reinitialised, so we place some code
	301	* in the SRAM to perform this function.
	302	*
	303	* We disable FIQs across the standby - otherwise, we might receive a
	304	* FIQ while the SDRAM is unavailable.
	305	*/
	306	static void pxa3xx_cpu_standby(unsigned int pwrmode)
	307	{
	308	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	309	void (fn)(unsigned int) = (void __force )(sram + 0x8000);
	310
	311	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
	312	pm_enter_standby_end - pm_enter_standby_start);
	313
	314	AD2D0SR = ~0;
	315	AD2D1SR = ~0;
	316	AD2D0ER = wakeup_src;
	317	AD2D1ER = 0;
	318	ASCR = ASCR;
	319	ARSR = ARSR;
	320
	321	local_fiq_disable();
	322	fn(pwrmode);
	323	local_fiq_enable();
	324
	325	AD2D0ER = 0;
	326	AD2D1ER = 0;
7b5dea12 RK	327	}
7b5dea12 RK	328
c4d1fb62	329	/*
	330	* NOTE: currently, the OBM (OEM Boot Module) binary comes along with
	331	* PXA3xx development kits assumes that the resuming process continues
	332	* with the address stored within the first 4 bytes of SDRAM. The PSPR
	333	* register is used privately by BootROM and OBM, and _must_ be set to
	334	* 0x5c014000 for the moment.
	335	*/
	336	static void pxa3xx_cpu_pm_suspend(void)
	337	{
	338	volatile unsigned long p = (volatile void )0xc0000000;
	339	unsigned long saved_data = *p;
	340
	341	extern void pxa3xx_cpu_suspend(void);
	342	extern void pxa3xx_cpu_resume(void);
	343
	344	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	345	CKENA \|= (1 << CKEN_BOOT) \| (1 << CKEN_TPM);
	346	CKENB \|= 1 << (CKEN_HSIO2 & 0x1f);
	347
	348	/* clear and setup wakeup source */
	349	AD3SR = ~0;
	350	AD3ER = wakeup_src;
	351	ASCR = ASCR;
	352	ARSR = ARSR;
	353
	354	PCFR \|= (1u << 13); /* L1_DIS */
	355	PCFR &= ~((1u << 12) \| (1u << 1)); /* L0_EN \| SL_ROD */
	356
	357	PSPR = 0x5c014000;
	358
	359	/* overwrite with the resume address */
	360	*p = virt_to_phys(pxa3xx_cpu_resume);
	361
	362	pxa3xx_cpu_suspend();
	363
	364	*p = saved_data;
	365
	366	AD3ER = 0;
	367	}
	368
7b5dea12 RK	369	static void pxa3xx_cpu_pm_enter(suspend_state_t state)
	370	{
	371	/*
	372	* Don't sleep if no wakeup sources are defined
	373	*/
b86a5da8 MB	374	if (wakeup_src == 0) {
b86a5da8 MB	375	printk(KERN_ERR "Not suspending: no wakeup sources\n");
7b5dea12	376	return;
b86a5da8	377	}
7b5dea12 RK	378
	379	switch (state) {
	380	case PM_SUSPEND_STANDBY:
	381	pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
	382	break;
	383
	384	case PM_SUSPEND_MEM:
c4d1fb62	385	pxa3xx_cpu_pm_suspend();
7b5dea12 RK	386	break;
	387	}
	388	}
	389
	390	static int pxa3xx_cpu_pm_valid(suspend_state_t state)
	391	{
	392	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	393	}
	394
	395	static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
649de51b	396	.save_count = SLEEP_SAVE_COUNT,
7b5dea12 RK	397	.save = pxa3xx_cpu_pm_save,
	398	.restore = pxa3xx_cpu_pm_restore,
	399	.valid = pxa3xx_cpu_pm_valid,
	400	.enter = pxa3xx_cpu_pm_enter,
2c8086a5	401	};
2c8086a5	402
7b5dea12 RK	403	static void __init pxa3xx_init_pm(void)
	404	{
	405	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	406	if (!sram) {
	407	printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
	408	return;
	409	}
	410
	411	/*
	412	* Since we copy wakeup code into the SRAM, we need to ensure
	413	* that it is preserved over the low power modes. Note: bit 8
	414	* is undocumented in the developer manual, but must be set.
	415	*/
	416	AD1R \|= ADXR_L2 \| ADXR_R0;
	417	AD2R \|= ADXR_L2 \| ADXR_R0;
	418	AD3R \|= ADXR_L2 \| ADXR_R0;
	419
	420	/*
	421	* Clear the resume enable registers.
	422	*/
	423	AD1D0ER = 0;
	424	AD2D0ER = 0;
	425	AD2D1ER = 0;
	426	AD3ER = 0;
	427
	428	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
	429	}
	430
	431	static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
	432	{
	433	unsigned long flags, mask = 0;
	434
	435	switch (irq) {
	436	case IRQ_SSP3:
	437	mask = ADXER_MFP_WSSP3;
	438	break;
	439	case IRQ_MSL:
	440	mask = ADXER_WMSL0;
	441	break;
	442	case IRQ_USBH2:
	443	case IRQ_USBH1:
	444	mask = ADXER_WUSBH;
	445	break;
	446	case IRQ_KEYPAD:
	447	mask = ADXER_WKP;
	448	break;
	449	case IRQ_AC97:
	450	mask = ADXER_MFP_WAC97;
	451	break;
	452	case IRQ_USIM:
	453	mask = ADXER_WUSIM0;
	454	break;
	455	case IRQ_SSP2:
	456	mask = ADXER_MFP_WSSP2;
	457	break;
	458	case IRQ_I2C:
	459	mask = ADXER_MFP_WI2C;
	460	break;
	461	case IRQ_STUART:
	462	mask = ADXER_MFP_WUART3;
	463	break;
	464	case IRQ_BTUART:
	465	mask = ADXER_MFP_WUART2;
	466	break;
467	case IRQ_FFUART:
468	mask = ADXER_MFP_WUART1;
469	break;
470	case IRQ_MMC:
471	mask = ADXER_MFP_WMMC1;
472	break;
473	case IRQ_SSP:
474	mask = ADXER_MFP_WSSP1;
475	break;
476	case IRQ_RTCAlrm:
477	mask = ADXER_WRTC;
478	break;
479	case IRQ_SSP4:
480	mask = ADXER_MFP_WSSP4;
481	break;
482	case IRQ_TSI:
483	mask = ADXER_WTSI;
484	break;
485	case IRQ_USIM2:
486	mask = ADXER_WUSIM1;
487	break;
488	case IRQ_MMC2:
489	mask = ADXER_MFP_WMMC2;
490	break;
491	case IRQ_NAND:
492	mask = ADXER_MFP_WFLASH;
493	break;
494	case IRQ_USB2:
495	mask = ADXER_WUSB2;
496	break;
497	case IRQ_WAKEUP0:
498	mask = ADXER_WEXTWAKE0;
499	break;
500	case IRQ_WAKEUP1:
501	mask = ADXER_WEXTWAKE1;
502	break;
503	case IRQ_MMC3:
504	mask = ADXER_MFP_GEN12;
505	break;
e1217707 MB	506	default:
e1217707 MB	507	return -EINVAL;
7b5dea12 RK	508	}
	509
	510	local_irq_save(flags);
	511	if (on)
	512	wakeup_src \|= mask;
	513	else
	514	wakeup_src &= ~mask;
	515	local_irq_restore(flags);
	516
	517	return 0;
	518	}
7b5dea12 RK	519	#else
7b5dea12 RK	520	static inline void pxa3xx_init_pm(void) {}
b9e25ace	521	#define pxa3xx_set_wake NULL
7b5dea12 RK	522	#endif
7b5dea12 RK	523
bf293aec MR	524	static void pxa_ack_ext_wakeup(unsigned int irq)
	525	{
	526	PECR \|= PECR_IS(irq - IRQ_WAKEUP0);
	527	}
	528
	529	static void pxa_mask_ext_wakeup(unsigned int irq)
	530	{
	531	ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f));
	532	PECR &= ~PECR_IE(irq - IRQ_WAKEUP0);
	533	}
	534
	535	static void pxa_unmask_ext_wakeup(unsigned int irq)
	536	{
	537	ICMR2 \|= 1 << ((irq - PXA_IRQ(0)) & 0x1f);
	538	PECR \|= PECR_IE(irq - IRQ_WAKEUP0);
	539	}
	540
12882096 IG	541	static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type)
	542	{
	543	if (flow_type & IRQ_TYPE_EDGE_RISING)
	544	PWER \|= 1 << (irq - IRQ_WAKEUP0);
	545
	546	if (flow_type & IRQ_TYPE_EDGE_FALLING)
	547	PWER \|= 1 << (irq - IRQ_WAKEUP0 + 2);
	548
	549	return 0;
	550	}
	551
bf293aec MR	552	static struct irq_chip pxa_ext_wakeup_chip = {
	553	.name = "WAKEUP",
	554	.ack = pxa_ack_ext_wakeup,
	555	.mask = pxa_mask_ext_wakeup,
	556	.unmask = pxa_unmask_ext_wakeup,
12882096	557	.set_type = pxa_set_ext_wakeup_type,
bf293aec MR	558	};
	559
	560	static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
	561	{
	562	int irq;
	563
	564	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
	565	set_irq_chip(irq, &pxa_ext_wakeup_chip);
	566	set_irq_handler(irq, handle_edge_irq);
	567	set_irq_flags(irq, IRQF_VALID);
	568	}
	569
	570	pxa_ext_wakeup_chip.set_wake = fn;
	571	}
	572
2c8086a5	573	void __init pxa3xx_init_irq(void)
	574	{
	575	/* enable CP6 access */
	576	u32 value;
	577	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	578	value \|= (1 << 6);
	579	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
	580
b9e25ace	581	pxa_init_irq(56, pxa3xx_set_wake);
bf293aec	582	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
a58fbcd8	583	pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
2c8086a5	584	}
2c8086a5	585
851982c1 MV	586	static struct map_desc pxa3xx_io_desc[] __initdata = {
851982c1 MV	587	{ /* Mem Ctl */
ad68bb9f MV	588	.virtual = SMEMC_VIRT,
ad68bb9f MV	589	.pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
851982c1 MV	590	.length = 0x00200000,
	591	.type = MT_DEVICE
	592	}
	593	};
	594
	595	void __init pxa3xx_map_io(void)
	596	{
	597	pxa_map_io();
	598	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
	599	pxa3xx_get_clk_frequency_khz(1);
	600	}
	601
2c8086a5	602	/*
	603	* device registration specific to PXA3xx.
	604	*/
	605
9ba63c4f MR	606	void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
9ba63c4f MR	607	{
14758220	608	pxa_register_device(&pxa3xx_device_i2c_power, info);
9ba63c4f MR	609	}
9ba63c4f MR	610
2c8086a5	611	static struct platform_device *devices[] __initdata = {
94c35a6b	612	&pxa27x_device_udc,
09a5358d	613	&pxa_device_pmu,
2c8086a5	614	&pxa_device_i2s,
f0fba2ad LG	615	&pxa_device_asoc_ssp1,
	616	&pxa_device_asoc_ssp2,
	617	&pxa_device_asoc_ssp3,
	618	&pxa_device_asoc_ssp4,
	619	&pxa_device_asoc_platform,
72493146	620	&sa1100_device_rtc,
2c8086a5	621	&pxa_device_rtc,
d8e0db11	622	&pxa27x_device_ssp1,
	623	&pxa27x_device_ssp2,
	624	&pxa27x_device_ssp3,
	625	&pxa3xx_device_ssp4,
75540c1a	626	&pxa27x_device_pwm0,
75540c1a	627	&pxa27x_device_pwm1,
2c8086a5	628	};
2c8086a5	629
c0165504	630	static struct sys_device pxa3xx_sysdev[] = {
c0165504	631	{
c0165504	632	.cls = &pxa_irq_sysclass,
4be35e23	633	}, {
4be35e23	634	.cls = &pxa3xx_mfp_sysclass,
16dfdbf0	635	}, {
16dfdbf0	636	.cls = &pxa_gpio_sysclass,
c0165504	637	},
	638	};
	639
2c8086a5	640	static int __init pxa3xx_init(void)
2c8086a5	641	{
c0165504	642	int i, ret = 0;
2c8086a5	643
2c8086a5	644	if (cpu_is_pxa3xx()) {
04fef228 EM	645
	646	reset_status = ARSR;
	647
86260f98 DK	648	/*
	649	* clear RDH bit every time after reset
	650	*
	651	* Note: the last 3 bits DxS are write-1-to-clear so carefully
	652	* preserve them here in case they will be referenced later
	653	*/
	654	ASCR &= ~(ASCR_RDH \| ASCR_D1S \| ASCR_D2S \| ASCR_D3S);
	655
0a0300dc	656	clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
2c8086a5	657
fef1f99a	658	if ((ret = pxa_init_dma(IRQ_DMA, 32)))
2c8086a5	659	return ret;
2c8086a5	660
7b5dea12 RK	661	pxa3xx_init_pm();
7b5dea12 RK	662
c0165504	663	for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
	664	ret = sysdev_register(&pxa3xx_sysdev[i]);
	665	if (ret)
	666	pr_err("failed to register sysdev[%d]\n", i);
	667	}
	668
	669	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
2c8086a5	670	}
c0165504	671
c0165504	672	return ret;
2c8086a5	673	}
2c8086a5	674
1c104e0e	675	postcore_initcall(pxa3xx_init);