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2c8086a5 | 1 | /* |
2 | * linux/arch/arm/mach-pxa/pxa3xx.c | |
3 | * | |
4 | * code specific to pxa3xx aka Monahans | |
5 | * | |
6 | * Copyright (C) 2006 Marvell International Ltd. | |
7 | * | |
e9bba8ee | 8 | * 2007-09-02: eric miao <eric.miao@marvell.com> |
2c8086a5 | 9 | * initial version |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/pm.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/irq.h> | |
7b5dea12 | 22 | #include <linux/io.h> |
c0165504 | 23 | #include <linux/sysdev.h> |
2c8086a5 | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
a58fbcd8 | 26 | #include <mach/gpio.h> |
a09e64fb | 27 | #include <mach/pxa3xx-regs.h> |
afd2fc02 | 28 | #include <mach/reset.h> |
a09e64fb RK |
29 | #include <mach/ohci.h> |
30 | #include <mach/pm.h> | |
31 | #include <mach/dma.h> | |
32 | #include <mach/ssp.h> | |
14758220 | 33 | #include <mach/i2c.h> |
2c8086a5 | 34 | |
35 | #include "generic.h" | |
36 | #include "devices.h" | |
37 | #include "clock.h" | |
38 | ||
39 | /* Crystal clock: 13MHz */ | |
40 | #define BASE_CLK 13000000 | |
41 | ||
42 | /* Ring Oscillator Clock: 60MHz */ | |
43 | #define RO_CLK 60000000 | |
44 | ||
45 | #define ACCR_D0CS (1 << 26) | |
c4d1fb62 | 46 | #define ACCR_PCCE (1 << 11) |
2c8086a5 | 47 | |
48 | /* crystal frequency to static memory controller multiplier (SMCFS) */ | |
49 | static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; | |
50 | ||
51 | /* crystal frequency to HSIO bus frequency multiplier (HSS) */ | |
52 | static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; | |
53 | ||
54 | /* | |
55 | * Get the clock frequency as reflected by CCSR and the turbo flag. | |
56 | * We assume these values have been applied via a fcs. | |
57 | * If info is not 0 we also display the current settings. | |
58 | */ | |
59 | unsigned int pxa3xx_get_clk_frequency_khz(int info) | |
60 | { | |
61 | unsigned long acsr, xclkcfg; | |
62 | unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; | |
63 | ||
64 | /* Read XCLKCFG register turbo bit */ | |
65 | __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); | |
66 | t = xclkcfg & 0x1; | |
67 | ||
68 | acsr = ACSR; | |
69 | ||
70 | xl = acsr & 0x1f; | |
71 | xn = (acsr >> 8) & 0x7; | |
72 | hss = (acsr >> 14) & 0x3; | |
73 | ||
74 | XL = xl * BASE_CLK; | |
75 | XN = xn * XL; | |
76 | ||
77 | ro = acsr & ACCR_D0CS; | |
78 | ||
79 | CLK = (ro) ? RO_CLK : ((t) ? XN : XL); | |
80 | HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; | |
81 | ||
82 | if (info) { | |
83 | pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", | |
84 | RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, | |
85 | (ro) ? "" : "in"); | |
86 | pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", | |
87 | XL / 1000000, (XL % 1000000) / 10000, xl); | |
88 | pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", | |
89 | XN / 1000000, (XN % 1000000) / 10000, xn, | |
90 | (t) ? "" : "in"); | |
91 | pr_info("HSIO bus clock: %d.%02dMHz\n", | |
92 | HSS / 1000000, (HSS % 1000000) / 10000); | |
93 | } | |
94 | ||
6232be32 | 95 | return CLK / 1000; |
2c8086a5 | 96 | } |
97 | ||
98 | /* | |
99 | * Return the current static memory controller clock frequency | |
100 | * in units of 10kHz | |
101 | */ | |
102 | unsigned int pxa3xx_get_memclk_frequency_10khz(void) | |
103 | { | |
104 | unsigned long acsr; | |
105 | unsigned int smcfs, clk = 0; | |
106 | ||
107 | acsr = ACSR; | |
108 | ||
109 | smcfs = (acsr >> 23) & 0x7; | |
110 | clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; | |
111 | ||
112 | return (clk / 10000); | |
113 | } | |
114 | ||
04fef228 EM |
115 | void pxa3xx_clear_reset_status(unsigned int mask) |
116 | { | |
117 | /* RESET_STATUS_* has a 1:1 mapping with ARSR */ | |
118 | ARSR = mask; | |
119 | } | |
120 | ||
60bfe7fa MB |
121 | /* |
122 | * Return the current AC97 clock frequency. | |
123 | */ | |
124 | static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) | |
125 | { | |
126 | unsigned long rate = 312000000; | |
127 | unsigned long ac97_div; | |
128 | ||
129 | ac97_div = AC97_DIV; | |
130 | ||
131 | /* This may loose precision for some rates but won't for the | |
132 | * standard 24.576MHz. | |
133 | */ | |
134 | rate /= (ac97_div >> 12) & 0x7fff; | |
135 | rate *= (ac97_div & 0xfff); | |
136 | ||
137 | return rate; | |
138 | } | |
139 | ||
2c8086a5 | 140 | /* |
141 | * Return the current HSIO bus clock frequency | |
142 | */ | |
143 | static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) | |
144 | { | |
145 | unsigned long acsr; | |
146 | unsigned int hss, hsio_clk; | |
147 | ||
148 | acsr = ACSR; | |
149 | ||
150 | hss = (acsr >> 14) & 0x3; | |
151 | hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; | |
152 | ||
153 | return hsio_clk; | |
154 | } | |
155 | ||
7a2c5cb0 | 156 | void clk_pxa3xx_cken_enable(struct clk *clk) |
2c8086a5 | 157 | { |
158 | unsigned long mask = 1ul << (clk->cken & 0x1f); | |
159 | ||
2c8086a5 | 160 | if (clk->cken < 32) |
161 | CKENA |= mask; | |
162 | else | |
163 | CKENB |= mask; | |
2c8086a5 | 164 | } |
165 | ||
7a2c5cb0 | 166 | void clk_pxa3xx_cken_disable(struct clk *clk) |
2c8086a5 | 167 | { |
168 | unsigned long mask = 1ul << (clk->cken & 0x1f); | |
169 | ||
2c8086a5 | 170 | if (clk->cken < 32) |
171 | CKENA &= ~mask; | |
172 | else | |
173 | CKENB &= ~mask; | |
2c8086a5 | 174 | } |
175 | ||
7a2c5cb0 | 176 | const struct clkops clk_pxa3xx_cken_ops = { |
2a0d7187 | 177 | .enable = clk_pxa3xx_cken_enable, |
178 | .disable = clk_pxa3xx_cken_disable, | |
179 | }; | |
180 | ||
2c8086a5 | 181 | static const struct clkops clk_pxa3xx_hsio_ops = { |
182 | .enable = clk_pxa3xx_cken_enable, | |
183 | .disable = clk_pxa3xx_cken_disable, | |
184 | .getrate = clk_pxa3xx_hsio_getrate, | |
185 | }; | |
186 | ||
60bfe7fa MB |
187 | static const struct clkops clk_pxa3xx_ac97_ops = { |
188 | .enable = clk_pxa3xx_cken_enable, | |
189 | .disable = clk_pxa3xx_cken_disable, | |
190 | .getrate = clk_pxa3xx_ac97_getrate, | |
191 | }; | |
192 | ||
dcc88a17 MB |
193 | static void clk_pout_enable(struct clk *clk) |
194 | { | |
195 | OSCC |= OSCC_PEN; | |
196 | } | |
197 | ||
198 | static void clk_pout_disable(struct clk *clk) | |
199 | { | |
200 | OSCC &= ~OSCC_PEN; | |
201 | } | |
202 | ||
203 | static const struct clkops clk_pout_ops = { | |
204 | .enable = clk_pout_enable, | |
205 | .disable = clk_pout_disable, | |
206 | }; | |
207 | ||
9ba63c4f MR |
208 | static void clk_dummy_enable(struct clk *clk) |
209 | { | |
210 | } | |
211 | ||
212 | static void clk_dummy_disable(struct clk *clk) | |
213 | { | |
214 | } | |
215 | ||
216 | static const struct clkops clk_dummy_ops = { | |
217 | .enable = clk_dummy_enable, | |
218 | .disable = clk_dummy_disable, | |
219 | }; | |
220 | ||
8c3abc7d RK |
221 | static struct clk clk_pxa3xx_pout = { |
222 | .ops = &clk_pout_ops, | |
223 | .rate = 13000000, | |
224 | .delay = 70, | |
225 | }; | |
d8e0db11 | 226 | |
8c3abc7d RK |
227 | static struct clk clk_dummy = { |
228 | .ops = &clk_dummy_ops, | |
229 | }; | |
fafc9d3f | 230 | |
8c3abc7d RK |
231 | static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); |
232 | static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); | |
233 | static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); | |
234 | static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); | |
235 | static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); | |
236 | static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); | |
237 | static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); | |
238 | static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); | |
239 | static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); | |
240 | static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); | |
241 | static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); | |
242 | static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); | |
243 | static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); | |
244 | static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); | |
245 | static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); | |
246 | static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); | |
247 | static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); | |
248 | static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); | |
249 | ||
250 | static struct clk_lookup pxa3xx_clkregs[] = { | |
251 | INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), | |
252 | /* Power I2C clock is always on */ | |
253 | INIT_CLKREG(&clk_dummy, "pxa2xx-i2c.1", NULL), | |
254 | INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), | |
255 | INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), | |
256 | INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), | |
257 | INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), | |
258 | INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), | |
259 | INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), | |
260 | INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), | |
261 | INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), | |
262 | INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), | |
263 | INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), | |
264 | INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), | |
265 | INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), | |
266 | INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), | |
267 | INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), | |
268 | INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), | |
269 | INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), | |
270 | INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), | |
271 | INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), | |
272 | INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), | |
2c8086a5 | 273 | }; |
274 | ||
7b5dea12 | 275 | #ifdef CONFIG_PM |
7b5dea12 RK |
276 | |
277 | #define ISRAM_START 0x5c000000 | |
278 | #define ISRAM_SIZE SZ_256K | |
279 | ||
280 | static void __iomem *sram; | |
281 | static unsigned long wakeup_src; | |
282 | ||
c4d1fb62 | 283 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
284 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | |
7b5dea12 | 285 | |
649de51b | 286 | enum { SLEEP_SAVE_CKENA, |
c4d1fb62 | 287 | SLEEP_SAVE_CKENB, |
288 | SLEEP_SAVE_ACCR, | |
7b5dea12 | 289 | |
649de51b | 290 | SLEEP_SAVE_COUNT, |
c4d1fb62 | 291 | }; |
292 | ||
293 | static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) | |
294 | { | |
295 | SAVE(CKENA); | |
296 | SAVE(CKENB); | |
297 | SAVE(ACCR); | |
7b5dea12 RK |
298 | } |
299 | ||
300 | static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) | |
301 | { | |
c4d1fb62 | 302 | RESTORE(ACCR); |
303 | RESTORE(CKENA); | |
304 | RESTORE(CKENB); | |
7b5dea12 RK |
305 | } |
306 | ||
307 | /* | |
308 | * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic | |
309 | * memory controller has to be reinitialised, so we place some code | |
310 | * in the SRAM to perform this function. | |
311 | * | |
312 | * We disable FIQs across the standby - otherwise, we might receive a | |
313 | * FIQ while the SDRAM is unavailable. | |
314 | */ | |
315 | static void pxa3xx_cpu_standby(unsigned int pwrmode) | |
316 | { | |
317 | extern const char pm_enter_standby_start[], pm_enter_standby_end[]; | |
318 | void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); | |
319 | ||
320 | memcpy_toio(sram + 0x8000, pm_enter_standby_start, | |
321 | pm_enter_standby_end - pm_enter_standby_start); | |
322 | ||
323 | AD2D0SR = ~0; | |
324 | AD2D1SR = ~0; | |
325 | AD2D0ER = wakeup_src; | |
326 | AD2D1ER = 0; | |
327 | ASCR = ASCR; | |
328 | ARSR = ARSR; | |
329 | ||
330 | local_fiq_disable(); | |
331 | fn(pwrmode); | |
332 | local_fiq_enable(); | |
333 | ||
334 | AD2D0ER = 0; | |
335 | AD2D1ER = 0; | |
7b5dea12 RK |
336 | } |
337 | ||
c4d1fb62 | 338 | /* |
339 | * NOTE: currently, the OBM (OEM Boot Module) binary comes along with | |
340 | * PXA3xx development kits assumes that the resuming process continues | |
341 | * with the address stored within the first 4 bytes of SDRAM. The PSPR | |
342 | * register is used privately by BootROM and OBM, and _must_ be set to | |
343 | * 0x5c014000 for the moment. | |
344 | */ | |
345 | static void pxa3xx_cpu_pm_suspend(void) | |
346 | { | |
347 | volatile unsigned long *p = (volatile void *)0xc0000000; | |
348 | unsigned long saved_data = *p; | |
349 | ||
350 | extern void pxa3xx_cpu_suspend(void); | |
351 | extern void pxa3xx_cpu_resume(void); | |
352 | ||
353 | /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ | |
354 | CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); | |
355 | CKENB |= 1 << (CKEN_HSIO2 & 0x1f); | |
356 | ||
357 | /* clear and setup wakeup source */ | |
358 | AD3SR = ~0; | |
359 | AD3ER = wakeup_src; | |
360 | ASCR = ASCR; | |
361 | ARSR = ARSR; | |
362 | ||
363 | PCFR |= (1u << 13); /* L1_DIS */ | |
364 | PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ | |
365 | ||
366 | PSPR = 0x5c014000; | |
367 | ||
368 | /* overwrite with the resume address */ | |
369 | *p = virt_to_phys(pxa3xx_cpu_resume); | |
370 | ||
371 | pxa3xx_cpu_suspend(); | |
372 | ||
373 | *p = saved_data; | |
374 | ||
375 | AD3ER = 0; | |
376 | } | |
377 | ||
7b5dea12 RK |
378 | static void pxa3xx_cpu_pm_enter(suspend_state_t state) |
379 | { | |
380 | /* | |
381 | * Don't sleep if no wakeup sources are defined | |
382 | */ | |
b86a5da8 MB |
383 | if (wakeup_src == 0) { |
384 | printk(KERN_ERR "Not suspending: no wakeup sources\n"); | |
7b5dea12 | 385 | return; |
b86a5da8 | 386 | } |
7b5dea12 RK |
387 | |
388 | switch (state) { | |
389 | case PM_SUSPEND_STANDBY: | |
390 | pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); | |
391 | break; | |
392 | ||
393 | case PM_SUSPEND_MEM: | |
c4d1fb62 | 394 | pxa3xx_cpu_pm_suspend(); |
7b5dea12 RK |
395 | break; |
396 | } | |
397 | } | |
398 | ||
399 | static int pxa3xx_cpu_pm_valid(suspend_state_t state) | |
400 | { | |
401 | return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; | |
402 | } | |
403 | ||
404 | static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { | |
649de51b | 405 | .save_count = SLEEP_SAVE_COUNT, |
7b5dea12 RK |
406 | .save = pxa3xx_cpu_pm_save, |
407 | .restore = pxa3xx_cpu_pm_restore, | |
408 | .valid = pxa3xx_cpu_pm_valid, | |
409 | .enter = pxa3xx_cpu_pm_enter, | |
2c8086a5 | 410 | }; |
411 | ||
7b5dea12 RK |
412 | static void __init pxa3xx_init_pm(void) |
413 | { | |
414 | sram = ioremap(ISRAM_START, ISRAM_SIZE); | |
415 | if (!sram) { | |
416 | printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); | |
417 | return; | |
418 | } | |
419 | ||
420 | /* | |
421 | * Since we copy wakeup code into the SRAM, we need to ensure | |
422 | * that it is preserved over the low power modes. Note: bit 8 | |
423 | * is undocumented in the developer manual, but must be set. | |
424 | */ | |
425 | AD1R |= ADXR_L2 | ADXR_R0; | |
426 | AD2R |= ADXR_L2 | ADXR_R0; | |
427 | AD3R |= ADXR_L2 | ADXR_R0; | |
428 | ||
429 | /* | |
430 | * Clear the resume enable registers. | |
431 | */ | |
432 | AD1D0ER = 0; | |
433 | AD2D0ER = 0; | |
434 | AD2D1ER = 0; | |
435 | AD3ER = 0; | |
436 | ||
437 | pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; | |
438 | } | |
439 | ||
440 | static int pxa3xx_set_wake(unsigned int irq, unsigned int on) | |
441 | { | |
442 | unsigned long flags, mask = 0; | |
443 | ||
444 | switch (irq) { | |
445 | case IRQ_SSP3: | |
446 | mask = ADXER_MFP_WSSP3; | |
447 | break; | |
448 | case IRQ_MSL: | |
449 | mask = ADXER_WMSL0; | |
450 | break; | |
451 | case IRQ_USBH2: | |
452 | case IRQ_USBH1: | |
453 | mask = ADXER_WUSBH; | |
454 | break; | |
455 | case IRQ_KEYPAD: | |
456 | mask = ADXER_WKP; | |
457 | break; | |
458 | case IRQ_AC97: | |
459 | mask = ADXER_MFP_WAC97; | |
460 | break; | |
461 | case IRQ_USIM: | |
462 | mask = ADXER_WUSIM0; | |
463 | break; | |
464 | case IRQ_SSP2: | |
465 | mask = ADXER_MFP_WSSP2; | |
466 | break; | |
467 | case IRQ_I2C: | |
468 | mask = ADXER_MFP_WI2C; | |
469 | break; | |
470 | case IRQ_STUART: | |
471 | mask = ADXER_MFP_WUART3; | |
472 | break; | |
473 | case IRQ_BTUART: | |
474 | mask = ADXER_MFP_WUART2; | |
475 | break; | |
476 | case IRQ_FFUART: | |
477 | mask = ADXER_MFP_WUART1; | |
478 | break; | |
479 | case IRQ_MMC: | |
480 | mask = ADXER_MFP_WMMC1; | |
481 | break; | |
482 | case IRQ_SSP: | |
483 | mask = ADXER_MFP_WSSP1; | |
484 | break; | |
485 | case IRQ_RTCAlrm: | |
486 | mask = ADXER_WRTC; | |
487 | break; | |
488 | case IRQ_SSP4: | |
489 | mask = ADXER_MFP_WSSP4; | |
490 | break; | |
491 | case IRQ_TSI: | |
492 | mask = ADXER_WTSI; | |
493 | break; | |
494 | case IRQ_USIM2: | |
495 | mask = ADXER_WUSIM1; | |
496 | break; | |
497 | case IRQ_MMC2: | |
498 | mask = ADXER_MFP_WMMC2; | |
499 | break; | |
500 | case IRQ_NAND: | |
501 | mask = ADXER_MFP_WFLASH; | |
502 | break; | |
503 | case IRQ_USB2: | |
504 | mask = ADXER_WUSB2; | |
505 | break; | |
506 | case IRQ_WAKEUP0: | |
507 | mask = ADXER_WEXTWAKE0; | |
508 | break; | |
509 | case IRQ_WAKEUP1: | |
510 | mask = ADXER_WEXTWAKE1; | |
511 | break; | |
512 | case IRQ_MMC3: | |
513 | mask = ADXER_MFP_GEN12; | |
514 | break; | |
e1217707 MB |
515 | default: |
516 | return -EINVAL; | |
7b5dea12 RK |
517 | } |
518 | ||
519 | local_irq_save(flags); | |
520 | if (on) | |
521 | wakeup_src |= mask; | |
522 | else | |
523 | wakeup_src &= ~mask; | |
524 | local_irq_restore(flags); | |
525 | ||
526 | return 0; | |
527 | } | |
7b5dea12 RK |
528 | #else |
529 | static inline void pxa3xx_init_pm(void) {} | |
b9e25ace | 530 | #define pxa3xx_set_wake NULL |
7b5dea12 RK |
531 | #endif |
532 | ||
2c8086a5 | 533 | void __init pxa3xx_init_irq(void) |
534 | { | |
535 | /* enable CP6 access */ | |
536 | u32 value; | |
537 | __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); | |
538 | value |= (1 << 6); | |
539 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); | |
540 | ||
b9e25ace | 541 | pxa_init_irq(56, pxa3xx_set_wake); |
a58fbcd8 | 542 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); |
2c8086a5 | 543 | } |
544 | ||
545 | /* | |
546 | * device registration specific to PXA3xx. | |
547 | */ | |
548 | ||
9ba63c4f MR |
549 | void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) |
550 | { | |
14758220 | 551 | pxa_register_device(&pxa3xx_device_i2c_power, info); |
9ba63c4f MR |
552 | } |
553 | ||
2c8086a5 | 554 | static struct platform_device *devices[] __initdata = { |
284d115e | 555 | /* &pxa_device_udc, The UDC driver is PXA25x only */ |
2c8086a5 | 556 | &pxa_device_ffuart, |
557 | &pxa_device_btuart, | |
558 | &pxa_device_stuart, | |
2c8086a5 | 559 | &pxa_device_i2s, |
72493146 | 560 | &sa1100_device_rtc, |
2c8086a5 | 561 | &pxa_device_rtc, |
d8e0db11 | 562 | &pxa27x_device_ssp1, |
563 | &pxa27x_device_ssp2, | |
564 | &pxa27x_device_ssp3, | |
565 | &pxa3xx_device_ssp4, | |
75540c1a | 566 | &pxa27x_device_pwm0, |
567 | &pxa27x_device_pwm1, | |
2c8086a5 | 568 | }; |
569 | ||
c0165504 | 570 | static struct sys_device pxa3xx_sysdev[] = { |
571 | { | |
c0165504 | 572 | .cls = &pxa_irq_sysclass, |
4be35e23 | 573 | }, { |
574 | .cls = &pxa3xx_mfp_sysclass, | |
16dfdbf0 | 575 | }, { |
576 | .cls = &pxa_gpio_sysclass, | |
c0165504 | 577 | }, |
578 | }; | |
579 | ||
2c8086a5 | 580 | static int __init pxa3xx_init(void) |
581 | { | |
c0165504 | 582 | int i, ret = 0; |
2c8086a5 | 583 | |
584 | if (cpu_is_pxa3xx()) { | |
04fef228 EM |
585 | |
586 | reset_status = ARSR; | |
587 | ||
86260f98 DK |
588 | /* |
589 | * clear RDH bit every time after reset | |
590 | * | |
591 | * Note: the last 3 bits DxS are write-1-to-clear so carefully | |
592 | * preserve them here in case they will be referenced later | |
593 | */ | |
594 | ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); | |
595 | ||
8c3abc7d | 596 | clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); |
2c8086a5 | 597 | |
fef1f99a | 598 | if ((ret = pxa_init_dma(IRQ_DMA, 32))) |
2c8086a5 | 599 | return ret; |
600 | ||
7b5dea12 RK |
601 | pxa3xx_init_pm(); |
602 | ||
c0165504 | 603 | for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { |
604 | ret = sysdev_register(&pxa3xx_sysdev[i]); | |
605 | if (ret) | |
606 | pr_err("failed to register sysdev[%d]\n", i); | |
607 | } | |
608 | ||
609 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); | |
2c8086a5 | 610 | } |
c0165504 | 611 | |
612 | return ret; | |
2c8086a5 | 613 | } |
614 | ||
1c104e0e | 615 | postcore_initcall(pxa3xx_init); |