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2c8086a5 | 1 | /* |
2 | * linux/arch/arm/mach-pxa/pxa3xx.c | |
3 | * | |
4 | * code specific to pxa3xx aka Monahans | |
5 | * | |
6 | * Copyright (C) 2006 Marvell International Ltd. | |
7 | * | |
e9bba8ee | 8 | * 2007-09-02: eric miao <eric.miao@marvell.com> |
2c8086a5 | 9 | * initial version |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/pm.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/irq.h> | |
7b5dea12 | 22 | #include <linux/io.h> |
c0165504 | 23 | #include <linux/sysdev.h> |
b459396e | 24 | #include <linux/i2c/pxa-i2c.h> |
2c8086a5 | 25 | |
851982c1 | 26 | #include <asm/mach/map.h> |
a09e64fb | 27 | #include <mach/hardware.h> |
a58fbcd8 | 28 | #include <mach/gpio.h> |
a09e64fb | 29 | #include <mach/pxa3xx-regs.h> |
afd2fc02 | 30 | #include <mach/reset.h> |
a09e64fb RK |
31 | #include <mach/ohci.h> |
32 | #include <mach/pm.h> | |
33 | #include <mach/dma.h> | |
bf293aec | 34 | #include <mach/regs-intc.h> |
ad68bb9f | 35 | #include <mach/smemc.h> |
2c8086a5 | 36 | |
37 | #include "generic.h" | |
38 | #include "devices.h" | |
39 | #include "clock.h" | |
40 | ||
bf293aec MR |
41 | #define PECR_IE(n) ((1 << ((n) * 2)) << 28) |
42 | #define PECR_IS(n) ((1 << ((n) * 2)) << 29) | |
43 | ||
8c3abc7d RK |
44 | static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); |
45 | static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); | |
46 | static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); | |
47 | static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); | |
48 | static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); | |
49 | static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); | |
e68750ae | 50 | static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); |
8c3abc7d RK |
51 | static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); |
52 | static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); | |
53 | static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); | |
54 | static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); | |
55 | static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); | |
56 | static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); | |
57 | static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); | |
58 | static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); | |
59 | static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); | |
60 | ||
2e8581e7 | 61 | static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); |
c085052b | 62 | static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops); |
2e8581e7 EM |
63 | static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); |
64 | static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); | |
4029813c | 65 | static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70); |
2e8581e7 | 66 | |
8c3abc7d RK |
67 | static struct clk_lookup pxa3xx_clkregs[] = { |
68 | INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), | |
69 | /* Power I2C clock is always on */ | |
5c68b099 | 70 | INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), |
8c3abc7d RK |
71 | INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), |
72 | INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), | |
73 | INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), | |
74 | INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), | |
75 | INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), | |
76 | INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), | |
77 | INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), | |
78 | INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), | |
79 | INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), | |
80 | INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), | |
69f22be7 | 81 | INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), |
8c3abc7d RK |
82 | INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), |
83 | INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), | |
84 | INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), | |
85 | INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), | |
86 | INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), | |
87 | INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), | |
88 | INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), | |
89 | INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), | |
90 | INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), | |
c085052b | 91 | INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL), |
2c8086a5 | 92 | }; |
93 | ||
7b5dea12 | 94 | #ifdef CONFIG_PM |
7b5dea12 RK |
95 | |
96 | #define ISRAM_START 0x5c000000 | |
97 | #define ISRAM_SIZE SZ_256K | |
98 | ||
99 | static void __iomem *sram; | |
100 | static unsigned long wakeup_src; | |
101 | ||
7b5dea12 RK |
102 | /* |
103 | * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic | |
104 | * memory controller has to be reinitialised, so we place some code | |
105 | * in the SRAM to perform this function. | |
106 | * | |
107 | * We disable FIQs across the standby - otherwise, we might receive a | |
108 | * FIQ while the SDRAM is unavailable. | |
109 | */ | |
110 | static void pxa3xx_cpu_standby(unsigned int pwrmode) | |
111 | { | |
112 | extern const char pm_enter_standby_start[], pm_enter_standby_end[]; | |
113 | void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); | |
114 | ||
115 | memcpy_toio(sram + 0x8000, pm_enter_standby_start, | |
116 | pm_enter_standby_end - pm_enter_standby_start); | |
117 | ||
118 | AD2D0SR = ~0; | |
119 | AD2D1SR = ~0; | |
120 | AD2D0ER = wakeup_src; | |
121 | AD2D1ER = 0; | |
122 | ASCR = ASCR; | |
123 | ARSR = ARSR; | |
124 | ||
125 | local_fiq_disable(); | |
126 | fn(pwrmode); | |
127 | local_fiq_enable(); | |
128 | ||
129 | AD2D0ER = 0; | |
130 | AD2D1ER = 0; | |
7b5dea12 RK |
131 | } |
132 | ||
c4d1fb62 | 133 | /* |
134 | * NOTE: currently, the OBM (OEM Boot Module) binary comes along with | |
135 | * PXA3xx development kits assumes that the resuming process continues | |
136 | * with the address stored within the first 4 bytes of SDRAM. The PSPR | |
137 | * register is used privately by BootROM and OBM, and _must_ be set to | |
138 | * 0x5c014000 for the moment. | |
139 | */ | |
140 | static void pxa3xx_cpu_pm_suspend(void) | |
141 | { | |
142 | volatile unsigned long *p = (volatile void *)0xc0000000; | |
143 | unsigned long saved_data = *p; | |
144 | ||
4f5ad99b | 145 | extern void pxa3xx_cpu_suspend(long); |
c4d1fb62 | 146 | |
147 | /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ | |
148 | CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); | |
149 | CKENB |= 1 << (CKEN_HSIO2 & 0x1f); | |
150 | ||
151 | /* clear and setup wakeup source */ | |
152 | AD3SR = ~0; | |
153 | AD3ER = wakeup_src; | |
154 | ASCR = ASCR; | |
155 | ARSR = ARSR; | |
156 | ||
157 | PCFR |= (1u << 13); /* L1_DIS */ | |
158 | PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ | |
159 | ||
160 | PSPR = 0x5c014000; | |
161 | ||
162 | /* overwrite with the resume address */ | |
4f5ad99b | 163 | *p = virt_to_phys(cpu_resume); |
c4d1fb62 | 164 | |
4f5ad99b | 165 | pxa3xx_cpu_suspend(PLAT_PHYS_OFFSET - PAGE_OFFSET); |
c4d1fb62 | 166 | |
167 | *p = saved_data; | |
168 | ||
169 | AD3ER = 0; | |
170 | } | |
171 | ||
7b5dea12 RK |
172 | static void pxa3xx_cpu_pm_enter(suspend_state_t state) |
173 | { | |
174 | /* | |
175 | * Don't sleep if no wakeup sources are defined | |
176 | */ | |
b86a5da8 MB |
177 | if (wakeup_src == 0) { |
178 | printk(KERN_ERR "Not suspending: no wakeup sources\n"); | |
7b5dea12 | 179 | return; |
b86a5da8 | 180 | } |
7b5dea12 RK |
181 | |
182 | switch (state) { | |
183 | case PM_SUSPEND_STANDBY: | |
184 | pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); | |
185 | break; | |
186 | ||
187 | case PM_SUSPEND_MEM: | |
c4d1fb62 | 188 | pxa3xx_cpu_pm_suspend(); |
7b5dea12 RK |
189 | break; |
190 | } | |
191 | } | |
192 | ||
193 | static int pxa3xx_cpu_pm_valid(suspend_state_t state) | |
194 | { | |
195 | return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; | |
196 | } | |
197 | ||
198 | static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { | |
7b5dea12 RK |
199 | .valid = pxa3xx_cpu_pm_valid, |
200 | .enter = pxa3xx_cpu_pm_enter, | |
2c8086a5 | 201 | }; |
202 | ||
7b5dea12 RK |
203 | static void __init pxa3xx_init_pm(void) |
204 | { | |
205 | sram = ioremap(ISRAM_START, ISRAM_SIZE); | |
206 | if (!sram) { | |
207 | printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); | |
208 | return; | |
209 | } | |
210 | ||
211 | /* | |
212 | * Since we copy wakeup code into the SRAM, we need to ensure | |
213 | * that it is preserved over the low power modes. Note: bit 8 | |
214 | * is undocumented in the developer manual, but must be set. | |
215 | */ | |
216 | AD1R |= ADXR_L2 | ADXR_R0; | |
217 | AD2R |= ADXR_L2 | ADXR_R0; | |
218 | AD3R |= ADXR_L2 | ADXR_R0; | |
219 | ||
220 | /* | |
221 | * Clear the resume enable registers. | |
222 | */ | |
223 | AD1D0ER = 0; | |
224 | AD2D0ER = 0; | |
225 | AD2D1ER = 0; | |
226 | AD3ER = 0; | |
227 | ||
228 | pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; | |
229 | } | |
230 | ||
a3f4c927 | 231 | static int pxa3xx_set_wake(struct irq_data *d, unsigned int on) |
7b5dea12 RK |
232 | { |
233 | unsigned long flags, mask = 0; | |
234 | ||
a3f4c927 | 235 | switch (d->irq) { |
7b5dea12 RK |
236 | case IRQ_SSP3: |
237 | mask = ADXER_MFP_WSSP3; | |
238 | break; | |
239 | case IRQ_MSL: | |
240 | mask = ADXER_WMSL0; | |
241 | break; | |
242 | case IRQ_USBH2: | |
243 | case IRQ_USBH1: | |
244 | mask = ADXER_WUSBH; | |
245 | break; | |
246 | case IRQ_KEYPAD: | |
247 | mask = ADXER_WKP; | |
248 | break; | |
249 | case IRQ_AC97: | |
250 | mask = ADXER_MFP_WAC97; | |
251 | break; | |
252 | case IRQ_USIM: | |
253 | mask = ADXER_WUSIM0; | |
254 | break; | |
255 | case IRQ_SSP2: | |
256 | mask = ADXER_MFP_WSSP2; | |
257 | break; | |
258 | case IRQ_I2C: | |
259 | mask = ADXER_MFP_WI2C; | |
260 | break; | |
261 | case IRQ_STUART: | |
262 | mask = ADXER_MFP_WUART3; | |
263 | break; | |
264 | case IRQ_BTUART: | |
265 | mask = ADXER_MFP_WUART2; | |
266 | break; | |
267 | case IRQ_FFUART: | |
268 | mask = ADXER_MFP_WUART1; | |
269 | break; | |
270 | case IRQ_MMC: | |
271 | mask = ADXER_MFP_WMMC1; | |
272 | break; | |
273 | case IRQ_SSP: | |
274 | mask = ADXER_MFP_WSSP1; | |
275 | break; | |
276 | case IRQ_RTCAlrm: | |
277 | mask = ADXER_WRTC; | |
278 | break; | |
279 | case IRQ_SSP4: | |
280 | mask = ADXER_MFP_WSSP4; | |
281 | break; | |
282 | case IRQ_TSI: | |
283 | mask = ADXER_WTSI; | |
284 | break; | |
285 | case IRQ_USIM2: | |
286 | mask = ADXER_WUSIM1; | |
287 | break; | |
288 | case IRQ_MMC2: | |
289 | mask = ADXER_MFP_WMMC2; | |
290 | break; | |
291 | case IRQ_NAND: | |
292 | mask = ADXER_MFP_WFLASH; | |
293 | break; | |
294 | case IRQ_USB2: | |
295 | mask = ADXER_WUSB2; | |
296 | break; | |
297 | case IRQ_WAKEUP0: | |
298 | mask = ADXER_WEXTWAKE0; | |
299 | break; | |
300 | case IRQ_WAKEUP1: | |
301 | mask = ADXER_WEXTWAKE1; | |
302 | break; | |
303 | case IRQ_MMC3: | |
304 | mask = ADXER_MFP_GEN12; | |
305 | break; | |
e1217707 MB |
306 | default: |
307 | return -EINVAL; | |
7b5dea12 RK |
308 | } |
309 | ||
310 | local_irq_save(flags); | |
311 | if (on) | |
312 | wakeup_src |= mask; | |
313 | else | |
314 | wakeup_src &= ~mask; | |
315 | local_irq_restore(flags); | |
316 | ||
317 | return 0; | |
318 | } | |
7b5dea12 RK |
319 | #else |
320 | static inline void pxa3xx_init_pm(void) {} | |
b9e25ace | 321 | #define pxa3xx_set_wake NULL |
7b5dea12 RK |
322 | #endif |
323 | ||
a3f4c927 | 324 | static void pxa_ack_ext_wakeup(struct irq_data *d) |
bf293aec | 325 | { |
a3f4c927 | 326 | PECR |= PECR_IS(d->irq - IRQ_WAKEUP0); |
bf293aec MR |
327 | } |
328 | ||
a3f4c927 | 329 | static void pxa_mask_ext_wakeup(struct irq_data *d) |
bf293aec | 330 | { |
a3f4c927 LB |
331 | ICMR2 &= ~(1 << ((d->irq - PXA_IRQ(0)) & 0x1f)); |
332 | PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); | |
bf293aec MR |
333 | } |
334 | ||
a3f4c927 | 335 | static void pxa_unmask_ext_wakeup(struct irq_data *d) |
bf293aec | 336 | { |
a3f4c927 LB |
337 | ICMR2 |= 1 << ((d->irq - PXA_IRQ(0)) & 0x1f); |
338 | PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); | |
bf293aec MR |
339 | } |
340 | ||
a3f4c927 | 341 | static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type) |
12882096 IG |
342 | { |
343 | if (flow_type & IRQ_TYPE_EDGE_RISING) | |
a3f4c927 | 344 | PWER |= 1 << (d->irq - IRQ_WAKEUP0); |
12882096 IG |
345 | |
346 | if (flow_type & IRQ_TYPE_EDGE_FALLING) | |
a3f4c927 | 347 | PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2); |
12882096 IG |
348 | |
349 | return 0; | |
350 | } | |
351 | ||
bf293aec MR |
352 | static struct irq_chip pxa_ext_wakeup_chip = { |
353 | .name = "WAKEUP", | |
a3f4c927 LB |
354 | .irq_ack = pxa_ack_ext_wakeup, |
355 | .irq_mask = pxa_mask_ext_wakeup, | |
356 | .irq_unmask = pxa_unmask_ext_wakeup, | |
357 | .irq_set_type = pxa_set_ext_wakeup_type, | |
bf293aec MR |
358 | }; |
359 | ||
360 | static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) | |
361 | { | |
362 | int irq; | |
363 | ||
364 | for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { | |
f38c02f3 TG |
365 | irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, |
366 | handle_edge_irq); | |
bf293aec MR |
367 | set_irq_flags(irq, IRQF_VALID); |
368 | } | |
369 | ||
a3f4c927 | 370 | pxa_ext_wakeup_chip.irq_set_wake = fn; |
bf293aec MR |
371 | } |
372 | ||
2c8086a5 | 373 | void __init pxa3xx_init_irq(void) |
374 | { | |
375 | /* enable CP6 access */ | |
376 | u32 value; | |
377 | __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); | |
378 | value |= (1 << 6); | |
379 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); | |
380 | ||
b9e25ace | 381 | pxa_init_irq(56, pxa3xx_set_wake); |
bf293aec | 382 | pxa_init_ext_wakeup_irq(pxa3xx_set_wake); |
a58fbcd8 | 383 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); |
2c8086a5 | 384 | } |
385 | ||
851982c1 MV |
386 | static struct map_desc pxa3xx_io_desc[] __initdata = { |
387 | { /* Mem Ctl */ | |
ad68bb9f MV |
388 | .virtual = SMEMC_VIRT, |
389 | .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), | |
851982c1 MV |
390 | .length = 0x00200000, |
391 | .type = MT_DEVICE | |
392 | } | |
393 | }; | |
394 | ||
395 | void __init pxa3xx_map_io(void) | |
396 | { | |
397 | pxa_map_io(); | |
398 | iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); | |
399 | pxa3xx_get_clk_frequency_khz(1); | |
400 | } | |
401 | ||
2c8086a5 | 402 | /* |
403 | * device registration specific to PXA3xx. | |
404 | */ | |
405 | ||
9ba63c4f MR |
406 | void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) |
407 | { | |
14758220 | 408 | pxa_register_device(&pxa3xx_device_i2c_power, info); |
9ba63c4f MR |
409 | } |
410 | ||
2c8086a5 | 411 | static struct platform_device *devices[] __initdata = { |
94c35a6b | 412 | &pxa27x_device_udc, |
09a5358d | 413 | &pxa_device_pmu, |
2c8086a5 | 414 | &pxa_device_i2s, |
f0fba2ad LG |
415 | &pxa_device_asoc_ssp1, |
416 | &pxa_device_asoc_ssp2, | |
417 | &pxa_device_asoc_ssp3, | |
418 | &pxa_device_asoc_ssp4, | |
419 | &pxa_device_asoc_platform, | |
72493146 | 420 | &sa1100_device_rtc, |
2c8086a5 | 421 | &pxa_device_rtc, |
d8e0db11 | 422 | &pxa27x_device_ssp1, |
423 | &pxa27x_device_ssp2, | |
424 | &pxa27x_device_ssp3, | |
425 | &pxa3xx_device_ssp4, | |
75540c1a | 426 | &pxa27x_device_pwm0, |
427 | &pxa27x_device_pwm1, | |
2c8086a5 | 428 | }; |
429 | ||
c0165504 | 430 | static struct sys_device pxa3xx_sysdev[] = { |
431 | { | |
c0165504 | 432 | .cls = &pxa_irq_sysclass, |
4be35e23 | 433 | }, { |
434 | .cls = &pxa3xx_mfp_sysclass, | |
16dfdbf0 | 435 | }, { |
436 | .cls = &pxa_gpio_sysclass, | |
aae8224d EM |
437 | }, { |
438 | .cls = &pxa3xx_clock_sysclass, | |
439 | } | |
c0165504 | 440 | }; |
441 | ||
2c8086a5 | 442 | static int __init pxa3xx_init(void) |
443 | { | |
c0165504 | 444 | int i, ret = 0; |
2c8086a5 | 445 | |
446 | if (cpu_is_pxa3xx()) { | |
04fef228 EM |
447 | |
448 | reset_status = ARSR; | |
449 | ||
86260f98 DK |
450 | /* |
451 | * clear RDH bit every time after reset | |
452 | * | |
453 | * Note: the last 3 bits DxS are write-1-to-clear so carefully | |
454 | * preserve them here in case they will be referenced later | |
455 | */ | |
456 | ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); | |
457 | ||
0a0300dc | 458 | clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); |
2c8086a5 | 459 | |
fef1f99a | 460 | if ((ret = pxa_init_dma(IRQ_DMA, 32))) |
2c8086a5 | 461 | return ret; |
462 | ||
7b5dea12 RK |
463 | pxa3xx_init_pm(); |
464 | ||
c0165504 | 465 | for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { |
466 | ret = sysdev_register(&pxa3xx_sysdev[i]); | |
467 | if (ret) | |
468 | pr_err("failed to register sysdev[%d]\n", i); | |
469 | } | |
470 | ||
471 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); | |
2c8086a5 | 472 | } |
c0165504 | 473 | |
474 | return ret; | |
2c8086a5 | 475 | } |
476 | ||
1c104e0e | 477 | postcore_initcall(pxa3xx_init); |