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Commit | Line | Data |
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b1d907f9 | 1 | /* |
2 | * Static Memory Controller | |
3 | */ | |
4 | ||
5 | #include <linux/module.h> | |
6 | #include <linux/kernel.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/io.h> | |
9 | #include <linux/sysdev.h> | |
10 | ||
11 | #define SMEMC_PHYS_BASE (0x4A000000) | |
12 | #define SMEMC_PHYS_SIZE (0x90) | |
13 | ||
14 | #define MSC0 (0x08) /* Static Memory Controller Register 0 */ | |
15 | #define MSC1 (0x0C) /* Static Memory Controller Register 1 */ | |
16 | #define SXCNFG (0x1C) /* Synchronous Static Memory Control Register */ | |
17 | #define MEMCLKCFG (0x68) /* Clock Configuration */ | |
18 | #define CSADRCFG0 (0x80) /* Address Configuration Register for CS0 */ | |
19 | #define CSADRCFG1 (0x84) /* Address Configuration Register for CS1 */ | |
20 | #define CSADRCFG2 (0x88) /* Address Configuration Register for CS2 */ | |
21 | #define CSADRCFG3 (0x8C) /* Address Configuration Register for CS3 */ | |
22 | ||
23 | #ifdef CONFIG_PM | |
24 | static void __iomem *smemc_mmio_base; | |
25 | ||
26 | static unsigned long msc[2]; | |
27 | static unsigned long sxcnfg, memclkcfg; | |
28 | static unsigned long csadrcfg[4]; | |
29 | ||
30 | static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state) | |
31 | { | |
32 | msc[0] = __raw_readl(smemc_mmio_base + MSC0); | |
33 | msc[1] = __raw_readl(smemc_mmio_base + MSC1); | |
34 | sxcnfg = __raw_readl(smemc_mmio_base + SXCNFG); | |
35 | memclkcfg = __raw_readl(smemc_mmio_base + MEMCLKCFG); | |
36 | csadrcfg[0] = __raw_readl(smemc_mmio_base + CSADRCFG0); | |
37 | csadrcfg[1] = __raw_readl(smemc_mmio_base + CSADRCFG1); | |
38 | csadrcfg[2] = __raw_readl(smemc_mmio_base + CSADRCFG2); | |
39 | csadrcfg[3] = __raw_readl(smemc_mmio_base + CSADRCFG3); | |
40 | ||
41 | return 0; | |
42 | } | |
43 | ||
44 | static int pxa3xx_smemc_resume(struct sys_device *dev) | |
45 | { | |
46 | __raw_writel(msc[0], smemc_mmio_base + MSC0); | |
47 | __raw_writel(msc[1], smemc_mmio_base + MSC1); | |
48 | __raw_writel(sxcnfg, smemc_mmio_base + SXCNFG); | |
49 | __raw_writel(memclkcfg, smemc_mmio_base + MEMCLKCFG); | |
50 | __raw_writel(csadrcfg[0], smemc_mmio_base + CSADRCFG0); | |
51 | __raw_writel(csadrcfg[1], smemc_mmio_base + CSADRCFG1); | |
52 | __raw_writel(csadrcfg[2], smemc_mmio_base + CSADRCFG2); | |
53 | __raw_writel(csadrcfg[3], smemc_mmio_base + CSADRCFG3); | |
54 | ||
55 | return 0; | |
56 | } | |
57 | ||
58 | static struct sysdev_class smemc_sysclass = { | |
59 | .name = "smemc", | |
60 | .suspend = pxa3xx_smemc_suspend, | |
61 | .resume = pxa3xx_smemc_resume, | |
62 | }; | |
63 | ||
64 | static struct sys_device smemc_sysdev = { | |
65 | .id = 0, | |
66 | .cls = &smemc_sysclass, | |
67 | }; | |
68 | ||
69 | static int __init smemc_init(void) | |
70 | { | |
71 | int ret = 0; | |
72 | ||
73 | if (cpu_is_pxa3xx()) { | |
74 | smemc_mmio_base = ioremap(SMEMC_PHYS_BASE, SMEMC_PHYS_SIZE); | |
75 | if (smemc_mmio_base == NULL) | |
76 | return -ENODEV; | |
77 | ||
78 | ret = sysdev_class_register(&smemc_sysclass); | |
79 | if (ret) | |
80 | return ret; | |
81 | ||
82 | ret = sysdev_register(&smemc_sysdev); | |
83 | } | |
84 | ||
85 | return ret; | |
86 | } | |
87 | subsys_initcall(smemc_init); | |
88 | #endif |