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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
b1d907f9 | 2 | /* |
3 | * Static Memory Controller | |
4 | */ | |
5 | ||
6 | #include <linux/module.h> | |
7 | #include <linux/kernel.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/io.h> | |
2eaa03b5 | 10 | #include <linux/syscore_ops.h> |
b1d907f9 | 11 | |
05678a96 | 12 | #include <mach/hardware.h> |
ad68bb9f | 13 | #include <mach/smemc.h> |
b1d907f9 | 14 | |
15 | #ifdef CONFIG_PM | |
b1d907f9 | 16 | static unsigned long msc[2]; |
17 | static unsigned long sxcnfg, memclkcfg; | |
18 | static unsigned long csadrcfg[4]; | |
19 | ||
2eaa03b5 | 20 | static int pxa3xx_smemc_suspend(void) |
b1d907f9 | 21 | { |
ad68bb9f MV |
22 | msc[0] = __raw_readl(MSC0); |
23 | msc[1] = __raw_readl(MSC1); | |
24 | sxcnfg = __raw_readl(SXCNFG); | |
25 | memclkcfg = __raw_readl(MEMCLKCFG); | |
26 | csadrcfg[0] = __raw_readl(CSADRCFG0); | |
27 | csadrcfg[1] = __raw_readl(CSADRCFG1); | |
28 | csadrcfg[2] = __raw_readl(CSADRCFG2); | |
29 | csadrcfg[3] = __raw_readl(CSADRCFG3); | |
b1d907f9 | 30 | |
31 | return 0; | |
32 | } | |
33 | ||
2eaa03b5 | 34 | static void pxa3xx_smemc_resume(void) |
b1d907f9 | 35 | { |
ad68bb9f MV |
36 | __raw_writel(msc[0], MSC0); |
37 | __raw_writel(msc[1], MSC1); | |
38 | __raw_writel(sxcnfg, SXCNFG); | |
39 | __raw_writel(memclkcfg, MEMCLKCFG); | |
40 | __raw_writel(csadrcfg[0], CSADRCFG0); | |
41 | __raw_writel(csadrcfg[1], CSADRCFG1); | |
42 | __raw_writel(csadrcfg[2], CSADRCFG2); | |
43 | __raw_writel(csadrcfg[3], CSADRCFG3); | |
d107a204 IG |
44 | /* CSMSADRCFG wakes up in its default state (0), so we need to set it */ |
45 | __raw_writel(0x2, CSMSADRCFG); | |
b1d907f9 | 46 | } |
47 | ||
2eaa03b5 | 48 | static struct syscore_ops smemc_syscore_ops = { |
b1d907f9 | 49 | .suspend = pxa3xx_smemc_suspend, |
50 | .resume = pxa3xx_smemc_resume, | |
51 | }; | |
52 | ||
b1d907f9 | 53 | static int __init smemc_init(void) |
54 | { | |
d107a204 IG |
55 | if (cpu_is_pxa3xx()) { |
56 | /* | |
57 | * The only documentation we have on the | |
58 | * Chip Select Configuration Register (CSMSADRCFG) is that | |
59 | * it must be programmed to 0x2. | |
60 | * Moreover, in the bit definitions, the second bit | |
61 | * (CSMSADRCFG[1]) is called "SETALWAYS". | |
62 | * Other bits are reserved in this register. | |
63 | */ | |
64 | __raw_writel(0x2, CSMSADRCFG); | |
65 | ||
2eaa03b5 | 66 | register_syscore_ops(&smemc_syscore_ops); |
d107a204 | 67 | } |
b1d907f9 | 68 | |
2eaa03b5 | 69 | return 0; |
b1d907f9 | 70 | } |
71 | subsys_initcall(smemc_init); | |
72 | #endif |