projects / mirror_ubuntu-hirsute-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 352699a3 MZ |
2 | /* |
| 3 | * arch/arm/mach-pxa/include/mach/viper.h | |
| 4 | * | |
| 5 | * Author: Ian Campbell | |
| 6 | * Created: Feb 03, 2003 | |
| 7 | * Copyright: Arcom Control Systems. | |
| 8 | * | |
| 9 | * Maintained by Marc Zyngier <maz@misterjones.org> | |
| 10 | * <marc.zyngier@altran.com> | |
| 11 | * | |
| 12 | * Created based on lubbock.h: | |
| 13 | * Author: Nicolas Pitre | |
| 14 | * Created: Jun 15, 2001 | |
| 15 | * Copyright: MontaVista Software Inc. | |
| 352699a3 MZ |
16 | */ |
| 17 | ||
| 18 | #ifndef ARCH_VIPER_H | |
| 19 | #define ARCH_VIPER_H | |
| 20 | ||
| 21 | #define VIPER_BOOT_PHYS PXA_CS0_PHYS | |
| 22 | #define VIPER_FLASH_PHYS PXA_CS1_PHYS | |
| 23 | #define VIPER_ETH_PHYS PXA_CS2_PHYS | |
| 24 | #define VIPER_USB_PHYS PXA_CS3_PHYS | |
| 25 | #define VIPER_ETH_DATA_PHYS PXA_CS4_PHYS | |
| 26 | #define VIPER_CPLD_PHYS PXA_CS5_PHYS | |
| 27 | ||
| 28 | #define VIPER_CPLD_BASE (0xf0000000) | |
| 29 | #define VIPER_PC104IO_BASE (0xf1000000) | |
| 30 | #define VIPER_USB_BASE (0xf1800000) | |
| 31 | ||
| 32 | #define VIPER_ETH_GPIO (0) | |
| 33 | #define VIPER_CPLD_GPIO (1) | |
| 34 | #define VIPER_USB_GPIO (2) | |
| 35 | #define VIPER_UARTA_GPIO (4) | |
| 36 | #define VIPER_UARTB_GPIO (3) | |
| 37 | #define VIPER_CF_CD_GPIO (32) | |
| 38 | #define VIPER_CF_RDY_GPIO (8) | |
| 39 | #define VIPER_BCKLIGHT_EN_GPIO (9) | |
| 40 | #define VIPER_LCD_EN_GPIO (10) | |
| 41 | #define VIPER_PSU_DATA_GPIO (6) | |
| 42 | #define VIPER_PSU_CLK_GPIO (11) | |
| 43 | #define VIPER_UART_SHDN_GPIO (12) | |
| 44 | #define VIPER_BRIGHTNESS_GPIO (16) | |
| 45 | #define VIPER_PSU_nCS_LD_GPIO (19) | |
| 46 | #define VIPER_UPS_GPIO (20) | |
| 47 | #define VIPER_CF_POWER_GPIO (82) | |
| 48 | #define VIPER_TPM_I2C_SDA_GPIO (26) | |
| 49 | #define VIPER_TPM_I2C_SCL_GPIO (27) | |
| 50 | #define VIPER_RTC_I2C_SDA_GPIO (83) | |
| 51 | #define VIPER_RTC_I2C_SCL_GPIO (84) | |
| 52 | ||
| 53 | #define VIPER_CPLD_P2V(x) ((x) - VIPER_CPLD_PHYS + VIPER_CPLD_BASE) | |
| 54 | #define VIPER_CPLD_V2P(x) ((x) - VIPER_CPLD_BASE + VIPER_CPLD_PHYS) | |
| 55 | ||
| 56 | #ifndef __ASSEMBLY__ | |
| 57 | # define __VIPER_CPLD_REG(x) (*((volatile u16 *)VIPER_CPLD_P2V(x))) | |
| 58 | #endif | |
| 59 | ||
| 60 | /* board level registers in the CPLD: (offsets from CPLD_BASE) ... */ | |
| 61 | ||
| 62 | /* ... Physical addresses */ | |
| 63 | #define _VIPER_LO_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100000) | |
| 64 | #define _VIPER_ICR_PHYS (VIPER_CPLD_PHYS + 0x100002) | |
| 65 | #define _VIPER_HI_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100004) | |
| 66 | #define _VIPER_VERSION_PHYS (VIPER_CPLD_PHYS + 0x100006) | |
| 67 | #define VIPER_UARTA_PHYS (VIPER_CPLD_PHYS + 0x300010) | |
| 68 | #define VIPER_UARTB_PHYS (VIPER_CPLD_PHYS + 0x300000) | |
| 69 | #define _VIPER_SRAM_BASE (VIPER_CPLD_PHYS + 0x800000) | |
| 70 | ||
| 71 | /* ... Virtual addresses */ | |
| 72 | #define VIPER_LO_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_LO_IRQ_STATUS) | |
| 73 | #define VIPER_HI_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_HI_IRQ_STATUS) | |
| 74 | #define VIPER_VERSION __VIPER_CPLD_REG(_VIPER_VERSION_PHYS) | |
| 75 | #define VIPER_ICR __VIPER_CPLD_REG(_VIPER_ICR_PHYS) | |
| 76 | ||
| 77 | /* Decode VIPER_VERSION register */ | |
| 78 | #define VIPER_CPLD_REVISION(x) (((x) >> 5) & 0x7) | |
| 79 | #define VIPER_BOARD_VERSION(x) (((x) >> 3) & 0x3) | |
| 80 | #define VIPER_BOARD_ISSUE(x) (((x) >> 0) & 0x7) | |
| 81 | ||
| 82 | /* Interrupt and Configuration Register (VIPER_ICR) */ | |
| 83 | /* This is a write only register. Only CF_RST is used under Linux */ | |
| 84 | ||
| 352699a3 MZ |
85 | #define VIPER_ICR_RETRIG (1 << 0) |
| 86 | #define VIPER_ICR_AUTO_CLR (1 << 1) | |
| 87 | #define VIPER_ICR_R_DIS (1 << 2) | |
| 88 | #define VIPER_ICR_CF_RST (1 << 3) | |
| 89 | ||
| 90 | #endif | |
| 91 |