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[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-pxa / zeus.c
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e491a11c
MZ		 1/*
2 * Support for the Arcom ZEUS.
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * Loosely based on Arcom's 2.6.16.28.
7 * Maintained by Marc Zyngier <maz@misterjones.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/cpufreq.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/pm.h>
18#include <linux/gpio.h>
19#include <linux/serial_8250.h>
20#include <linux/dm9000.h>
21#include <linux/mmc/host.h>
22#include <linux/spi/spi.h>
8348c259 23#include <linux/spi/pxa2xx_spi.h>
e491a11c
MZ		 24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h>
26#include <linux/mtd/physmap.h>
27#include <linux/i2c.h>
b459396e 28#include <linux/i2c/pxa-i2c.h>
5877457a 29#include <linux/platform_data/pca953x.h>
a1916eb0 30#include <linux/apm-emulation.h>
438a22fe 31#include <linux/can/platform/mcp251x.h>
1ddff7da
AS		 32#include <linux/regulator/fixed.h>
33#include <linux/regulator/machine.h>
e491a11c
MZ		 34
35#include <asm/mach-types.h>
2c74a0ce 36#include <asm/suspend.h>
9f97da78 37#include <asm/system_info.h>
e491a11c
MZ		 38#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40
ca0e687c 41#include <mach/pxa27x.h>
e491a11c 42#include <mach/regs-uart.h>
293b2da1
AB		 43#include <linux/platform_data/usb-ohci-pxa27x.h>
44#include <linux/platform_data/mmc-pxamci.h>
e491a11c
MZ		 45#include <mach/pxa27x-udc.h>
46#include <mach/udc.h>
293b2da1 47#include <linux/platform_data/video-pxafb.h>
e491a11c
MZ		 48#include <mach/pm.h>
49#include <mach/audio.h>
293b2da1 50#include <linux/platform_data/pcmcia-pxa2xx_viper.h>
e491a11c 51#include <mach/zeus.h>
ad68bb9f 52#include <mach/smemc.h>
e491a11c
MZ		 53
54#include "generic.h"
55
56/*
57 * Interrupt handling
58 */
59
60static unsigned long zeus_irq_enabled_mask;
61static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
62static const int zeus_isa_irq_map[] = {
63 0, /* ISA irq #0, invalid */
64 0, /* ISA irq #1, invalid */
65 0, /* ISA irq #2, invalid */
66 1 << 0, /* ISA irq #3 */
67 1 << 1, /* ISA irq #4 */
68 1 << 2, /* ISA irq #5 */
69 1 << 3, /* ISA irq #6 */
70 1 << 4, /* ISA irq #7 */
71 0, /* ISA irq #8, invalid */
72 0, /* ISA irq #9, invalid */
73 1 << 5, /* ISA irq #10 */
74 1 << 6, /* ISA irq #11 */
75 1 << 7, /* ISA irq #12 */
76};
77
78static inline int zeus_irq_to_bitmask(unsigned int irq)
79{
80 return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
81}
82
83static inline int zeus_bit_to_irq(int bit)
84{
85 return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
86}
87
a3f4c927 88static void zeus_ack_irq(struct irq_data *d)
e491a11c 89{
a3f4c927 90 __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
e491a11c
MZ		 91}
92
a3f4c927 93static void zeus_mask_irq(struct irq_data *d)
e491a11c 94{
a3f4c927 95 zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
e491a11c
MZ		 96}
97
a3f4c927 98static void zeus_unmask_irq(struct irq_data *d)
e491a11c 99{
a3f4c927 100 zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
e491a11c
MZ		 101}
102
103static inline unsigned long zeus_irq_pending(void)
104{
105 return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
106}
107
108static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc)
109{
110 unsigned long pending;
111
112 pending = zeus_irq_pending();
113 do {
114 /* we're in a chained irq handler,
115 * so ack the interrupt by hand */
a3f4c927 116 desc->irq_data.chip->irq_ack(&desc->irq_data);
e491a11c
MZ		 117
118 if (likely(pending)) {
119 irq = zeus_bit_to_irq(__ffs(pending));
120 generic_handle_irq(irq);
121 }
122 pending = zeus_irq_pending();
123 } while (pending);
124}
125
126static struct irq_chip zeus_irq_chip = {
a3f4c927
LB		 127 .name = "ISA",
128 .irq_ack = zeus_ack_irq,
129 .irq_mask = zeus_mask_irq,
130 .irq_unmask = zeus_unmask_irq,
e491a11c
MZ		 131};
132
133static void __init zeus_init_irq(void)
134{
135 int level;
136 int isa_irq;
137
138 pxa27x_init_irq();
139
140 /* Peripheral IRQs. It would be nice to move those inside driver
141 configuration, but it is not supported at the moment. */
6845664a
TG		 142 irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
143 irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
144 irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
145 irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
146 IRQ_TYPE_EDGE_FALLING);
147 irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
e491a11c
MZ		 148
149 /* Setup ISA IRQs */
150 for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
151 isa_irq = zeus_bit_to_irq(level);
f38c02f3
TG		 152 irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
153 handle_edge_irq);
e491a11c
MZ		 154 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
155 }
156
6845664a
TG		 157 irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
158 irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
e491a11c
MZ		 159}
160
161
162/*
163 * Platform devices
164 */
165
166/* Flash */
167static struct resource zeus_mtd_resources[] = {
168 [0] = { /* NOR Flash (up to 64MB) */
169 .start = ZEUS_FLASH_PHYS,
170 .end = ZEUS_FLASH_PHYS + SZ_64M - 1,
171 .flags = IORESOURCE_MEM,
172 },
173 [1] = { /* SRAM */
174 .start = ZEUS_SRAM_PHYS,
175 .end = ZEUS_SRAM_PHYS + SZ_512K - 1,
176 .flags = IORESOURCE_MEM,
177 },
178};
179
180static struct physmap_flash_data zeus_flash_data[] = {
181 [0] = {
182 .width = 2,
183 .parts = NULL,
184 .nr_parts = 0,
185 },
186};
187
188static struct platform_device zeus_mtd_devices[] = {
189 [0] = {
190 .name = "physmap-flash",
191 .id = 0,
192 .dev = {
193 .platform_data = &zeus_flash_data[0],
194 },
195 .resource = &zeus_mtd_resources[0],
196 .num_resources = 1,
197 },
198};
199
200/* Serial */
201static struct resource zeus_serial_resources[] = {
202 {
203 .start = 0x10000000,
204 .end = 0x1000000f,
205 .flags = IORESOURCE_MEM,
206 },
207 {
208 .start = 0x10800000,
209 .end = 0x1080000f,
210 .flags = IORESOURCE_MEM,
211 },
212 {
213 .start = 0x11000000,
214 .end = 0x1100000f,
215 .flags = IORESOURCE_MEM,
216 },
217 {
218 .start = 0x40100000,
219 .end = 0x4010001f,
220 .flags = IORESOURCE_MEM,
221 },
222 {
223 .start = 0x40200000,
224 .end = 0x4020001f,
225 .flags = IORESOURCE_MEM,
226 },
227 {
228 .start = 0x40700000,
229 .end = 0x4070001f,
230 .flags = IORESOURCE_MEM,
231 },
232};
233
234static struct plat_serial8250_port serial_platform_data[] = {
235 /* External UARTs */
236 /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
237 { /* COM1 */
238 .mapbase = 0x10000000,
4929f5a8 239 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO),
e491a11c
MZ		 240 .irqflags = IRQF_TRIGGER_RISING,
241 .uartclk = 14745600,
242 .regshift = 1,
243 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
244 .iotype = UPIO_MEM,
245 },
246 { /* COM2 */
247 .mapbase = 0x10800000,
4929f5a8 248 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO),
e491a11c
MZ		 249 .irqflags = IRQF_TRIGGER_RISING,
250 .uartclk = 14745600,
251 .regshift = 1,
252 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
253 .iotype = UPIO_MEM,
254 },
255 { /* COM3 */
256 .mapbase = 0x11000000,
4929f5a8 257 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO),
e491a11c
MZ		 258 .irqflags = IRQF_TRIGGER_RISING,
259 .uartclk = 14745600,
260 .regshift = 1,
261 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
262 .iotype = UPIO_MEM,
263 },
264 { /* COM4 */
265 .mapbase = 0x11800000,
4929f5a8 266 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO),
e491a11c
MZ		 267 .irqflags = IRQF_TRIGGER_RISING,
268 .uartclk = 14745600,
269 .regshift = 1,
270 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
271 .iotype = UPIO_MEM,
272 },
273 /* Internal UARTs */
274 { /* FFUART */
275 .membase = (void *)&FFUART,
276 .mapbase = __PREG(FFUART),
277 .irq = IRQ_FFUART,
278 .uartclk = 921600 * 16,
279 .regshift = 2,
280 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
281 .iotype = UPIO_MEM,
282 },
283 { /* BTUART */
284 .membase = (void *)&BTUART,
285 .mapbase = __PREG(BTUART),
286 .irq = IRQ_BTUART,
287 .uartclk = 921600 * 16,
288 .regshift = 2,
289 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
290 .iotype = UPIO_MEM,
291 },
292 { /* STUART */
293 .membase = (void *)&STUART,
294 .mapbase = __PREG(STUART),
295 .irq = IRQ_STUART,
296 .uartclk = 921600 * 16,
297 .regshift = 2,
298 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
299 .iotype = UPIO_MEM,
300 },
301 { },
302};
303
304static struct platform_device zeus_serial_device = {
305 .name = "serial8250",
306 .id = PLAT8250_DEV_PLATFORM,
307 .dev = {
308 .platform_data = serial_platform_data,
309 },
310 .num_resources = ARRAY_SIZE(zeus_serial_resources),
311 .resource = zeus_serial_resources,
312};
313
314/* Ethernet */
315static struct resource zeus_dm9k0_resource[] = {
316 [0] = {
317 .start = ZEUS_ETH0_PHYS,
318 .end = ZEUS_ETH0_PHYS + 1,
319 .flags = IORESOURCE_MEM
320 },
321 [1] = {
322 .start = ZEUS_ETH0_PHYS + 2,
323 .end = ZEUS_ETH0_PHYS + 3,
324 .flags = IORESOURCE_MEM
325 },
326 [2] = {
4929f5a8
HZ		 327 .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
328 .end = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
e491a11c
MZ		 329 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
330 },
331};
332
333static struct resource zeus_dm9k1_resource[] = {
334 [0] = {
335 .start = ZEUS_ETH1_PHYS,
336 .end = ZEUS_ETH1_PHYS + 1,
337 .flags = IORESOURCE_MEM
338 },
339 [1] = {
340 .start = ZEUS_ETH1_PHYS + 2,
341 .end = ZEUS_ETH1_PHYS + 3,
342 .flags = IORESOURCE_MEM,
343 },
344 [2] = {
4929f5a8
HZ		 345 .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
346 .end = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
e491a11c
MZ		 347 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
348 },
349};
350
351static struct dm9000_plat_data zeus_dm9k_platdata = {
352 .flags = DM9000_PLATF_16BITONLY,
353};
354
355static struct platform_device zeus_dm9k0_device = {
356 .name = "dm9000",
357 .id = 0,
358 .num_resources = ARRAY_SIZE(zeus_dm9k0_resource),
359 .resource = zeus_dm9k0_resource,
360 .dev = {
361 .platform_data = &zeus_dm9k_platdata,
362 }
363};
364
365static struct platform_device zeus_dm9k1_device = {
366 .name = "dm9000",
367 .id = 1,
368 .num_resources = ARRAY_SIZE(zeus_dm9k1_resource),
369 .resource = zeus_dm9k1_resource,
370 .dev = {
371 .platform_data = &zeus_dm9k_platdata,
372 }
373};
374
375/* External SRAM */
376static struct resource zeus_sram_resource = {
377 .start = ZEUS_SRAM_PHYS,
378 .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
379 .flags = IORESOURCE_MEM,
380};
381
382static struct platform_device zeus_sram_device = {
383 .name = "pxa2xx-8bit-sram",
384 .id = 0,
385 .num_resources = 1,
386 .resource = &zeus_sram_resource,
387};
388
389/* SPI interface on SSP3 */
390static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
391 .num_chipselect = 1,
392 .enable_dma = 1,
393};
394
438a22fe 395/* CAN bus on SPI */
1ddff7da
AS		 396static struct regulator_consumer_supply can_regulator_consumer =
397 REGULATOR_SUPPLY("vdd", "spi3.0");
438a22fe 398
1ddff7da
AS		 399static struct regulator_init_data can_regulator_init_data = {
400 .constraints = {
401 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
402 },
403 .consumer_supplies = &can_regulator_consumer,
404 .num_consumer_supplies = 1,
405};
438a22fe 406
1ddff7da
AS		 407static struct fixed_voltage_config can_regulator_pdata = {
408 .supply_name = "CAN_SHDN",
409 .microvolts = 3300000,
410 .gpio = ZEUS_CAN_SHDN_GPIO,
411 .init_data = &can_regulator_init_data,
412};
438a22fe 413
1ddff7da
AS		 414static struct platform_device can_regulator_device = {
415 .name = "reg-fixed-volage",
541e00ae 416 .id = 0,
1ddff7da
AS		 417 .dev = {
418 .platform_data = &can_regulator_pdata,
419 },
420};
438a22fe
MZ		 421
422static struct mcp251x_platform_data zeus_mcp2515_pdata = {
423 .oscillator_frequency = 16*1000*1000,
438a22fe
MZ		 424};
425
426static struct spi_board_info zeus_spi_board_info[] = {
427 [0] = {
e446630c 428 .modalias = "mcp2515",
438a22fe 429 .platform_data = &zeus_mcp2515_pdata,
4929f5a8 430 .irq = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
438a22fe
MZ		 431 .max_speed_hz = 1*1000*1000,
432 .bus_num = 3,
433 .mode = SPI_MODE_0,
434 .chip_select = 0,
e491a11c
MZ		 435 },
436};
437
438/* Leds */
439static struct gpio_led zeus_leds[] = {
440 [0] = {
441 .name = "zeus:yellow:1",
442 .default_trigger = "heartbeat",
443 .gpio = ZEUS_EXT0_GPIO(3),
444 .active_low = 1,
445 },
446 [1] = {
447 .name = "zeus:yellow:2",
448 .default_trigger = "default-on",
449 .gpio = ZEUS_EXT0_GPIO(4),
450 .active_low = 1,
451 },
452 [2] = {
453 .name = "zeus:yellow:3",
454 .default_trigger = "default-on",
455 .gpio = ZEUS_EXT0_GPIO(5),
456 .active_low = 1,
457 },
458};
459
460static struct gpio_led_platform_data zeus_leds_info = {
461 .leds = zeus_leds,
462 .num_leds = ARRAY_SIZE(zeus_leds),
463};
464
465static struct platform_device zeus_leds_device = {
466 .name = "leds-gpio",
467 .id = -1,
468 .dev = {
469 .platform_data = &zeus_leds_info,
470 },
471};
472
c2de1c38
MZ		 473static void zeus_cf_reset(int state)
474{
475 u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
476
477 if (state)
478 cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
479 else
480 cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
481
482 __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
483}
484
485static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
486 .cd_gpio = ZEUS_CF_CD_GPIO,
487 .rdy_gpio = ZEUS_CF_RDY_GPIO,
488 .pwr_gpio = ZEUS_CF_PWEN_GPIO,
489 .reset = zeus_cf_reset,
490};
491
492static struct platform_device zeus_pcmcia_device = {
493 .name = "zeus-pcmcia",
494 .id = -1,
495 .dev = {
496 .platform_data = &zeus_pcmcia_info,
497 },
498};
499
fcfdc67f
MZ		 500static struct resource zeus_max6369_resource = {
501 .start = ZEUS_CPLD_EXTWDOG_PHYS,
502 .end = ZEUS_CPLD_EXTWDOG_PHYS,
503 .flags = IORESOURCE_MEM,
504};
505
506struct platform_device zeus_max6369_device = {
507 .name = "max6369_wdt",
508 .id = -1,
509 .resource = &zeus_max6369_resource,
510 .num_resources = 1,
511};
512
e491a11c
MZ		 513/* AC'97 */
514static pxa2xx_audio_ops_t zeus_ac97_info = {
515 .reset_gpio = 95,
516};
517
518
519/*
520 * USB host
521 */
522
541e00ae
LP		 523static struct regulator_consumer_supply zeus_ohci_regulator_supplies[] = {
524 REGULATOR_SUPPLY("vbus2", "pxa27x-ohci"),
525};
e491a11c 526
541e00ae
LP		 527static struct regulator_init_data zeus_ohci_regulator_data = {
528 .constraints = {
529 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
530 },
531 .num_consumer_supplies = ARRAY_SIZE(zeus_ohci_regulator_supplies),
532 .consumer_supplies = zeus_ohci_regulator_supplies,
533};
e491a11c 534
541e00ae
LP		 535static struct fixed_voltage_config zeus_ohci_regulator_config = {
536 .supply_name = "vbus2",
537 .microvolts = 5000000, /* 5.0V */
538 .gpio = ZEUS_USB2_PWREN_GPIO,
539 .enable_high = 1,
540 .startup_delay = 0,
541 .init_data = &zeus_ohci_regulator_data,
542};
e491a11c 543
541e00ae
LP		 544static struct platform_device zeus_ohci_regulator_device = {
545 .name = "reg-fixed-voltage",
546 .id = 1,
547 .dev = {
548 .platform_data = &zeus_ohci_regulator_config,
549 },
550};
e491a11c
MZ		 551
552static struct pxaohci_platform_data zeus_ohci_platform_data = {
553 .port_mode = PMM_NPS_MODE,
7ff27dfa
MZ		 554 /* Clear Power Control Polarity Low and set Power Sense
555 * Polarity Low. Supply power to USB ports. */
556 .flags = ENABLE_PORT_ALL | POWER_SENSE_LOW,
e491a11c
MZ		 557};
558
541e00ae
LP		 559static void zeus_register_ohci(void)
560{
561 /* Port 2 is shared between host and client interface. */
562 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
563
564 pxa_set_ohci_info(&zeus_ohci_platform_data);
565}
566
e491a11c
MZ		 567/*
568 * Flat Panel
569 */
570
571static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
572{
573 gpio_set_value(ZEUS_LCD_EN_GPIO, on);
574}
575
576static void zeus_backlight_power(int on)
577{
578 gpio_set_value(ZEUS_BKLEN_GPIO, on);
579}
580
581static int zeus_setup_fb_gpios(void)
582{
583 int err;
584
585 if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
586 goto out_err;
587
588 if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
589 goto out_err_lcd;
590
591 if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
592 goto out_err_lcd;
593
594 if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
595 goto out_err_bkl;
596
597 return 0;
598
599out_err_bkl:
600 gpio_free(ZEUS_BKLEN_GPIO);
601out_err_lcd:
602 gpio_free(ZEUS_LCD_EN_GPIO);
603out_err:
604 return err;
605}
606
607static struct pxafb_mode_info zeus_fb_mode_info[] = {
608 {
609 .pixclock = 39722,
610
611 .xres = 640,
612 .yres = 480,
613
614 .bpp = 16,
615
616 .hsync_len = 63,
617 .left_margin = 16,
618 .right_margin = 81,
619
620 .vsync_len = 2,
621 .upper_margin = 12,
622 .lower_margin = 31,
623
624 .sync = 0,
625 },
626};
627
628static struct pxafb_mach_info zeus_fb_info = {
629 .modes = zeus_fb_mode_info,
630 .num_modes = 1,
631 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
632 .pxafb_lcd_power = zeus_lcd_power,
633 .pxafb_backlight_power = zeus_backlight_power,
634};
635
636/*
637 * MMC/SD Device
638 *
639 * The card detect interrupt isn't debounced so we delay it by 250ms
640 * to give the card a chance to fully insert/eject.
641 */
642
643static struct pxamci_platform_data zeus_mci_platform_data = {
644 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
f97cab28 645 .detect_delay_ms = 250,
e491a11c
MZ		 646 .gpio_card_detect = ZEUS_MMC_CD_GPIO,
647 .gpio_card_ro = ZEUS_MMC_WP_GPIO,
648 .gpio_card_ro_invert = 1,
649 .gpio_power = -1
650};
651
652/*
653 * USB Device Controller
654 */
655static void zeus_udc_command(int cmd)
656{
657 switch (cmd) {
658 case PXA2XX_UDC_CMD_DISCONNECT:
659 pr_info("zeus: disconnecting USB client\n");
660 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
661 break;
662
663 case PXA2XX_UDC_CMD_CONNECT:
664 pr_info("zeus: connecting USB client\n");
665 UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
666 break;
667 }
668}
669
670static struct pxa2xx_udc_mach_info zeus_udc_info = {
671 .udc_command = zeus_udc_command,
672};
673
541e00ae
LP		 674static struct platform_device *zeus_devices[] __initdata = {
675 &zeus_serial_device,
676 &zeus_mtd_devices[0],
677 &zeus_dm9k0_device,
678 &zeus_dm9k1_device,
679 &zeus_sram_device,
680 &zeus_leds_device,
681 &zeus_pcmcia_device,
682 &zeus_max6369_device,
683 &can_regulator_device,
684 &zeus_ohci_regulator_device,
685};
686
98acdbe4 687#ifdef CONFIG_PM
e491a11c
MZ		 688static void zeus_power_off(void)
689{
690 local_irq_disable();
2c74a0ce 691 cpu_suspend(PWRMODE_DEEPSLEEP, pxa27x_finish_suspend);
e491a11c 692}
98acdbe4
SS		 693#else
694#define zeus_power_off NULL
695#endif
e491a11c 696
a1916eb0
MZ		 697#ifdef CONFIG_APM_EMULATION
698static void zeus_get_power_status(struct apm_power_info *info)
699{
700 /* Power supply is always present */
701 info->ac_line_status = APM_AC_ONLINE;
702 info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT;
703 info->battery_flag = APM_BATTERY_FLAG_NOT_PRESENT;
704}
705
706static inline void zeus_setup_apm(void)
707{
708 apm_get_power_status = zeus_get_power_status;
709}
710#else
711static inline void zeus_setup_apm(void)
712{
713}
714#endif
715
100627b4
MZ		 716static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
717 unsigned ngpio, void *context)
e491a11c
MZ		 718{
719 int i;
720 u8 pcb_info = 0;
721
722 for (i = 0; i < 8; i++) {
723 int pcb_bit = gpio + i + 8;
724
725 if (gpio_request(pcb_bit, "pcb info")) {
726 dev_err(&client->dev, "Can't request pcb info %d\n", i);
727 continue;
728 }
729
730 if (gpio_direction_input(pcb_bit)) {
731 dev_err(&client->dev, "Can't read pcb info %d\n", i);
732 gpio_free(pcb_bit);
733 continue;
734 }
735
736 pcb_info |= !!gpio_get_value(pcb_bit) << i;
737
738 gpio_free(pcb_bit);
739 }
740
741 dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
742 pcb_info >> 4, pcb_info & 0xf);
743
744 return 0;
745}
746
747static struct pca953x_platform_data zeus_pca953x_pdata[] = {
748 [0] = { .gpio_base = ZEUS_EXT0_GPIO_BASE, },
749 [1] = {
750 .gpio_base = ZEUS_EXT1_GPIO_BASE,
751 .setup = zeus_get_pcb_info,
752 },
753 [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
754};
755
756static struct i2c_board_info __initdata zeus_i2c_devices[] = {
757 {
758 I2C_BOARD_INFO("pca9535", 0x21),
759 .platform_data = &zeus_pca953x_pdata[0],
760 },
761 {
762 I2C_BOARD_INFO("pca9535", 0x22),
763 .platform_data = &zeus_pca953x_pdata[1],
764 },
765 {
766 I2C_BOARD_INFO("pca9535", 0x20),
767 .platform_data = &zeus_pca953x_pdata[2],
4929f5a8 768 .irq = PXA_GPIO_TO_IRQ(ZEUS_EXTGPIO_GPIO),
e491a11c
MZ		 769 },
770 { I2C_BOARD_INFO("lm75a", 0x48) },
771 { I2C_BOARD_INFO("24c01", 0x50) },
772 { I2C_BOARD_INFO("isl1208", 0x6f) },
773};
774
775static mfp_cfg_t zeus_pin_config[] __initdata = {
c11b6a42
EM		 776 /* AC97 */
777 GPIO28_AC97_BITCLK,
778 GPIO29_AC97_SDATA_IN_0,
779 GPIO30_AC97_SDATA_OUT,
780 GPIO31_AC97_SYNC,
781
e491a11c
MZ		 782 GPIO15_nCS_1,
783 GPIO78_nCS_2,
784 GPIO80_nCS_4,
785 GPIO33_nCS_5,
786
787 GPIO22_GPIO,
788 GPIO32_MMC_CLK,
789 GPIO92_MMC_DAT_0,
790 GPIO109_MMC_DAT_1,
791 GPIO110_MMC_DAT_2,
792 GPIO111_MMC_DAT_3,
793 GPIO112_MMC_CMD,
794
795 GPIO88_USBH1_PWR,
796 GPIO89_USBH1_PEN,
797 GPIO119_USBH2_PWR,
798 GPIO120_USBH2_PEN,
799
800 GPIO86_LCD_LDD_16,
801 GPIO87_LCD_LDD_17,
802
803 GPIO102_GPIO,
804 GPIO104_CIF_DD_2,
805 GPIO105_CIF_DD_1,
806
438a22fe
MZ		 807 GPIO81_SSP3_TXD,
808 GPIO82_SSP3_RXD,
809 GPIO83_SSP3_SFRM,
810 GPIO84_SSP3_SCLK,
811
e491a11c
MZ		 812 GPIO48_nPOE,
813 GPIO49_nPWE,
814 GPIO50_nPIOR,
815 GPIO51_nPIOW,
816 GPIO85_nPCE_1,
817 GPIO54_nPCE_2,
818 GPIO79_PSKTSEL,
819 GPIO55_nPREG,
820 GPIO56_nPWAIT,
821 GPIO57_nIOIS16,
822 GPIO36_GPIO, /* CF CD */
823 GPIO97_GPIO, /* CF PWREN */
824 GPIO99_GPIO, /* CF RDY */
825};
826
5f86ceba
MZ		 827/*
828 * DM9k MSCx settings: SRAM, 16 bits
829 * 17 cycles delay first access
830 * 5 cycles delay next access
831 * 13 cycles recovery time
832 * faster device
833 */
834#define DM9K_MSC_VALUE 0xe4c9
835
e491a11c
MZ		 836static void __init zeus_init(void)
837{
5f86ceba 838 u16 dm9000_msc = DM9K_MSC_VALUE;
ad68bb9f 839 u32 msc0, msc1;
e491a11c
MZ		 840
841 system_rev = __raw_readw(ZEUS_CPLD_VERSION);
842 pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
843
844 /* Fix timings for dm9000s (CS1/CS2)*/
bc3e55c6
MV		 845 msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
846 msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
ad68bb9f
MV		 847 __raw_writel(msc0, MSC0);
848 __raw_writel(msc1, MSC1);
e491a11c
MZ		 849
850 pm_power_off = zeus_power_off;
a1916eb0 851 zeus_setup_apm();
e491a11c
MZ		 852
853 pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
854
855 platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
856
541e00ae 857 zeus_register_ohci();
e491a11c
MZ		 858
859 if (zeus_setup_fb_gpios())
860 pr_err("Failed to setup fb gpios\n");
861 else
4321e1a1 862 pxa_set_fb_info(NULL, &zeus_fb_info);
e491a11c
MZ		 863
864 pxa_set_mci_info(&zeus_mci_platform_data);
865 pxa_set_udc_info(&zeus_udc_info);
866 pxa_set_ac97_info(&zeus_ac97_info);
867 pxa_set_i2c_info(NULL);
868 i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
438a22fe
MZ		 869 pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
870 spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
e491a11c
MZ		 871}
872
873static struct map_desc zeus_io_desc[] __initdata = {
874 {
97b09da4 875 .virtual = (unsigned long)ZEUS_CPLD_VERSION,
e491a11c
MZ		 876 .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
877 .length = 0x1000,
878 .type = MT_DEVICE,
879 },
880 {
97b09da4 881 .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ,
e491a11c
MZ		 882 .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
883 .length = 0x1000,
884 .type = MT_DEVICE,
885 },
886 {
97b09da4 887 .virtual = (unsigned long)ZEUS_CPLD_CONTROL,
e491a11c
MZ		 888 .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
889 .length = 0x1000,
890 .type = MT_DEVICE,
891 },
e491a11c 892 {
97b09da4 893 .virtual = (unsigned long)ZEUS_PC104IO,
e491a11c
MZ		 894 .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS),
895 .length = 0x00800000,
896 .type = MT_DEVICE,
897 },
898};
899
900static void __init zeus_map_io(void)
901{
851982c1 902 pxa27x_map_io();
e491a11c
MZ		 903
904 iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
905
906 /* Clear PSPR to ensure a full restart on wake-up. */
907 PMCR = PSPR = 0;
908
909 /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
910 OSCC |= OSCC_OON;
911
912 /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
913 * float chip selects and PCMCIA */
914 PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
915}
916
90ac0dfd 917MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
e491a11c 918 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
7375aba6 919 .atag_offset = 0x100,
e491a11c 920 .map_io = zeus_map_io,
6ac6b817 921 .nr_irqs = ZEUS_NR_IRQS,
e491a11c 922 .init_irq = zeus_init_irq,
8a97ae2f 923 .handle_irq = pxa27x_handle_irq,
6bb27d73 924 .init_time = pxa_timer_init,
e491a11c 925 .init_machine = zeus_init,
271a74fc 926 .restart = pxa_restart,
e491a11c
MZ		 927MACHINE_END
928
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