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862184fe RK |
1 | /* |
2 | * linux/arch/arm/mach-realview/platsmp.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Ltd. | |
5 | * All Rights Reserved | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/smp.h> | |
16 | ||
17 | #include <asm/cacheflush.h> | |
18 | #include <asm/hardware/arm_scu.h> | |
19 | #include <asm/hardware.h> | |
ce07d90a | 20 | #include <asm/io.h> |
862184fe RK |
21 | |
22 | extern void realview_secondary_startup(void); | |
23 | ||
24 | /* | |
25 | * control for which core is the next to come out of the secondary | |
26 | * boot "holding pen" | |
27 | */ | |
28 | volatile int __cpuinitdata pen_release = -1; | |
29 | ||
30 | static unsigned int __init get_core_count(void) | |
31 | { | |
32 | unsigned int ncores; | |
33 | ||
356cb470 | 34 | ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG); |
862184fe RK |
35 | |
36 | return (ncores & 0x03) + 1; | |
37 | } | |
38 | ||
39 | static DEFINE_SPINLOCK(boot_lock); | |
40 | ||
41 | void __cpuinit platform_secondary_init(unsigned int cpu) | |
42 | { | |
43 | /* | |
44 | * the primary core may have used a "cross call" soft interrupt | |
45 | * to get this processor out of WFI in the BootMonitor - make | |
46 | * sure that we are no longer being sent this soft interrupt | |
47 | */ | |
48 | smp_cross_call_done(cpumask_of_cpu(cpu)); | |
49 | ||
50 | /* | |
51 | * if any interrupts are already enabled for the primary | |
52 | * core (e.g. timer irq), then they will not have been enabled | |
53 | * for us: do so | |
54 | */ | |
356cb470 | 55 | gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); |
862184fe RK |
56 | |
57 | /* | |
58 | * let the primary processor know we're out of the | |
59 | * pen, then head off into the C entry point | |
60 | */ | |
61 | pen_release = -1; | |
0e0ba769 | 62 | smp_wmb(); |
862184fe RK |
63 | |
64 | /* | |
65 | * Synchronise with the boot thread. | |
66 | */ | |
67 | spin_lock(&boot_lock); | |
68 | spin_unlock(&boot_lock); | |
69 | } | |
70 | ||
71 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |
72 | { | |
73 | unsigned long timeout; | |
74 | ||
75 | /* | |
76 | * set synchronisation state between this boot processor | |
77 | * and the secondary one | |
78 | */ | |
79 | spin_lock(&boot_lock); | |
80 | ||
81 | /* | |
82 | * The secondary processor is waiting to be released from | |
83 | * the holding pen - release it, then wait for it to flag | |
84 | * that it has been released by resetting pen_release. | |
85 | * | |
86 | * Note that "pen_release" is the hardware CPU ID, whereas | |
87 | * "cpu" is Linux's internal ID. | |
88 | */ | |
89 | pen_release = cpu; | |
90 | flush_cache_all(); | |
91 | ||
92 | /* | |
93 | * XXX | |
94 | * | |
95 | * This is a later addition to the booting protocol: the | |
96 | * bootMonitor now puts secondary cores into WFI, so | |
97 | * poke_milo() no longer gets the cores moving; we need | |
98 | * to send a soft interrupt to wake the secondary core. | |
99 | * Use smp_cross_call() for this, since there's little | |
100 | * point duplicating the code here | |
101 | */ | |
102 | smp_cross_call(cpumask_of_cpu(cpu)); | |
103 | ||
104 | timeout = jiffies + (1 * HZ); | |
105 | while (time_before(jiffies, timeout)) { | |
0e0ba769 | 106 | smp_rmb(); |
862184fe RK |
107 | if (pen_release == -1) |
108 | break; | |
109 | ||
110 | udelay(10); | |
111 | } | |
112 | ||
113 | /* | |
114 | * now the secondary core is starting up let it run its | |
115 | * calibrations, then wait for it to finish | |
116 | */ | |
117 | spin_unlock(&boot_lock); | |
118 | ||
119 | return pen_release != -1 ? -ENOSYS : 0; | |
120 | } | |
121 | ||
122 | static void __init poke_milo(void) | |
123 | { | |
124 | extern void secondary_startup(void); | |
125 | ||
126 | /* nobody is to be released from the pen yet */ | |
127 | pen_release = -1; | |
128 | ||
129 | /* | |
130 | * write the address of secondary startup into the system-wide | |
131 | * flags register, then clear the bottom two bits, which is what | |
132 | * BootMonitor is waiting for | |
133 | */ | |
134 | #if 1 | |
135 | #define REALVIEW_SYS_FLAGSS_OFFSET 0x30 | |
136 | __raw_writel(virt_to_phys(realview_secondary_startup), | |
5d43045b RK |
137 | __io_address(REALVIEW_SYS_BASE) + |
138 | REALVIEW_SYS_FLAGSS_OFFSET); | |
862184fe RK |
139 | #define REALVIEW_SYS_FLAGSC_OFFSET 0x34 |
140 | __raw_writel(3, | |
5d43045b RK |
141 | __io_address(REALVIEW_SYS_BASE) + |
142 | REALVIEW_SYS_FLAGSC_OFFSET); | |
862184fe RK |
143 | #endif |
144 | ||
145 | mb(); | |
146 | } | |
147 | ||
7bbb7940 RK |
148 | /* |
149 | * Initialise the CPU possible map early - this describes the CPUs | |
150 | * which may be present or become present in the system. | |
151 | */ | |
152 | void __init smp_init_cpus(void) | |
153 | { | |
154 | unsigned int i, ncores = get_core_count(); | |
155 | ||
156 | for (i = 0; i < ncores; i++) | |
157 | cpu_set(i, cpu_possible_map); | |
158 | } | |
159 | ||
862184fe RK |
160 | void __init smp_prepare_cpus(unsigned int max_cpus) |
161 | { | |
162 | unsigned int ncores = get_core_count(); | |
163 | unsigned int cpu = smp_processor_id(); | |
164 | int i; | |
165 | ||
166 | /* sanity check */ | |
167 | if (ncores == 0) { | |
168 | printk(KERN_ERR | |
169 | "Realview: strange CM count of 0? Default to 1\n"); | |
170 | ||
171 | ncores = 1; | |
172 | } | |
173 | ||
174 | if (ncores > NR_CPUS) { | |
175 | printk(KERN_WARNING | |
176 | "Realview: no. of cores (%d) greater than configured " | |
177 | "maximum of %d - clipping\n", | |
178 | ncores, NR_CPUS); | |
179 | ncores = NR_CPUS; | |
180 | } | |
181 | ||
182 | smp_store_cpu_info(cpu); | |
183 | ||
184 | /* | |
185 | * are we trying to boot more cores than exist? | |
186 | */ | |
187 | if (max_cpus > ncores) | |
188 | max_cpus = ncores; | |
189 | ||
a8655e83 | 190 | #ifdef CONFIG_LOCAL_TIMERS |
2a98beb6 | 191 | /* |
a8655e83 CM |
192 | * Enable the local timer for primary CPU. If the device is |
193 | * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in | |
194 | * realview_timer_init | |
2a98beb6 RK |
195 | */ |
196 | local_timer_setup(cpu); | |
a8655e83 | 197 | #endif |
2a98beb6 | 198 | |
862184fe | 199 | /* |
7bbb7940 RK |
200 | * Initialise the present map, which describes the set of CPUs |
201 | * actually populated at the present time. | |
862184fe | 202 | */ |
7bbb7940 | 203 | for (i = 0; i < max_cpus; i++) |
862184fe | 204 | cpu_set(i, cpu_present_map); |
862184fe RK |
205 | |
206 | /* | |
207 | * Do we need any more CPUs? If so, then let them know where | |
208 | * to start. Note that, on modern versions of MILO, the "poke" | |
209 | * doesn't actually do anything until each individual core is | |
210 | * sent a soft interrupt to get it out of WFI | |
211 | */ | |
212 | if (max_cpus > 1) | |
213 | poke_milo(); | |
214 | } |