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2025cf9e | 1 | // SPDX-License-Identifier: GPL-2.0-only |
9c1ec8e1 CZ |
2 | /* |
3 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
4 | * Author: Tony Xie <tony.xie@rock-chips.com> | |
9c1ec8e1 CZ |
5 | */ |
6 | ||
7 | #include <linux/init.h> | |
8 | #include <linux/io.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/of.h> | |
11 | #include <linux/of_address.h> | |
12 | #include <linux/regmap.h> | |
13 | #include <linux/suspend.h> | |
14 | #include <linux/mfd/syscon.h> | |
15 | #include <linux/regulator/machine.h> | |
16 | ||
17 | #include <asm/cacheflush.h> | |
18 | #include <asm/tlbflush.h> | |
19 | #include <asm/suspend.h> | |
20 | ||
21 | #include "pm.h" | |
22 | ||
23 | /* These enum are option of low power mode */ | |
24 | enum { | |
25 | ROCKCHIP_ARM_OFF_LOGIC_NORMAL = 0, | |
26 | ROCKCHIP_ARM_OFF_LOGIC_DEEP = 1, | |
27 | }; | |
28 | ||
29 | struct rockchip_pm_data { | |
30 | const struct platform_suspend_ops *ops; | |
31 | int (*init)(struct device_node *np); | |
32 | }; | |
33 | ||
34 | static void __iomem *rk3288_bootram_base; | |
35 | static phys_addr_t rk3288_bootram_phy; | |
36 | ||
37 | static struct regmap *pmu_regmap; | |
38 | static struct regmap *sgrf_regmap; | |
134f1f60 | 39 | static struct regmap *grf_regmap; |
9c1ec8e1 CZ |
40 | |
41 | static u32 rk3288_pmu_pwr_mode_con; | |
42 | static u32 rk3288_sgrf_soc_con0; | |
33939403 | 43 | static u32 rk3288_sgrf_cpu_con0; |
9c1ec8e1 CZ |
44 | |
45 | static inline u32 rk3288_l2_config(void) | |
46 | { | |
47 | u32 l2ctlr; | |
48 | ||
49 | asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr)); | |
50 | return l2ctlr; | |
51 | } | |
52 | ||
2dd00d31 | 53 | static void __init rk3288_config_bootdata(void) |
9c1ec8e1 CZ |
54 | { |
55 | rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8); | |
64fc2a94 | 56 | rkpm_bootdata_cpu_code = __pa_symbol(cpu_resume); |
9c1ec8e1 CZ |
57 | |
58 | rkpm_bootdata_l2ctlr_f = 1; | |
59 | rkpm_bootdata_l2ctlr = rk3288_l2_config(); | |
60 | } | |
61 | ||
134f1f60 CZ |
62 | #define GRF_UOC0_CON0 0x320 |
63 | #define GRF_UOC1_CON0 0x334 | |
64 | #define GRF_UOC2_CON0 0x348 | |
65 | #define GRF_SIDDQ BIT(13) | |
66 | ||
67 | static bool rk3288_slp_disable_osc(void) | |
68 | { | |
69 | static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0, | |
70 | GRF_UOC2_CON0 }; | |
71 | u32 reg, i; | |
72 | ||
73 | /* | |
74 | * if any usb phy is still on(GRF_SIDDQ==0), that means we need the | |
75 | * function of usb wakeup, so do not switch to 32khz, since the usb phy | |
76 | * clk does not connect to 32khz osc | |
77 | */ | |
78 | for (i = 0; i < ARRAY_SIZE(reg_offset); i++) { | |
79 | regmap_read(grf_regmap, reg_offset[i], ®); | |
80 | if (!(reg & GRF_SIDDQ)) | |
81 | return false; | |
82 | } | |
83 | ||
84 | return true; | |
85 | } | |
86 | ||
9c1ec8e1 CZ |
87 | static void rk3288_slp_mode_set(int level) |
88 | { | |
89 | u32 mode_set, mode_set1; | |
41fe6a01 | 90 | bool osc_disable = rk3288_slp_disable_osc(); |
9c1ec8e1 | 91 | |
33939403 | 92 | regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0); |
9c1ec8e1 CZ |
93 | regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); |
94 | ||
95 | regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, | |
96 | &rk3288_pmu_pwr_mode_con); | |
97 | ||
a0307d18 CZ |
98 | /* |
99 | * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR | |
100 | * PCLK_WDT_GATE - disable WDT during suspend. | |
101 | */ | |
9c1ec8e1 | 102 | regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, |
a0307d18 CZ |
103 | SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN |
104 | | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE); | |
9c1ec8e1 | 105 | |
0ea001d3 CZ |
106 | /* |
107 | * The dapswjdp can not auto reset before resume, that cause it may | |
108 | * access some illegal address during resume. Let's disable it before | |
109 | * suspend, and the MASKROM will enable it back. | |
110 | */ | |
111 | regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE); | |
112 | ||
9c1ec8e1 CZ |
113 | /* booting address of resuming system is from this register value */ |
114 | regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR, | |
115 | rk3288_bootram_phy); | |
116 | ||
9c1ec8e1 CZ |
117 | mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) | |
118 | BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) | | |
119 | BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) | | |
120 | BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) | | |
121 | BIT(PMU_SCU_EN); | |
122 | ||
123 | mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP); | |
124 | ||
125 | if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) { | |
126 | /* arm off, logic deep sleep */ | |
134f1f60 | 127 | mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) | |
9c1ec8e1 | 128 | BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) | |
9c1ec8e1 CZ |
129 | BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN); |
130 | ||
41fe6a01 | 131 | if (osc_disable) |
134f1f60 CZ |
132 | mode_set |= BIT(PMU_OSC_24M_DIS); |
133 | ||
9c1ec8e1 CZ |
134 | mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) | |
135 | BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA); | |
d1d3a1a1 | 136 | |
9bb91ae9 HS |
137 | regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1, |
138 | PMU_ARMINT_WAKEUP_EN); | |
139 | ||
d1d3a1a1 HS |
140 | /* |
141 | * In deep suspend we use PMU_PMU_USE_LF to let the rk3288 | |
142 | * switch its main clock supply to the alternative 32kHz | |
143 | * source. Therefore set 30ms on a 32kHz clock for pmic | |
144 | * stabilization. Similar 30ms on 24MHz for the other | |
145 | * mode below. | |
146 | */ | |
147 | regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30); | |
148 | ||
149 | /* only wait for stabilization, if we turned the osc off */ | |
150 | regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, | |
151 | osc_disable ? 32 * 30 : 0); | |
9c1ec8e1 CZ |
152 | } else { |
153 | /* | |
154 | * arm off, logic normal | |
155 | * if pmu_clk_core_src_gate_en is not set, | |
156 | * wakeup will be error | |
157 | */ | |
158 | mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN); | |
d1d3a1a1 | 159 | |
9bb91ae9 HS |
160 | regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1, |
161 | PMU_ARMINT_WAKEUP_EN | PMU_GPIOINT_WAKEUP_EN); | |
162 | ||
d1d3a1a1 HS |
163 | /* 30ms on a 24MHz clock for pmic stabilization */ |
164 | regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30); | |
165 | ||
166 | /* oscillator is still running, so no need to wait */ | |
167 | regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 0); | |
9c1ec8e1 CZ |
168 | } |
169 | ||
170 | regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set); | |
171 | regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON1, mode_set1); | |
172 | } | |
173 | ||
174 | static void rk3288_slp_mode_set_resume(void) | |
175 | { | |
33939403 DA |
176 | regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, |
177 | rk3288_sgrf_cpu_con0 | SGRF_DAPDEVICEEN_WRITE); | |
178 | ||
9c1ec8e1 CZ |
179 | regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, |
180 | rk3288_pmu_pwr_mode_con); | |
181 | ||
182 | regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, | |
a0307d18 CZ |
183 | rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE |
184 | | SGRF_FAST_BOOT_EN_WRITE); | |
9c1ec8e1 CZ |
185 | } |
186 | ||
187 | static int rockchip_lpmode_enter(unsigned long arg) | |
188 | { | |
189 | flush_cache_all(); | |
190 | ||
191 | cpu_do_idle(); | |
192 | ||
193 | pr_err("%s: Failed to suspend\n", __func__); | |
194 | ||
195 | return 1; | |
196 | } | |
197 | ||
198 | static int rk3288_suspend_enter(suspend_state_t state) | |
199 | { | |
200 | local_fiq_disable(); | |
201 | ||
202 | rk3288_slp_mode_set(ROCKCHIP_ARM_OFF_LOGIC_NORMAL); | |
203 | ||
204 | cpu_suspend(0, rockchip_lpmode_enter); | |
205 | ||
206 | rk3288_slp_mode_set_resume(); | |
207 | ||
208 | local_fiq_enable(); | |
209 | ||
210 | return 0; | |
211 | } | |
212 | ||
213 | static int rk3288_suspend_prepare(void) | |
214 | { | |
215 | return regulator_suspend_prepare(PM_SUSPEND_MEM); | |
216 | } | |
217 | ||
218 | static void rk3288_suspend_finish(void) | |
219 | { | |
220 | if (regulator_suspend_finish()) | |
221 | pr_err("%s: Suspend finish failed\n", __func__); | |
222 | } | |
223 | ||
2dd00d31 | 224 | static int __init rk3288_suspend_init(struct device_node *np) |
9c1ec8e1 CZ |
225 | { |
226 | struct device_node *sram_np; | |
227 | struct resource res; | |
228 | int ret; | |
229 | ||
230 | pmu_regmap = syscon_node_to_regmap(np); | |
231 | if (IS_ERR(pmu_regmap)) { | |
232 | pr_err("%s: could not find pmu regmap\n", __func__); | |
233 | return PTR_ERR(pmu_regmap); | |
234 | } | |
235 | ||
236 | sgrf_regmap = syscon_regmap_lookup_by_compatible( | |
237 | "rockchip,rk3288-sgrf"); | |
238 | if (IS_ERR(sgrf_regmap)) { | |
239 | pr_err("%s: could not find sgrf regmap\n", __func__); | |
2a03c025 | 240 | return PTR_ERR(sgrf_regmap); |
9c1ec8e1 CZ |
241 | } |
242 | ||
134f1f60 CZ |
243 | grf_regmap = syscon_regmap_lookup_by_compatible( |
244 | "rockchip,rk3288-grf"); | |
245 | if (IS_ERR(grf_regmap)) { | |
246 | pr_err("%s: could not find grf regmap\n", __func__); | |
2a03c025 | 247 | return PTR_ERR(grf_regmap); |
134f1f60 CZ |
248 | } |
249 | ||
9c1ec8e1 CZ |
250 | sram_np = of_find_compatible_node(NULL, NULL, |
251 | "rockchip,rk3288-pmu-sram"); | |
252 | if (!sram_np) { | |
253 | pr_err("%s: could not find bootram dt node\n", __func__); | |
254 | return -ENODEV; | |
255 | } | |
256 | ||
257 | rk3288_bootram_base = of_iomap(sram_np, 0); | |
258 | if (!rk3288_bootram_base) { | |
259 | pr_err("%s: could not map bootram base\n", __func__); | |
260 | return -ENOMEM; | |
261 | } | |
262 | ||
263 | ret = of_address_to_resource(sram_np, 0, &res); | |
264 | if (ret) { | |
265 | pr_err("%s: could not get bootram phy addr\n", __func__); | |
266 | return ret; | |
267 | } | |
268 | rk3288_bootram_phy = res.start; | |
269 | ||
270 | of_node_put(sram_np); | |
271 | ||
272 | rk3288_config_bootdata(); | |
273 | ||
274 | /* copy resume code and data to bootsram */ | |
275 | memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume, | |
276 | rk3288_bootram_sz); | |
277 | ||
278 | return 0; | |
279 | } | |
280 | ||
281 | static const struct platform_suspend_ops rk3288_suspend_ops = { | |
282 | .enter = rk3288_suspend_enter, | |
283 | .valid = suspend_valid_only_mem, | |
284 | .prepare = rk3288_suspend_prepare, | |
285 | .finish = rk3288_suspend_finish, | |
286 | }; | |
287 | ||
288 | static const struct rockchip_pm_data rk3288_pm_data __initconst = { | |
289 | .ops = &rk3288_suspend_ops, | |
290 | .init = rk3288_suspend_init, | |
291 | }; | |
292 | ||
293 | static const struct of_device_id rockchip_pmu_of_device_ids[] __initconst = { | |
294 | { | |
295 | .compatible = "rockchip,rk3288-pmu", | |
296 | .data = &rk3288_pm_data, | |
297 | }, | |
298 | { /* sentinel */ }, | |
299 | }; | |
300 | ||
301 | void __init rockchip_suspend_init(void) | |
302 | { | |
303 | const struct rockchip_pm_data *pm_data; | |
304 | const struct of_device_id *match; | |
305 | struct device_node *np; | |
306 | int ret; | |
307 | ||
308 | np = of_find_matching_node_and_match(NULL, rockchip_pmu_of_device_ids, | |
309 | &match); | |
310 | if (!match) { | |
311 | pr_err("Failed to find PMU node\n"); | |
312 | return; | |
313 | } | |
314 | pm_data = (struct rockchip_pm_data *) match->data; | |
315 | ||
316 | if (pm_data->init) { | |
317 | ret = pm_data->init(np); | |
318 | ||
319 | if (ret) { | |
320 | pr_err("%s: matches init error %d\n", __func__, ret); | |
321 | return; | |
322 | } | |
323 | } | |
324 | ||
325 | suspend_set_ops(pm_data->ops); | |
326 | } |