projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| d63dc051 HS |
1 | /* |
| 2 | * Device Tree support for Rockchip SoCs | |
| 3 | * | |
| 4 | * Copyright (c) 2013 MundoReader S.L. | |
| 5 | * Author: Heiko Stuebner <heiko@sntech.de> | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License as published by | |
| 9 | * the Free Software Foundation; either version 2 of the License, or | |
| 10 | * (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | */ | |
| 17 | ||
| 18 | #include <linux/kernel.h> | |
| 19 | #include <linux/init.h> | |
| 20 | #include <linux/of_platform.h> | |
| 21 | #include <linux/irqchip.h> | |
| c9b75d51 HS |
22 | #include <linux/clk-provider.h> |
| 23 | #include <linux/clocksource.h> | |
| 24 | #include <linux/mfd/syscon.h> | |
| 25 | #include <linux/regmap.h> | |
| d63dc051 HS |
26 | #include <asm/mach/arch.h> |
| 27 | #include <asm/mach/map.h> | |
| 28 | #include <asm/hardware/cache-l2x0.h> | |
| a7a2b311 | 29 | #include "core.h" |
| 9c1ec8e1 | 30 | #include "pm.h" |
| d63dc051 | 31 | |
| c9b75d51 | 32 | #define RK3288_GRF_SOC_CON0 0x244 |
| 2a9fe3ca | 33 | #define RK3288_TIMER6_7_PHYS 0xff810000 |
| c9b75d51 HS |
34 | |
| 35 | static void __init rockchip_timer_init(void) | |
| 36 | { | |
| 37 | if (of_machine_is_compatible("rockchip,rk3288")) { | |
| 38 | struct regmap *grf; | |
| 2a9fe3ca HS |
39 | void __iomem *reg_base; |
| 40 | ||
| 41 | /* | |
| 42 | * Most/all uboot versions for rk3288 don't enable timer7 | |
| 43 | * which is needed for the architected timer to work. | |
| 44 | * So make sure it is running during early boot. | |
| 45 | */ | |
| 46 | reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); | |
| 47 | if (reg_base) { | |
| 48 | writel(0, reg_base + 0x30); | |
| 49 | writel(0xffffffff, reg_base + 0x20); | |
| 50 | writel(0xffffffff, reg_base + 0x24); | |
| 51 | writel(1, reg_base + 0x30); | |
| 52 | dsb(); | |
| 53 | iounmap(reg_base); | |
| 54 | } else { | |
| 55 | pr_err("rockchip: could not map timer7 registers\n"); | |
| 56 | } | |
| c9b75d51 HS |
57 | |
| 58 | /* | |
| 59 | * Disable auto jtag/sdmmc switching that causes issues | |
| 60 | * with the mmc controllers making them unreliable | |
| 61 | */ | |
| 62 | grf = syscon_regmap_lookup_by_compatible("rockchip,rk3288-grf"); | |
| 63 | if (!IS_ERR(grf)) | |
| 64 | regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000); | |
| 65 | else | |
| 66 | pr_err("rockchip: could not get grf syscon\n"); | |
| 67 | } | |
| 68 | ||
| 69 | of_clk_init(NULL); | |
| 70 | clocksource_of_init(); | |
| 71 | } | |
| 72 | ||
| 47b06fc2 HS |
73 | static void __init rockchip_dt_init(void) |
| 74 | { | |
| 9c1ec8e1 | 75 | rockchip_suspend_init(); |
| 47b06fc2 | 76 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 3eb79a5a | 77 | platform_device_register_simple("cpufreq-dt", 0, NULL, 0); |
| 47b06fc2 HS |
78 | } |
| 79 | ||
| d63dc051 HS |
80 | static const char * const rockchip_board_dt_compat[] = { |
| 81 | "rockchip,rk2928", | |
| 82 | "rockchip,rk3066a", | |
| 83 | "rockchip,rk3066b", | |
| 84 | "rockchip,rk3188", | |
| 7a1917ab | 85 | "rockchip,rk3288", |
| d63dc051 HS |
86 | NULL, |
| 87 | }; | |
| 88 | ||
| 8c421241 | 89 | DT_MACHINE_START(ROCKCHIP_DT, "Rockchip (Device Tree)") |
| 2a2d2fff RK |
90 | .l2c_aux_val = 0, |
| 91 | .l2c_aux_mask = ~0, | |
| c9b75d51 | 92 | .init_time = rockchip_timer_init, |
| d63dc051 | 93 | .dt_compat = rockchip_board_dt_compat, |
| 47b06fc2 | 94 | .init_machine = rockchip_dt_init, |
| d63dc051 | 95 | MACHINE_END |