[mirror_ubuntu-jammy-kernel.git] / arch / arm / mach-s3c / mach-at2440evb.c

// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com>
//      Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk>
//      and modifications by SBZ <sbz@spgui.org> and
//      Weibing <http://weibing.blogbus.com>
//
// For product information, visit http://www.arm.com/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/gpio/machine.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/dm9000.h>
#include <linux/platform_device.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <linux/platform_data/fb-s3c2410.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include "regs-gpio.h"
#include "gpio-samsung.h"
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/nand-ecc-sw-hamming.h>
#include <linux/mtd/partitions.h>

#include "devs.h"
#include "cpu.h"
#include <linux/platform_data/mmc-s3cmci.h>

#include "s3c24xx.h"

static struct map_desc at2440evb_iodesc[] __initdata = {
	/* Nothing here */
};

#define UCON S3C2410_UCON_DEFAULT
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)

static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
	},
};

/* NAND Flash on AT2440EVB board */

static struct mtd_partition __initdata at2440evb_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_256K,
		.offset	= 0,
	},
	[1] = {
		.name	= "Kernel",
		.size	= SZ_2M,
		.offset	= SZ_256K,
	},
	[2] = {
		.name	= "Root",
		.offset	= SZ_256K + SZ_2M,
		.size	= MTDPART_SIZ_FULL,
	},
};

static struct s3c2410_nand_set __initdata at2440evb_nand_sets[] = {
	[0] = {
		.name		= "nand",
		.nr_chips	= 1,
		.nr_partitions	= ARRAY_SIZE(at2440evb_default_nand_part),
		.partitions	= at2440evb_default_nand_part,
	},
};

static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
	.tacls		= 25,
	.twrph0		= 55,
	.twrph1		= 40,
	.nr_sets	= ARRAY_SIZE(at2440evb_nand_sets),
	.sets		= at2440evb_nand_sets,
	.engine_type	= NAND_ECC_ENGINE_TYPE_SOFT,
};

/* DM9000AEP 10/100 ethernet controller */

static struct resource at2440evb_dm9k_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_CS3, 4),
	[1] = DEFINE_RES_MEM(S3C2410_CS3 + 4, 4),
	[2] = DEFINE_RES_NAMED(IRQ_EINT7, 1, NULL, IORESOURCE_IRQ \
					| IORESOURCE_IRQ_HIGHEDGE),
};

static struct dm9000_plat_data at2440evb_dm9k_pdata = {
	.flags		= (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
};

static struct platform_device at2440evb_device_eth = {
	.name		= "dm9000",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(at2440evb_dm9k_resource),
	.resource	= at2440evb_dm9k_resource,
	.dev		= {
		.platform_data	= &at2440evb_dm9k_pdata,
	},
};

static struct s3c24xx_mci_pdata at2440evb_mci_pdata __initdata = {
	.set_power	= s3c24xx_mci_def_set_power,
};

static struct gpiod_lookup_table at2440evb_mci_gpio_table = {
	.dev_id = "s3c2410-sdi",
	.table = {
		/* Card detect S3C2410_GPG(10) */
		GPIO_LOOKUP("GPIOG", 10, "cd", GPIO_ACTIVE_LOW),
		/* bus pins */
		GPIO_LOOKUP_IDX("GPIOE",  5, "bus", 0, GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP_IDX("GPIOE",  6, "bus", 1, GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP_IDX("GPIOE",  7, "bus", 2, GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP_IDX("GPIOE",  8, "bus", 3, GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP_IDX("GPIOE",  9, "bus", 4, GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
		{ },
	},
};


/* 7" LCD panel */

static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = {

	.lcdcon5	= S3C2410_LCDCON5_FRM565 |
			  S3C2410_LCDCON5_INVVLINE |
			  S3C2410_LCDCON5_INVVFRAME |
			  S3C2410_LCDCON5_PWREN |
			  S3C2410_LCDCON5_HWSWP,

	.type		= S3C2410_LCDCON1_TFT,

	.width		= 800,
	.height		= 480,

	.pixclock	= 33333, /* HCLK 60 MHz, divisor 2 */
	.xres		= 800,
	.yres		= 480,
	.bpp		= 16,
	.left_margin	= 88,
	.right_margin	= 40,
	.hsync_len	= 128,
	.upper_margin	= 32,
	.lower_margin	= 11,
	.vsync_len	= 2,
};

static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = {
	.displays	= &at2440evb_lcd_cfg,
	.num_displays	= 1,
	.default_display = 0,
};

static struct platform_device *at2440evb_devices[] __initdata = {
	&s3c_device_ohci,
	&s3c_device_wdt,
	&s3c_device_adc,
	&s3c_device_i2c0,
	&s3c_device_rtc,
	&s3c_device_nand,
	&s3c_device_sdi,
	&s3c_device_lcd,
	&at2440evb_device_eth,
};

static void __init at2440evb_map_io(void)
{
	s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
	s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
	s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}

static void __init at2440evb_init_time(void)
{
	s3c2440_init_clocks(16934400);
	s3c24xx_timer_init();
}

static void __init at2440evb_init(void)
{
	s3c24xx_fb_set_platdata(&at2440evb_fb_info);
	gpiod_add_lookup_table(&at2440evb_mci_gpio_table);
	s3c24xx_mci_set_platdata(&at2440evb_mci_pdata);
	s3c_nand_set_platdata(&at2440evb_nand_info);
	s3c_i2c0_set_platdata(NULL);

	platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
}


MACHINE_START(AT2440EVB, "AT2440EVB")
	.atag_offset	= 0x100,
	.map_io		= at2440evb_map_io,
	.init_machine	= at2440evb_init,
	.init_irq	= s3c2440_init_irq,
	.init_time	= at2440evb_init_time,
MACHINE_END
Commit	Line	Data
84b21701 KK	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com>
	4	// Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk>
	5	// and modifications by SBZ <sbz@spgui.org> and
	6	// Weibing <http://weibing.blogbus.com>
	7	//
	8	// For product information, visit http://www.arm.com/
4ab98971 RL	9
	10	#include <linux/kernel.h>
	11	#include <linux/types.h>
d2951dfa	12	#include <linux/gpio/machine.h>
4ab98971 RL	13	#include <linux/interrupt.h>
	14	#include <linux/list.h>
	15	#include <linux/timer.h>
	16	#include <linux/init.h>
	17	#include <linux/io.h>
	18	#include <linux/serial_core.h>
334a1c70	19	#include <linux/serial_s3c.h>
66493c2d	20	#include <linux/dm9000.h>
4ab98971 RL	21	#include <linux/platform_device.h>
	22
	23	#include <asm/mach/arch.h>
	24	#include <asm/mach/map.h>
	25	#include <asm/mach/irq.h>
	26
81994e0f	27	#include <linux/platform_data/fb-s3c2410.h>
4ab98971 RL	28	#include <asm/irq.h>
	29	#include <asm/mach-types.h>
	30
c6ff132d AB	31	#include "regs-gpio.h"
c6ff132d AB	32	#include "gpio-samsung.h"
436d42c6 AB	33	#include <linux/platform_data/mtd-nand-s3c2410.h>
436d42c6 AB	34	#include <linux/platform_data/i2c-s3c2410.h>
4ab98971 RL	35
4ab98971 RL	36	#include <linux/mtd/mtd.h>
d4092d76	37	#include <linux/mtd/rawnand.h>
e5acf9c8	38	#include <linux/mtd/nand-ecc-sw-hamming.h>
4ab98971 RL	39	#include <linux/mtd/partitions.h>
4ab98971 RL	40
c6ff132d AB	41	#include "devs.h"
c6ff132d AB	42	#include "cpu.h"
436d42c6	43	#include <linux/platform_data/mmc-s3cmci.h>
4ab98971	44
71b9114d	45	#include "s3c24xx.h"
b27b0727	46
4ab98971 RL	47	static struct map_desc at2440evb_iodesc[] __initdata = {
	48	/* Nothing here */
	49	};
	50
	51	#define UCON S3C2410_UCON_DEFAULT
	52	#define ULCON (S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE)
	53	#define UFCON (S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE)
	54
4ab98971 RL	55	static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
	56	[0] = {
	57	.hwport = 0,
	58	.flags = 0,
	59	.ucon = UCON,
	60	.ulcon = ULCON,
	61	.ufcon = UFCON,
afba7f91	62	.clk_sel = S3C2410_UCON_CLKSEL1 \| S3C2410_UCON_CLKSEL2,
4ab98971 RL	63	},
	64	[1] = {
	65	.hwport = 1,
	66	.flags = 0,
	67	.ucon = UCON,
	68	.ulcon = ULCON,
	69	.ufcon = UFCON,
afba7f91	70	.clk_sel = S3C2410_UCON_CLKSEL1 \| S3C2410_UCON_CLKSEL2,
4ab98971 RL	71	},
	72	};
	73
	74	/* NAND Flash on AT2440EVB board */
	75
2a3a1804	76	static struct mtd_partition __initdata at2440evb_default_nand_part[] = {
4ab98971 RL	77	[0] = {
	78	.name = "Boot Agent",
	79	.size = SZ_256K,
	80	.offset = 0,
	81	},
	82	[1] = {
	83	.name = "Kernel",
	84	.size = SZ_2M,
	85	.offset = SZ_256K,
	86	},
	87	[2] = {
	88	.name = "Root",
	89	.offset = SZ_256K + SZ_2M,
	90	.size = MTDPART_SIZ_FULL,
	91	},
	92	};
	93
2a3a1804	94	static struct s3c2410_nand_set __initdata at2440evb_nand_sets[] = {
4ab98971 RL	95	[0] = {
	96	.name = "nand",
	97	.nr_chips = 1,
	98	.nr_partitions = ARRAY_SIZE(at2440evb_default_nand_part),
	99	.partitions = at2440evb_default_nand_part,
	100	},
	101	};
	102
2a3a1804	103	static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
4ab98971 RL	104	.tacls = 25,
	105	.twrph0 = 55,
	106	.twrph1 = 40,
	107	.nr_sets = ARRAY_SIZE(at2440evb_nand_sets),
	108	.sets = at2440evb_nand_sets,
bace41f8	109	.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
4ab98971 RL	110	};
4ab98971 RL	111
66493c2d RL	112	/* DM9000AEP 10/100 ethernet controller */
	113
	114	static struct resource at2440evb_dm9k_resource[] = {
d990e398 TB	115	[0] = DEFINE_RES_MEM(S3C2410_CS3, 4),
	116	[1] = DEFINE_RES_MEM(S3C2410_CS3 + 4, 4),
	117	[2] = DEFINE_RES_NAMED(IRQ_EINT7, 1, NULL, IORESOURCE_IRQ \
	118	\| IORESOURCE_IRQ_HIGHEDGE),
66493c2d RL	119	};
	120
	121	static struct dm9000_plat_data at2440evb_dm9k_pdata = {
	122	.flags = (DM9000_PLATF_16BITONLY \| DM9000_PLATF_NO_EEPROM),
	123	};
	124
	125	static struct platform_device at2440evb_device_eth = {
	126	.name = "dm9000",
	127	.id = -1,
	128	.num_resources = ARRAY_SIZE(at2440evb_dm9k_resource),
	129	.resource = at2440evb_dm9k_resource,
	130	.dev = {
	131	.platform_data = &at2440evb_dm9k_pdata,
	132	},
	133	};
	134
22c810ab	135	static struct s3c24xx_mci_pdata at2440evb_mci_pdata __initdata = {
f67f6c00	136	.set_power = s3c24xx_mci_def_set_power,
d2951dfa LW	137	};
	138
	139	static struct gpiod_lookup_table at2440evb_mci_gpio_table = {
	140	.dev_id = "s3c2410-sdi",
	141	.table = {
	142	/* Card detect S3C2410_GPG(10) */
3af4e877	143	GPIO_LOOKUP("GPIOG", 10, "cd", GPIO_ACTIVE_LOW),
f67f6c00 AB	144	/* bus pins */
	145	GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
	146	GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
	147	GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
	148	GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
	149	GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
	150	GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
d2951dfa LW	151	{ },
d2951dfa LW	152	},
4a045cb3 BD	153	};
4a045cb3 BD	154
f67f6c00	155
1d19fdba BD	156	/* 7" LCD panel */
	157
	158	static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = {
	159
	160	.lcdcon5 = S3C2410_LCDCON5_FRM565 \|
	161	S3C2410_LCDCON5_INVVLINE \|
	162	S3C2410_LCDCON5_INVVFRAME \|
	163	S3C2410_LCDCON5_PWREN \|
	164	S3C2410_LCDCON5_HWSWP,
	165
	166	.type = S3C2410_LCDCON1_TFT,
	167
	168	.width = 800,
	169	.height = 480,
	170
	171	.pixclock = 33333, /* HCLK 60 MHz, divisor 2 */
	172	.xres = 800,
	173	.yres = 480,
	174	.bpp = 16,
	175	.left_margin = 88,
	176	.right_margin = 40,
	177	.hsync_len = 128,
	178	.upper_margin = 32,
	179	.lower_margin = 11,
	180	.vsync_len = 2,
	181	};
	182
	183	static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = {
	184	.displays = &at2440evb_lcd_cfg,
	185	.num_displays = 1,
	186	.default_display = 0,
	187	};
	188
4ab98971	189	static struct platform_device *at2440evb_devices[] __initdata = {
b813248c	190	&s3c_device_ohci,
4ab98971 RL	191	&s3c_device_wdt,
4ab98971 RL	192	&s3c_device_adc,
3e1b776c	193	&s3c_device_i2c0,
4ab98971 RL	194	&s3c_device_rtc,
4ab98971 RL	195	&s3c_device_nand,
4a045cb3	196	&s3c_device_sdi,
1d19fdba	197	&s3c_device_lcd,
66493c2d	198	&at2440evb_device_eth,
4ab98971 RL	199	};
	200
	201	static void __init at2440evb_map_io(void)
	202	{
4ab98971	203	s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
4ab98971	204	s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
a1342f6a	205	s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
4ab98971 RL	206	}
4ab98971 RL	207
a28d618e HS	208	static void __init at2440evb_init_time(void)
	209	{
	210	s3c2440_init_clocks(16934400);
a1342f6a	211	s3c24xx_timer_init();
a28d618e HS	212	}
a28d618e HS	213
4ab98971 RL	214	static void __init at2440evb_init(void)
4ab98971 RL	215	{
1d19fdba	216	s3c24xx_fb_set_platdata(&at2440evb_fb_info);
d2951dfa	217	gpiod_add_lookup_table(&at2440evb_mci_gpio_table);
22c810ab	218	s3c24xx_mci_set_platdata(&at2440evb_mci_pdata);
2a3a1804	219	s3c_nand_set_platdata(&at2440evb_nand_info);
3e1b776c	220	s3c_i2c0_set_platdata(NULL);
56c035c9	221
4ab98971 RL	222	platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
	223	}
	224
	225
	226	MACHINE_START(AT2440EVB, "AT2440EVB")
69d50710	227	.atag_offset = 0x100,
4ab98971 RL	228	.map_io = at2440evb_map_io,
4ab98971 RL	229	.init_machine = at2440evb_init,
ce6c164b	230	.init_irq = s3c2440_init_irq,
a28d618e	231	.init_time = at2440evb_init_time,
4ab98971	232	MACHINE_END