[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-s3c2410 / dma.c

/* linux/arch/arm/mach-s3c2410/dma.c
 *
 * Copyright (c) 2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2410 DMA selection
 *
 * http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>

#include <mach/dma.h>

#include <plat/cpu.h>
#include <plat/dma.h>

#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <plat/regs-ac97.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
#include <asm/plat-s3c24xx/regs-iis.h>
#include <plat/regs-spi.h>

static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
	[DMACH_XD0] = {
		.name		= "xdreq0",
		.channels[0]	= S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
	},
	[DMACH_XD1] = {
		.name		= "xdreq1",
		.channels[1]	= S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
	},
	[DMACH_SDI] = {
		.name		= "sdi",
		.channels[0]	= S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
		.channels[2]	= S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
		.channels[3]	= S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
		.hw_addr.to	= S3C2410_PA_IIS + S3C2410_IISFIFO,
		.hw_addr.from	= S3C2410_PA_IIS + S3C2410_IISFIFO,
	},
	[DMACH_SPI0] = {
		.name		= "spi0",
		.channels[1]	= S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
		.hw_addr.to	= S3C2410_PA_SPI + S3C2410_SPTDAT,
		.hw_addr.from	= S3C2410_PA_SPI + S3C2410_SPRDAT,
	},
	[DMACH_SPI1] = {
		.name		= "spi1",
		.channels[3]	= S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
		.hw_addr.to	= S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
		.hw_addr.from	= S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
	},
	[DMACH_UART0] = {
		.name		= "uart0",
		.channels[0]	= S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
		.hw_addr.to	= S3C2410_PA_UART0 + S3C2410_UTXH,
		.hw_addr.from	= S3C2410_PA_UART0 + S3C2410_URXH,
	},
	[DMACH_UART1] = {
		.name		= "uart1",
		.channels[1]	= S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
		.hw_addr.to	= S3C2410_PA_UART1 + S3C2410_UTXH,
		.hw_addr.from	= S3C2410_PA_UART1 + S3C2410_URXH,
	},
      	[DMACH_UART2] = {
		.name		= "uart2",
		.channels[3]	= S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
		.hw_addr.to	= S3C2410_PA_UART2 + S3C2410_UTXH,
		.hw_addr.from	= S3C2410_PA_UART2 + S3C2410_URXH,
	},
	[DMACH_TIMER] = {
		.name		= "timer",
		.channels[0]	= S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
		.channels[2]	= S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
		.channels[3]	= S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
	},
	[DMACH_I2S_IN] = {
		.name		= "i2s-sdi",
		.channels[1]	= S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
		.channels[2]	= S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
		.hw_addr.from	= S3C2410_PA_IIS + S3C2410_IISFIFO,
	},
	[DMACH_I2S_OUT] = {
		.name		= "i2s-sdo",
		.channels[2]	= S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
		.hw_addr.to	= S3C2410_PA_IIS + S3C2410_IISFIFO,
	},
	[DMACH_USB_EP1] = {
		.name		= "usb-ep1",
		.channels[0]	= S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
	},
	[DMACH_USB_EP2] = {
		.name		= "usb-ep2",
		.channels[1]	= S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
	},
	[DMACH_USB_EP3] = {
		.name		= "usb-ep3",
		.channels[2]	= S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
	},
	[DMACH_USB_EP4] = {
		.name		= "usb-ep4",
		.channels[3]	=S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
	},
};

static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
			       struct s3c24xx_dma_map *map)
{
	chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
}

static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
	.select		= s3c2410_dma_select,
	.dcon_mask	= 7 << 24,
	.map		= s3c2410_dma_mappings,
	.map_size	= ARRAY_SIZE(s3c2410_dma_mappings),
};

static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
	.channels	= {
		[DMACH_SDI]	= {
			.list	= {
				[0]	= 3 | DMA_CH_VALID,
				[1]	= 2 | DMA_CH_VALID,
				[2]	= 0 | DMA_CH_VALID,
			},
		},
		[DMACH_I2S_IN]	= {
			.list	= {
				[0]	= 1 | DMA_CH_VALID,
				[1]	= 2 | DMA_CH_VALID,
			},
		},
	},
};

static int __init s3c2410_dma_add(struct sys_device *sysdev)
{
	s3c2410_dma_init();
	s3c24xx_dma_order_set(&s3c2410_dma_order);
	return s3c24xx_dma_init_map(&s3c2410_dma_sel);
}

#if defined(CONFIG_CPU_S3C2410)
static struct sysdev_driver s3c2410_dma_driver = {
	.add	= s3c2410_dma_add,
};

static int __init s3c2410_dma_drvinit(void)
{
	return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_dma_driver);
}

arch_initcall(s3c2410_dma_drvinit);
#endif

#if defined(CONFIG_CPU_S3C2442)
/* S3C2442 DMA contains the same selection table as the S3C2410 */
static struct sysdev_driver s3c2442_dma_driver = {
	.add	= s3c2410_dma_add,
};

static int __init s3c2442_dma_drvinit(void)
{
	return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_dma_driver);
}

arch_initcall(s3c2442_dma_drvinit);
#endif
Commit	Line	Data
505788cc	1	/* linux/arch/arm/mach-s3c2410/dma.c
1da177e4	2	*
a21765a7	3	* Copyright (c) 2006 Simtec Electronics
1da177e4 LT	4	* Ben Dooks <ben@simtec.co.uk>
1da177e4 LT	5	*
a21765a7	6	* S3C2410 DMA selection
1da177e4	7	*
505788cc	8	* http://armlinux.simtec.co.uk/
1da177e4 LT	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
505788cc	13	*/
1da177e4	14
a21765a7	15	#include <linux/kernel.h>
1da177e4	16	#include <linux/init.h>
1da177e4	17	#include <linux/sysdev.h>
a21765a7	18	#include <linux/serial_core.h>
1da177e4	19
a09e64fb	20	#include <mach/dma.h>
a21765a7	21
a2b7ba9c	22	#include <plat/cpu.h>
d5120ae7	23	#include <plat/dma.h>
a21765a7	24
a2b7ba9c	25	#include <plat/regs-serial.h>
a09e64fb	26	#include <mach/regs-gpio.h>
f74c95c2	27	#include <plat/regs-ac97.h>
a09e64fb RK	28	#include <mach/regs-mem.h>
	29	#include <mach/regs-lcd.h>
	30	#include <mach/regs-sdi.h>
06cfa556	31	#include <asm/plat-s3c24xx/regs-iis.h>
13622708	32	#include <plat/regs-spi.h>
a21765a7 BD	33
	34	static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
	35	[DMACH_XD0] = {
	36	.name = "xdreq0",
	37	.channels[0] = S3C2410_DCON_CH0_XDREQ0 \| DMA_CH_VALID,
	38	},
	39	[DMACH_XD1] = {
	40	.name = "xdreq1",
	41	.channels[1] = S3C2410_DCON_CH1_XDREQ1 \| DMA_CH_VALID,
	42	},
	43	[DMACH_SDI] = {
	44	.name = "sdi",
	45	.channels[0] = S3C2410_DCON_CH0_SDI \| DMA_CH_VALID,
	46	.channels[2] = S3C2410_DCON_CH2_SDI \| DMA_CH_VALID,
	47	.channels[3] = S3C2410_DCON_CH3_SDI \| DMA_CH_VALID,
	48	.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
	49	.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
	50	},
	51	[DMACH_SPI0] = {
	52	.name = "spi0",
	53	.channels[1] = S3C2410_DCON_CH1_SPI \| DMA_CH_VALID,
	54	.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
	55	.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
	56	},
	57	[DMACH_SPI1] = {
	58	.name = "spi1",
	59	.channels[3] = S3C2410_DCON_CH3_SPI \| DMA_CH_VALID,
	60	.hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
	61	.hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
	62	},
	63	[DMACH_UART0] = {
	64	.name = "uart0",
	65	.channels[0] = S3C2410_DCON_CH0_UART0 \| DMA_CH_VALID,
	66	.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
	67	.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
	68	},
	69	[DMACH_UART1] = {
	70	.name = "uart1",
	71	.channels[1] = S3C2410_DCON_CH1_UART1 \| DMA_CH_VALID,
	72	.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
	73	.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
	74	},
	75	[DMACH_UART2] = {
	76	.name = "uart2",
	77	.channels[3] = S3C2410_DCON_CH3_UART2 \| DMA_CH_VALID,
	78	.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
	79	.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
	80	},
	81	[DMACH_TIMER] = {
	82	.name = "timer",
	83	.channels[0] = S3C2410_DCON_CH0_TIMER \| DMA_CH_VALID,
	84	.channels[2] = S3C2410_DCON_CH2_TIMER \| DMA_CH_VALID,
	85	.channels[3] = S3C2410_DCON_CH3_TIMER \| DMA_CH_VALID,
	86	},
	87	[DMACH_I2S_IN] = {
	88	.name = "i2s-sdi",
	89	.channels[1] = S3C2410_DCON_CH1_I2SSDI \| DMA_CH_VALID,
	90	.channels[2] = S3C2410_DCON_CH2_I2SSDI \| DMA_CH_VALID,
	91	.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
	92	},
	93	[DMACH_I2S_OUT] = {
	94	.name = "i2s-sdo",
	95	.channels[2] = S3C2410_DCON_CH2_I2SSDO \| DMA_CH_VALID,
	96	.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
97	},
98	[DMACH_USB_EP1] = {
99	.name = "usb-ep1",
100	.channels[0] = S3C2410_DCON_CH0_USBEP1 \| DMA_CH_VALID,
101	},
102	[DMACH_USB_EP2] = {
103	.name = "usb-ep2",
104	.channels[1] = S3C2410_DCON_CH1_USBEP2 \| DMA_CH_VALID,
105	},
106	[DMACH_USB_EP3] = {
107	.name = "usb-ep3",
108	.channels[2] = S3C2410_DCON_CH2_USBEP3 \| DMA_CH_VALID,
109	},
110	[DMACH_USB_EP4] = {
111	.name = "usb-ep4",
112	.channels[3] =S3C2410_DCON_CH3_USBEP4 \| DMA_CH_VALID,
113	},
1da177e4 LT	114	};
1da177e4 LT	115
a21765a7 BD	116	static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
a21765a7 BD	117	struct s3c24xx_dma_map *map)
1da177e4	118	{
a21765a7	119	chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
1da177e4 LT	120	}
1da177e4 LT	121
a21765a7 BD	122	static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
	123	.select = s3c2410_dma_select,
	124	.dcon_mask = 7 << 24,
	125	.map = s3c2410_dma_mappings,
	126	.map_size = ARRAY_SIZE(s3c2410_dma_mappings),
	127	};
1da177e4	128
dad8d6c5 BD	129	static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
	130	.channels = {
	131	[DMACH_SDI] = {
	132	.list = {
	133	[0] = 3 \| DMA_CH_VALID,
	134	[1] = 2 \| DMA_CH_VALID,
	135	[2] = 0 \| DMA_CH_VALID,
	136	},
	137	},
	138	[DMACH_I2S_IN] = {
	139	.list = {
	140	[0] = 1 \| DMA_CH_VALID,
	141	[1] = 2 \| DMA_CH_VALID,
	142	},
	143	},
	144	},
	145	};
	146
f2c10d6c	147	static int __init s3c2410_dma_add(struct sys_device *sysdev)
1da177e4	148	{
48adbcf3	149	s3c2410_dma_init();
dad8d6c5	150	s3c24xx_dma_order_set(&s3c2410_dma_order);
a21765a7	151	return s3c24xx_dma_init_map(&s3c2410_dma_sel);
1da177e4 LT	152	}
1da177e4 LT	153
a21765a7 BD	154	#if defined(CONFIG_CPU_S3C2410)
	155	static struct sysdev_driver s3c2410_dma_driver = {
	156	.add = s3c2410_dma_add,
	157	};
1da177e4	158
48adbcf3	159	static int __init s3c2410_dma_drvinit(void)
f57e1abd	160	{
a21765a7	161	return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_dma_driver);
f57e1abd BD	162	}
f57e1abd BD	163
48adbcf3	164	arch_initcall(s3c2410_dma_drvinit);
f57e1abd BD	165	#endif
f57e1abd BD	166
a21765a7 BD	167	#if defined(CONFIG_CPU_S3C2442)
	168	/* S3C2442 DMA contains the same selection table as the S3C2410 */
	169	static struct sysdev_driver s3c2442_dma_driver = {
	170	.add = s3c2410_dma_add,
1da177e4 LT	171	};
1da177e4 LT	172
48adbcf3	173	static int __init s3c2442_dma_drvinit(void)
505788cc	174	{
a21765a7	175	return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_dma_driver);
505788cc BD	176	}
505788cc BD	177
48adbcf3	178	arch_initcall(s3c2442_dma_drvinit);
a21765a7	179	#endif
505788cc	180