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a09e64fb | 1 | /* arch/arm/mach-s3c2410/include/mach/map.h |
1da177e4 | 2 | * |
f056076e BD |
3 | * Copyright (c) 2003 Simtec Electronics |
4 | * Ben Dooks <ben@simtec.co.uk> | |
1da177e4 LT |
5 | * |
6 | * S3C2410 - Memory map definitions | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
1da177e4 LT |
11 | */ |
12 | ||
13 | #ifndef __ASM_ARCH_MAP_H | |
14 | #define __ASM_ARCH_MAP_H | |
15 | ||
530ef3c2 | 16 | #include <asm/plat-s3c/map.h> |
1da177e4 | 17 | |
530ef3c2 | 18 | #define S3C2410_ADDR(x) S3C_ADDR(x) |
1da177e4 | 19 | |
1da177e4 LT |
20 | /* interrupt controller is the first thing we put in, to make |
21 | * the assembly code for the irq detection easier | |
22 | */ | |
530ef3c2 | 23 | #define S3C24XX_VA_IRQ S3C_VA_IRQ |
1da177e4 LT |
24 | #define S3C2410_PA_IRQ (0x4A000000) |
25 | #define S3C24XX_SZ_IRQ SZ_1M | |
26 | ||
27 | /* memory controller registers */ | |
530ef3c2 | 28 | #define S3C24XX_VA_MEMCTRL S3C_VA_MEM |
1da177e4 LT |
29 | #define S3C2410_PA_MEMCTRL (0x48000000) |
30 | #define S3C24XX_SZ_MEMCTRL SZ_1M | |
31 | ||
32 | /* USB host controller */ | |
1da177e4 LT |
33 | #define S3C2410_PA_USBHOST (0x49000000) |
34 | #define S3C24XX_SZ_USBHOST SZ_1M | |
35 | ||
36 | /* DMA controller */ | |
1da177e4 LT |
37 | #define S3C2410_PA_DMA (0x4B000000) |
38 | #define S3C24XX_SZ_DMA SZ_1M | |
39 | ||
40 | /* Clock and Power management */ | |
530ef3c2 | 41 | #define S3C24XX_VA_CLKPWR S3C_VA_SYS |
1da177e4 LT |
42 | #define S3C2410_PA_CLKPWR (0x4C000000) |
43 | #define S3C24XX_SZ_CLKPWR SZ_1M | |
44 | ||
45 | /* LCD controller */ | |
1da177e4 LT |
46 | #define S3C2410_PA_LCD (0x4D000000) |
47 | #define S3C24XX_SZ_LCD SZ_1M | |
48 | ||
49 | /* NAND flash controller */ | |
1da177e4 LT |
50 | #define S3C2410_PA_NAND (0x4E000000) |
51 | #define S3C24XX_SZ_NAND SZ_1M | |
52 | ||
1da177e4 | 53 | /* UARTs */ |
530ef3c2 | 54 | #define S3C24XX_VA_UART S3C_VA_UART |
1da177e4 LT |
55 | #define S3C2410_PA_UART (0x50000000) |
56 | #define S3C24XX_SZ_UART SZ_1M | |
57 | ||
58 | /* Timers */ | |
530ef3c2 | 59 | #define S3C24XX_VA_TIMER S3C_VA_TIMER |
1da177e4 LT |
60 | #define S3C2410_PA_TIMER (0x51000000) |
61 | #define S3C24XX_SZ_TIMER SZ_1M | |
62 | ||
63 | /* USB Device port */ | |
1da177e4 LT |
64 | #define S3C2410_PA_USBDEV (0x52000000) |
65 | #define S3C24XX_SZ_USBDEV SZ_1M | |
66 | ||
67 | /* Watchdog */ | |
530ef3c2 | 68 | #define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG |
1da177e4 LT |
69 | #define S3C2410_PA_WATCHDOG (0x53000000) |
70 | #define S3C24XX_SZ_WATCHDOG SZ_1M | |
71 | ||
72 | /* IIC hardware controller */ | |
1da177e4 LT |
73 | #define S3C2410_PA_IIC (0x54000000) |
74 | #define S3C24XX_SZ_IIC SZ_1M | |
75 | ||
1da177e4 | 76 | /* IIS controller */ |
1da177e4 LT |
77 | #define S3C2410_PA_IIS (0x55000000) |
78 | #define S3C24XX_SZ_IIS SZ_1M | |
79 | ||
80 | /* GPIO ports */ | |
68d59693 BD |
81 | |
82 | /* the calculation for the VA of this must ensure that | |
83 | * it is the same distance apart from the UART in the | |
84 | * phsyical address space, as the initial mapping for the IO | |
85 | * is done as a 1:1 maping. This puts it (currently) at | |
530ef3c2 | 86 | * 0xFA800000, which is not in the way of any current mapping |
68d59693 BD |
87 | * by the base system. |
88 | */ | |
89 | ||
1da177e4 | 90 | #define S3C2410_PA_GPIO (0x56000000) |
68d59693 | 91 | #define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) |
1da177e4 LT |
92 | #define S3C24XX_SZ_GPIO SZ_1M |
93 | ||
94 | /* RTC */ | |
1da177e4 LT |
95 | #define S3C2410_PA_RTC (0x57000000) |
96 | #define S3C24XX_SZ_RTC SZ_1M | |
97 | ||
98 | /* ADC */ | |
1da177e4 LT |
99 | #define S3C2410_PA_ADC (0x58000000) |
100 | #define S3C24XX_SZ_ADC SZ_1M | |
101 | ||
102 | /* SPI */ | |
1da177e4 LT |
103 | #define S3C2410_PA_SPI (0x59000000) |
104 | #define S3C24XX_SZ_SPI SZ_1M | |
105 | ||
106 | /* SDI */ | |
1da177e4 LT |
107 | #define S3C2410_PA_SDI (0x5A000000) |
108 | #define S3C24XX_SZ_SDI SZ_1M | |
109 | ||
110 | /* CAMIF */ | |
111 | #define S3C2440_PA_CAMIF (0x4F000000) | |
112 | #define S3C2440_SZ_CAMIF SZ_1M | |
113 | ||
fd88edd2 BD |
114 | /* AC97 */ |
115 | ||
116 | #define S3C2440_PA_AC97 (0x5B000000) | |
117 | #define S3C2440_SZ_AC97 SZ_1M | |
118 | ||
ece97941 BD |
119 | /* S3C2443 High-speed SD/MMC */ |
120 | #define S3C2443_PA_HSMMC (0x4A800000) | |
121 | #define S3C2443_SZ_HSMMC (256) | |
122 | ||
1da177e4 LT |
123 | /* ISA style IO, for each machine to sort out mappings for, if it |
124 | * implements it. We reserve two 16M regions for ISA. | |
125 | */ | |
126 | ||
127 | #define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) | |
128 | #define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) | |
129 | ||
130 | /* physical addresses of all the chip-select areas */ | |
131 | ||
132 | #define S3C2410_CS0 (0x00000000) | |
133 | #define S3C2410_CS1 (0x08000000) | |
134 | #define S3C2410_CS2 (0x10000000) | |
135 | #define S3C2410_CS3 (0x18000000) | |
136 | #define S3C2410_CS4 (0x20000000) | |
137 | #define S3C2410_CS5 (0x28000000) | |
138 | #define S3C2410_CS6 (0x30000000) | |
139 | #define S3C2410_CS7 (0x38000000) | |
140 | ||
141 | #define S3C2410_SDRAM_PA (S3C2410_CS6) | |
142 | ||
0367a8d3 LCVR |
143 | /* Use a single interface for common resources between S3C24XX cpus */ |
144 | ||
0367a8d3 LCVR |
145 | #define S3C24XX_PA_IRQ S3C2410_PA_IRQ |
146 | #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL | |
147 | #define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST | |
148 | #define S3C24XX_PA_DMA S3C2410_PA_DMA | |
149 | #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR | |
150 | #define S3C24XX_PA_LCD S3C2410_PA_LCD | |
151 | #define S3C24XX_PA_UART S3C2410_PA_UART | |
152 | #define S3C24XX_PA_TIMER S3C2410_PA_TIMER | |
153 | #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV | |
154 | #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG | |
155 | #define S3C24XX_PA_IIC S3C2410_PA_IIC | |
156 | #define S3C24XX_PA_IIS S3C2410_PA_IIS | |
157 | #define S3C24XX_PA_GPIO S3C2410_PA_GPIO | |
158 | #define S3C24XX_PA_RTC S3C2410_PA_RTC | |
159 | #define S3C24XX_PA_ADC S3C2410_PA_ADC | |
160 | #define S3C24XX_PA_SPI S3C2410_PA_SPI | |
1da177e4 | 161 | |
68d9ab39 BD |
162 | /* deal with the registers that move under the 2412/2413 */ |
163 | ||
164 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) | |
165 | #ifndef __ASSEMBLY__ | |
166 | extern void __iomem *s3c24xx_va_gpio2; | |
167 | #endif | |
168 | #ifdef CONFIG_CPU_S3C2412_ONLY | |
169 | #define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) | |
170 | #else | |
171 | #define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 | |
172 | #endif | |
173 | #else | |
174 | #define s3c24xx_va_gpio2 S3C24XX_VA_GPIO | |
175 | #define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO | |
176 | #endif | |
177 | ||
1da177e4 | 178 | #endif /* __ASM_ARCH_MAP_H */ |