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1da177e4 LT |
1 | /* linux/arch/arm/mach-s3c2410/mach-bast.c |
2 | * | |
3 | * Copyright (c) 2003-2005 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * http://www.simtec.co.uk/products/EB2410ITX/ | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Modifications: | |
13 | * 14-Sep-2004 BJD USB power control | |
14 | * 20-Aug-2004 BJD Added s3c2410_board struct | |
15 | * 18-Aug-2004 BJD Added platform devices from default set | |
16 | * 16-May-2003 BJD Created initial version | |
17 | * 16-Aug-2003 BJD Fixed header files and copyright, added URL | |
18 | * 05-Sep-2003 BJD Moved to v2.6 kernel | |
19 | * 06-Jan-2003 BJD Updates for <arch/map.h> | |
20 | * 18-Jan-2003 BJD Added serial port configuration | |
21 | * 05-Oct-2004 BJD Power management code | |
22 | * 04-Nov-2004 BJD Updated serial port clocks | |
23 | * 04-Jan-2005 BJD New uart init call | |
24 | * 10-Jan-2005 BJD Removed include of s3c2410.h | |
25 | * 14-Jan-2005 BJD Add support for muitlple NAND devices | |
26 | * 03-Mar-2005 BJD Ensured that bast-cpld.h is included | |
27 | * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA | |
5730b7d6 BD |
28 | * 14-Mar-2005 BJD Updated for __iomem changes |
29 | * 22-Jun-2005 BJD Added DM9000 platform information | |
30 | * 28-Jun-2005 BJD Moved pm functionality out to common code | |
31 | * 17-Jul-2005 BJD Changed to platform device for SuperIO 16550s | |
32 | * 25-Jul-2005 BJD Removed ASIX static mappings | |
1fcf8448 | 33 | * 27-Jul-2005 BJD Ensure maximum frequency of i2c bus |
5fe10ab1 | 34 | * 20-Sep-2005 BJD Added static to non-exported items |
1da177e4 LT |
35 | */ |
36 | ||
37 | #include <linux/kernel.h> | |
38 | #include <linux/types.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/list.h> | |
41 | #include <linux/timer.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/device.h> | |
d97a666f | 44 | #include <linux/dm9000.h> |
1da177e4 LT |
45 | |
46 | #include <asm/mach/arch.h> | |
47 | #include <asm/mach/map.h> | |
48 | #include <asm/mach/irq.h> | |
49 | ||
50 | #include <asm/arch/bast-map.h> | |
51 | #include <asm/arch/bast-irq.h> | |
52 | #include <asm/arch/bast-cpld.h> | |
53 | ||
54 | #include <asm/hardware.h> | |
55 | #include <asm/io.h> | |
56 | #include <asm/irq.h> | |
57 | #include <asm/mach-types.h> | |
58 | ||
59 | //#include <asm/debug-ll.h> | |
60 | #include <asm/arch/regs-serial.h> | |
61 | #include <asm/arch/regs-gpio.h> | |
62 | #include <asm/arch/regs-mem.h> | |
d97a666f | 63 | #include <asm/arch/regs-lcd.h> |
1da177e4 | 64 | #include <asm/arch/nand.h> |
1fcf8448 | 65 | #include <asm/arch/iic.h> |
1da177e4 LT |
66 | |
67 | #include <linux/mtd/mtd.h> | |
68 | #include <linux/mtd/nand.h> | |
69 | #include <linux/mtd/nand_ecc.h> | |
70 | #include <linux/mtd/partitions.h> | |
71 | ||
65cc3370 BD |
72 | #include <linux/serial_8250.h> |
73 | ||
1da177e4 LT |
74 | #include "clock.h" |
75 | #include "devs.h" | |
76 | #include "cpu.h" | |
77 | #include "usb-simtec.h" | |
1da177e4 LT |
78 | |
79 | #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics" | |
80 | ||
81 | /* macros for virtual address mods for the io space entries */ | |
82 | #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5) | |
83 | #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4) | |
84 | #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3) | |
85 | #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2) | |
86 | ||
87 | /* macros to modify the physical addresses for io space */ | |
88 | ||
89 | #define PA_CS2(item) ((item) + S3C2410_CS2) | |
90 | #define PA_CS3(item) ((item) + S3C2410_CS3) | |
91 | #define PA_CS4(item) ((item) + S3C2410_CS4) | |
92 | #define PA_CS5(item) ((item) + S3C2410_CS5) | |
93 | ||
94 | static struct map_desc bast_iodesc[] __initdata = { | |
95 | /* ISA IO areas */ | |
96 | ||
97 | { (u32)S3C24XX_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
98 | { (u32)S3C24XX_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
99 | ||
100 | /* we could possibly compress the next set down into a set of smaller tables | |
101 | * pagetables, but that would mean using an L2 section, and it still means | |
102 | * we cannot actually feed the same register to an LDR due to 16K spacing | |
103 | */ | |
104 | ||
105 | /* bast CPLD control registers, and external interrupt controls */ | |
106 | { (u32)BAST_VA_CTRL1, BAST_PA_CTRL1, SZ_1M, MT_DEVICE }, | |
107 | { (u32)BAST_VA_CTRL2, BAST_PA_CTRL2, SZ_1M, MT_DEVICE }, | |
108 | { (u32)BAST_VA_CTRL3, BAST_PA_CTRL3, SZ_1M, MT_DEVICE }, | |
109 | { (u32)BAST_VA_CTRL4, BAST_PA_CTRL4, SZ_1M, MT_DEVICE }, | |
110 | ||
111 | /* PC104 IRQ mux */ | |
112 | { (u32)BAST_VA_PC104_IRQREQ, BAST_PA_PC104_IRQREQ, SZ_1M, MT_DEVICE }, | |
113 | { (u32)BAST_VA_PC104_IRQRAW, BAST_PA_PC104_IRQRAW, SZ_1M, MT_DEVICE }, | |
114 | { (u32)BAST_VA_PC104_IRQMASK, BAST_PA_PC104_IRQMASK, SZ_1M, MT_DEVICE }, | |
115 | ||
116 | /* peripheral space... one for each of fast/slow/byte/16bit */ | |
117 | /* note, ide is only decoded in word space, even though some registers | |
118 | * are only 8bit */ | |
119 | ||
120 | /* slow, byte */ | |
121 | { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
122 | { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, | |
1da177e4 | 123 | { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, |
1da177e4 LT |
124 | { VA_C2(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE }, |
125 | { VA_C2(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE }, | |
126 | { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE }, | |
127 | { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE }, | |
128 | ||
129 | /* slow, word */ | |
130 | { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
131 | { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, | |
1da177e4 | 132 | { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, |
1da177e4 LT |
133 | { VA_C3(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE }, |
134 | { VA_C3(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE }, | |
135 | { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE }, | |
136 | { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE }, | |
137 | ||
138 | /* fast, byte */ | |
139 | { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
140 | { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, | |
1da177e4 | 141 | { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, |
1da177e4 LT |
142 | { VA_C4(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE }, |
143 | { VA_C4(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE }, | |
144 | { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE }, | |
145 | { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE }, | |
146 | ||
147 | /* fast, word */ | |
148 | { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
149 | { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, | |
1da177e4 | 150 | { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, |
1da177e4 LT |
151 | { VA_C5(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE }, |
152 | { VA_C5(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE }, | |
153 | { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE }, | |
154 | { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE }, | |
155 | }; | |
156 | ||
157 | #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK | |
158 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | |
159 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE | |
160 | ||
161 | static struct s3c24xx_uart_clksrc bast_serial_clocks[] = { | |
162 | [0] = { | |
163 | .name = "uclk", | |
164 | .divisor = 1, | |
165 | .min_baud = 0, | |
166 | .max_baud = 0, | |
167 | }, | |
168 | [1] = { | |
169 | .name = "pclk", | |
170 | .divisor = 1, | |
171 | .min_baud = 0, | |
172 | .max_baud = 0. | |
173 | } | |
174 | }; | |
175 | ||
176 | ||
177 | static struct s3c2410_uartcfg bast_uartcfgs[] = { | |
178 | [0] = { | |
179 | .hwport = 0, | |
180 | .flags = 0, | |
181 | .ucon = UCON, | |
182 | .ulcon = ULCON, | |
183 | .ufcon = UFCON, | |
184 | .clocks = bast_serial_clocks, | |
185 | .clocks_size = ARRAY_SIZE(bast_serial_clocks) | |
186 | }, | |
187 | [1] = { | |
188 | .hwport = 1, | |
189 | .flags = 0, | |
190 | .ucon = UCON, | |
191 | .ulcon = ULCON, | |
192 | .ufcon = UFCON, | |
193 | .clocks = bast_serial_clocks, | |
194 | .clocks_size = ARRAY_SIZE(bast_serial_clocks) | |
195 | }, | |
196 | /* port 2 is not actually used */ | |
197 | [2] = { | |
198 | .hwport = 2, | |
199 | .flags = 0, | |
200 | .ucon = UCON, | |
201 | .ulcon = ULCON, | |
202 | .ufcon = UFCON, | |
203 | .clocks = bast_serial_clocks, | |
204 | .clocks_size = ARRAY_SIZE(bast_serial_clocks) | |
205 | } | |
206 | }; | |
207 | ||
208 | /* NOR Flash on BAST board */ | |
209 | ||
210 | static struct resource bast_nor_resource[] = { | |
211 | [0] = { | |
212 | .start = S3C2410_CS1 + 0x4000000, | |
213 | .end = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1, | |
214 | .flags = IORESOURCE_MEM, | |
215 | } | |
216 | }; | |
217 | ||
218 | static struct platform_device bast_device_nor = { | |
219 | .name = "bast-nor", | |
220 | .id = -1, | |
221 | .num_resources = ARRAY_SIZE(bast_nor_resource), | |
222 | .resource = bast_nor_resource, | |
223 | }; | |
224 | ||
225 | /* NAND Flash on BAST board */ | |
226 | ||
227 | ||
228 | static int smartmedia_map[] = { 0 }; | |
229 | static int chip0_map[] = { 1 }; | |
230 | static int chip1_map[] = { 2 }; | |
231 | static int chip2_map[] = { 3 }; | |
232 | ||
233 | struct mtd_partition bast_default_nand_part[] = { | |
234 | [0] = { | |
235 | .name = "Boot Agent", | |
236 | .size = SZ_16K, | |
237 | .offset = 0 | |
238 | }, | |
239 | [1] = { | |
240 | .name = "/boot", | |
241 | .size = SZ_4M - SZ_16K, | |
242 | .offset = SZ_16K, | |
243 | }, | |
244 | [2] = { | |
245 | .name = "user", | |
246 | .offset = SZ_4M, | |
247 | .size = MTDPART_SIZ_FULL, | |
248 | } | |
249 | }; | |
250 | ||
251 | /* the bast has 4 selectable slots for nand-flash, the three | |
252 | * on-board chip areas, as well as the external SmartMedia | |
253 | * slot. | |
254 | * | |
255 | * Note, there is no current hot-plug support for the SmartMedia | |
256 | * socket. | |
257 | */ | |
258 | ||
259 | static struct s3c2410_nand_set bast_nand_sets[] = { | |
260 | [0] = { | |
261 | .name = "SmartMedia", | |
262 | .nr_chips = 1, | |
263 | .nr_map = smartmedia_map, | |
264 | .nr_partitions = ARRAY_SIZE(bast_default_nand_part), | |
265 | .partitions = bast_default_nand_part | |
266 | }, | |
267 | [1] = { | |
268 | .name = "chip0", | |
269 | .nr_chips = 1, | |
270 | .nr_map = chip0_map, | |
271 | .nr_partitions = ARRAY_SIZE(bast_default_nand_part), | |
272 | .partitions = bast_default_nand_part | |
273 | }, | |
274 | [2] = { | |
275 | .name = "chip1", | |
276 | .nr_chips = 1, | |
277 | .nr_map = chip1_map, | |
278 | .nr_partitions = ARRAY_SIZE(bast_default_nand_part), | |
279 | .partitions = bast_default_nand_part | |
280 | }, | |
281 | [3] = { | |
282 | .name = "chip2", | |
283 | .nr_chips = 1, | |
284 | .nr_map = chip2_map, | |
285 | .nr_partitions = ARRAY_SIZE(bast_default_nand_part), | |
286 | .partitions = bast_default_nand_part | |
287 | } | |
288 | }; | |
289 | ||
290 | static void bast_nand_select(struct s3c2410_nand_set *set, int slot) | |
291 | { | |
292 | unsigned int tmp; | |
293 | ||
294 | slot = set->nr_map[slot] & 3; | |
295 | ||
296 | pr_debug("bast_nand: selecting slot %d (set %p,%p)\n", | |
297 | slot, set, set->nr_map); | |
298 | ||
299 | tmp = __raw_readb(BAST_VA_CTRL2); | |
300 | tmp &= BAST_CPLD_CTLR2_IDERST; | |
301 | tmp |= slot; | |
302 | tmp |= BAST_CPLD_CTRL2_WNAND; | |
303 | ||
304 | pr_debug("bast_nand: ctrl2 now %02x\n", tmp); | |
305 | ||
306 | __raw_writeb(tmp, BAST_VA_CTRL2); | |
307 | } | |
308 | ||
309 | static struct s3c2410_platform_nand bast_nand_info = { | |
1fcf8448 | 310 | .tacls = 40, |
1da177e4 LT |
311 | .twrph0 = 80, |
312 | .twrph1 = 80, | |
313 | .nr_sets = ARRAY_SIZE(bast_nand_sets), | |
314 | .sets = bast_nand_sets, | |
315 | .select_chip = bast_nand_select, | |
316 | }; | |
317 | ||
d97a666f BD |
318 | /* DM9000 */ |
319 | ||
320 | static struct resource bast_dm9k_resource[] = { | |
321 | [0] = { | |
322 | .start = S3C2410_CS5 + BAST_PA_DM9000, | |
323 | .end = S3C2410_CS5 + BAST_PA_DM9000 + 3, | |
324 | .flags = IORESOURCE_MEM | |
325 | }, | |
326 | [1] = { | |
327 | .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40, | |
328 | .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f, | |
329 | .flags = IORESOURCE_MEM | |
330 | }, | |
331 | [2] = { | |
332 | .start = IRQ_DM9000, | |
333 | .end = IRQ_DM9000, | |
334 | .flags = IORESOURCE_IRQ | |
335 | } | |
336 | ||
337 | }; | |
338 | ||
339 | /* for the moment we limit ourselves to 16bit IO until some | |
340 | * better IO routines can be written and tested | |
341 | */ | |
342 | ||
343 | struct dm9000_plat_data bast_dm9k_platdata = { | |
344 | .flags = DM9000_PLATF_16BITONLY | |
345 | }; | |
346 | ||
347 | static struct platform_device bast_device_dm9k = { | |
348 | .name = "dm9000", | |
349 | .id = 0, | |
350 | .num_resources = ARRAY_SIZE(bast_dm9k_resource), | |
351 | .resource = bast_dm9k_resource, | |
352 | .dev = { | |
353 | .platform_data = &bast_dm9k_platdata, | |
354 | } | |
355 | }; | |
356 | ||
65cc3370 BD |
357 | /* serial devices */ |
358 | ||
359 | #define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO) | |
360 | #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ) | |
361 | #define SERIAL_CLK (1843200) | |
362 | ||
363 | static struct plat_serial8250_port bast_sio_data[] = { | |
364 | [0] = { | |
365 | .mapbase = SERIAL_BASE + 0x2f8, | |
366 | .irq = IRQ_PCSERIAL1, | |
367 | .flags = SERIAL_FLAGS, | |
368 | .iotype = UPIO_MEM, | |
369 | .regshift = 0, | |
370 | .uartclk = SERIAL_CLK, | |
371 | }, | |
372 | [1] = { | |
373 | .mapbase = SERIAL_BASE + 0x3f8, | |
374 | .irq = IRQ_PCSERIAL2, | |
375 | .flags = SERIAL_FLAGS, | |
376 | .iotype = UPIO_MEM, | |
377 | .regshift = 0, | |
378 | .uartclk = SERIAL_CLK, | |
379 | }, | |
380 | { } | |
381 | }; | |
382 | ||
383 | static struct platform_device bast_sio = { | |
384 | .name = "serial8250", | |
6df29deb | 385 | .id = PLAT8250_DEV_PLATFORM, |
65cc3370 BD |
386 | .dev = { |
387 | .platform_data = &bast_sio_data, | |
388 | }, | |
389 | }; | |
1da177e4 | 390 | |
1fcf8448 BD |
391 | /* we have devices on the bus which cannot work much over the |
392 | * standard 100KHz i2c bus frequency | |
393 | */ | |
394 | ||
395 | static struct s3c2410_platform_i2c bast_i2c_info = { | |
396 | .flags = 0, | |
397 | .slave_addr = 0x10, | |
398 | .bus_freq = 100*1000, | |
399 | .max_freq = 130*1000, | |
400 | }; | |
401 | ||
1da177e4 LT |
402 | /* Standard BAST devices */ |
403 | ||
404 | static struct platform_device *bast_devices[] __initdata = { | |
405 | &s3c_device_usb, | |
406 | &s3c_device_lcd, | |
407 | &s3c_device_wdt, | |
408 | &s3c_device_i2c, | |
409 | &s3c_device_iis, | |
410 | &s3c_device_rtc, | |
411 | &s3c_device_nand, | |
d97a666f BD |
412 | &bast_device_nor, |
413 | &bast_device_dm9k, | |
65cc3370 | 414 | &bast_sio, |
1da177e4 LT |
415 | }; |
416 | ||
417 | static struct clk *bast_clocks[] = { | |
418 | &s3c24xx_dclk0, | |
419 | &s3c24xx_dclk1, | |
420 | &s3c24xx_clkout0, | |
421 | &s3c24xx_clkout1, | |
422 | &s3c24xx_uclk, | |
423 | }; | |
424 | ||
425 | static struct s3c24xx_board bast_board __initdata = { | |
426 | .devices = bast_devices, | |
427 | .devices_count = ARRAY_SIZE(bast_devices), | |
428 | .clocks = bast_clocks, | |
429 | .clocks_count = ARRAY_SIZE(bast_clocks) | |
430 | }; | |
431 | ||
5fe10ab1 | 432 | static void __init bast_map_io(void) |
1da177e4 LT |
433 | { |
434 | /* initialise the clocks */ | |
435 | ||
436 | s3c24xx_dclk0.parent = NULL; | |
437 | s3c24xx_dclk0.rate = 12*1000*1000; | |
438 | ||
439 | s3c24xx_dclk1.parent = NULL; | |
440 | s3c24xx_dclk1.rate = 24*1000*1000; | |
441 | ||
442 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; | |
443 | s3c24xx_clkout1.parent = &s3c24xx_dclk1; | |
444 | ||
445 | s3c24xx_uclk.parent = &s3c24xx_clkout1; | |
446 | ||
447 | s3c_device_nand.dev.platform_data = &bast_nand_info; | |
1fcf8448 | 448 | s3c_device_i2c.dev.platform_data = &bast_i2c_info; |
1da177e4 LT |
449 | |
450 | s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); | |
451 | s3c24xx_init_clocks(0); | |
452 | s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); | |
453 | s3c24xx_set_board(&bast_board); | |
454 | usb_simtec_init(); | |
455 | } | |
456 | ||
1da177e4 LT |
457 | |
458 | MACHINE_START(BAST, "Simtec-BAST") | |
e9dea0c6 RK |
459 | /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ |
460 | .phys_ram = S3C2410_SDRAM_PA, | |
461 | .phys_io = S3C2410_PA_UART, | |
462 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | |
463 | .boot_params = S3C2410_SDRAM_PA + 0x100, | |
f705b1ae BD |
464 | .map_io = bast_map_io, |
465 | .init_irq = s3c24xx_init_irq, | |
1da177e4 LT |
466 | .timer = &s3c24xx_timer, |
467 | MACHINE_END |