[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-s3c2410 / mach-bast.c

/* linux/arch/arm/mach-s3c2410/mach-bast.c
 *
 * Copyright (c) 2003-2005,2008 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.simtec.co.uk/products/EB2410ITX/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/dm9000.h>
#include <linux/ata_platform.h>
#include <linux/i2c.h>
#include <linux/io.h>

#include <net/ax88796.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/bast-map.h>
#include <mach/bast-irq.h>
#include <mach/bast-cpld.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

//#include <asm/debug-ll.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>

#include <plat/hwmon.h>
#include <plat/nand.h>
#include <plat/iic.h>
#include <mach/fb.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <linux/serial_8250.h>

#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/cpu-freq.h>

#include "usb-simtec.h"
#include "nor-simtec.h"

#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"

/* macros for virtual address mods for the io space entries */
#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)

/* macros to modify the physical addresses for io space */

#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))

static struct map_desc bast_iodesc[] __initdata = {
  /* ISA IO areas */
  {
	  .virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	  .pfn		= PA_CS2(BAST_PA_ISAIO),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)S3C24XX_VA_ISA_WORD,
	  .pfn		= PA_CS3(BAST_PA_ISAIO),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  },
  /* bast CPLD control registers, and external interrupt controls */
  {
	  .virtual	= (u32)BAST_VA_CTRL1,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL1),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL2,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL2),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL3,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL3),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL4,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL4),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  },
  /* PC104 IRQ mux */
  {
	  .virtual	= (u32)BAST_VA_PC104_IRQREQ,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQREQ),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_PC104_IRQRAW,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQRAW),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_PC104_IRQMASK,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQMASK),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  },

  /* peripheral space... one for each of fast/slow/byte/16bit */
  /* note, ide is only decoded in word space, even though some registers
   * are only 8bit */

  /* slow, byte */
  { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* slow, word */
  { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* fast, byte */
  { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* fast, word */
  { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
	[0] = {
		.name		= "uclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	},
	[1] = {
		.name		= "pclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};


static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	},
	/* port 2 is not actually used */
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	}
};

/* NAND Flash on BAST board */

#ifdef CONFIG_PM
static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
{
	/* ensure that an nRESET is not generated on resume. */
	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);

	return 0;
}

static int bast_pm_resume(struct sys_device *sd)
{
	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
	return 0;
}

#else
#define bast_pm_suspend NULL
#define bast_pm_resume NULL
#endif

static struct sysdev_class bast_pm_sysclass = {
	.name		= "mach-bast",
	.suspend	= bast_pm_suspend,
	.resume		= bast_pm_resume,
};

static struct sys_device bast_pm_sysdev = {
	.cls		= &bast_pm_sysclass,
};

static int smartmedia_map[] = { 0 };
static int chip0_map[] = { 1 };
static int chip1_map[] = { 2 };
static int chip2_map[] = { 3 };

static struct mtd_partition bast_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user",
		.offset	= SZ_4M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the bast has 4 selectable slots for nand-flash, the three
 * on-board chip areas, as well as the external SmartMedia
 * slot.
 *
 * Note, there is no current hot-plug support for the SmartMedia
 * socket.
*/

static struct s3c2410_nand_set bast_nand_sets[] = {
	[0] = {
		.name		= "SmartMedia",
		.nr_chips	= 1,
		.nr_map		= smartmedia_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[1] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[3] = {
		.name		= "chip2",
		.nr_chips	= 1,
		.nr_map		= chip2_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	}
};

static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(BAST_VA_CTRL2);
	tmp &= BAST_CPLD_CTLR2_IDERST;
	tmp |= slot;
	tmp |= BAST_CPLD_CTRL2_WNAND;

	pr_debug("bast_nand: ctrl2 now %02x\n", tmp);

	__raw_writeb(tmp, BAST_VA_CTRL2);
}

static struct s3c2410_platform_nand bast_nand_info = {
	.tacls		= 30,
	.twrph0		= 60,
	.twrph1		= 60,
	.nr_sets	= ARRAY_SIZE(bast_nand_sets),
	.sets		= bast_nand_sets,
	.select_chip	= bast_nand_select,
};

/* DM9000 */

static struct resource bast_dm9k_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_DM9000,
		.end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
		.end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
		.flags = IORESOURCE_MEM,
	},
	[2] = {
		.start = IRQ_DM9000,
		.end   = IRQ_DM9000,
		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	}

};

/* for the moment we limit ourselves to 16bit IO until some
 * better IO routines can be written and tested
*/

static struct dm9000_plat_data bast_dm9k_platdata = {
	.flags		= DM9000_PLATF_16BITONLY,
};

static struct platform_device bast_device_dm9k = {
	.name		= "dm9000",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_dm9k_resource),
	.resource	= bast_dm9k_resource,
	.dev		= {
		.platform_data = &bast_dm9k_platdata,
	}
};

/* serial devices */

#define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
#define SERIAL_CLK   (1843200)

static struct plat_serial8250_port bast_sio_data[] = {
	[0] = {
		.mapbase	= SERIAL_BASE + 0x2f8,
		.irq		= IRQ_PCSERIAL1,
		.flags		= SERIAL_FLAGS,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= SERIAL_CLK,
	},
	[1] = {
		.mapbase	= SERIAL_BASE + 0x3f8,
		.irq		= IRQ_PCSERIAL2,
		.flags		= SERIAL_FLAGS,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= SERIAL_CLK,
	},
	{ }
};

static struct platform_device bast_sio = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= &bast_sio_data,
	},
};

/* we have devices on the bus which cannot work much over the
 * standard 100KHz i2c bus frequency
*/

static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
	.flags		= 0,
	.slave_addr	= 0x10,
	.frequency	= 100*1000,
};

/* Asix AX88796 10/100 ethernet controller */

static struct ax_plat_data bast_asix_platdata = {
	.flags		= AXFLG_MAC_FROMDEV,
	.wordlength	= 2,
	.dcr_val	= 0x48,
	.rcr_val	= 0x40,
};

static struct resource bast_asix_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET,
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
		.flags = IORESOURCE_MEM,
	},
	[2] = {
		.start = IRQ_ASIX,
		.end   = IRQ_ASIX,
		.flags = IORESOURCE_IRQ
	}
};

static struct platform_device bast_device_asix = {
	.name		= "ax88796",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_asix_resource),
	.resource	= bast_asix_resource,
	.dev		= {
		.platform_data = &bast_asix_platdata
	}
};

/* Asix AX88796 10/100 ethernet controller parallel port */

static struct resource bast_asixpp_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
		.flags = IORESOURCE_MEM,
	}
};

static struct platform_device bast_device_axpp = {
	.name		= "ax88796-pp",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_asixpp_resource),
	.resource	= bast_asixpp_resource,
};

/* LCD/VGA controller */

static struct s3c2410fb_display __initdata bast_lcd_info[] = {
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 4,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 8,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 16,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
};

/* LCD/VGA controller */

static struct s3c2410fb_mach_info __initdata bast_fb_info = {

	.displays = bast_lcd_info,
	.num_displays = ARRAY_SIZE(bast_lcd_info),
	.default_display = 1,
};

/* I2C devices fitted. */

static struct i2c_board_info bast_i2c_devs[] __initdata = {
	{
		I2C_BOARD_INFO("tlv320aic23", 0x1a),
	}, {
		I2C_BOARD_INFO("simtec-pmu", 0x6b),
	}, {
		I2C_BOARD_INFO("ch7013", 0x75),
	},
};

static struct s3c_hwmon_pdata bast_hwmon_info = {
	/* LCD contrast (0-6.6V) */
	.in[0] = &(struct s3c_hwmon_chcfg) {
		.name		= "lcd-contrast",
		.mult		= 3300,
		.div		= 512,
	},
	/* LED current feedback */
	.in[1] = &(struct s3c_hwmon_chcfg) {
		.name		= "led-feedback",
		.mult		= 3300,
		.div		= 1024,
	},
	/* LCD feedback (0-6.6V) */
	.in[2] = &(struct s3c_hwmon_chcfg) {
		.name		= "lcd-feedback",
		.mult		= 3300,
		.div		= 512,
	},
	/* Vcore (1.8-2.0V), Vref 3.3V  */
	.in[3] = &(struct s3c_hwmon_chcfg) {
		.name		= "vcore",
		.mult		= 3300,
		.div		= 1024,
	},
};

/* Standard BAST devices */
// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0

static struct platform_device *bast_devices[] __initdata = {
	&s3c_device_usb,
	&s3c_device_lcd,
	&s3c_device_wdt,
	&s3c_device_i2c0,
 	&s3c_device_rtc,
	&s3c_device_nand,
	&s3c_device_adc,
	&s3c_device_hwmon,
	&bast_device_dm9k,
	&bast_device_asix,
	&bast_device_axpp,
	&bast_sio,
};

static struct clk *bast_clocks[] __initdata = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static struct s3c_cpufreq_board __initdata bast_cpufreq = {
	.refresh	= 7800, /* 7.8usec */
	.auto_io	= 1,
	.need_io	= 1,
};

static void __init bast_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));

	s3c_device_nand.dev.platform_data = &bast_nand_info;
	s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;

	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
}

static void __init bast_init(void)
{
	sysdev_class_register(&bast_pm_sysclass);
	sysdev_register(&bast_pm_sysdev);

	s3c_i2c0_set_platdata(&bast_i2c_info);
	s3c24xx_fb_set_platdata(&bast_fb_info);
	platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));

	i2c_register_board_info(0, bast_i2c_devs,
				ARRAY_SIZE(bast_i2c_devs));

	usb_simtec_init();
	nor_simtec_init();

	s3c_cpufreq_setboard(&bast_cpufreq);
}

MACHINE_START(BAST, "Simtec-BAST")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= bast_map_io,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= bast_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/* linux/arch/arm/mach-s3c2410/mach-bast.c
1da177e4 LT	2	*
042cf0f2	3	* Copyright (c) 2003-2005,2008 Simtec Electronics
1da177e4 LT	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* http://www.simtec.co.uk/products/EB2410ITX/
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
1da177e4 LT	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/types.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/list.h>
	17	#include <linux/timer.h>
	18	#include <linux/init.h>
ec976d6e	19	#include <linux/gpio.h>
6ddc4b07	20	#include <linux/sysdev.h>
b6d1f542	21	#include <linux/serial_core.h>
d052d1be	22	#include <linux/platform_device.h>
d97a666f	23	#include <linux/dm9000.h>
b7a12d19	24	#include <linux/ata_platform.h>
042cf0f2	25	#include <linux/i2c.h>
fced80c7	26	#include <linux/io.h>
1da177e4	27
5ce4b1fe BD	28	#include <net/ax88796.h>
5ce4b1fe BD	29
1da177e4 LT	30	#include <asm/mach/arch.h>
	31	#include <asm/mach/map.h>
	32	#include <asm/mach/irq.h>
	33
a09e64fb RK	34	#include <mach/bast-map.h>
	35	#include <mach/bast-irq.h>
	36	#include <mach/bast-cpld.h>
1da177e4	37
a09e64fb	38	#include <mach/hardware.h>
1da177e4 LT	39	#include <asm/irq.h>
	40	#include <asm/mach-types.h>
	41
	42	//#include <asm/debug-ll.h>
a2b7ba9c	43	#include <plat/regs-serial.h>
a09e64fb RK	44	#include <mach/regs-gpio.h>
	45	#include <mach/regs-mem.h>
	46	#include <mach/regs-lcd.h>
58c8d570	47
885f9ebe	48	#include <plat/hwmon.h>
7926b5a3	49	#include <plat/nand.h>
9498cb79	50	#include <plat/iic.h>
a09e64fb	51	#include <mach/fb.h>
1da177e4 LT	52
	53	#include <linux/mtd/mtd.h>
	54	#include <linux/mtd/nand.h>
	55	#include <linux/mtd/nand_ecc.h>
	56	#include <linux/mtd/partitions.h>
	57
65cc3370 BD	58	#include <linux/serial_8250.h>
65cc3370 BD	59
d5120ae7	60	#include <plat/clock.h>
a2b7ba9c BD	61	#include <plat/devs.h>
a2b7ba9c BD	62	#include <plat/cpu.h>
ca0b4901	63	#include <plat/cpu-freq.h>
9d529c6e	64
1da177e4	65	#include "usb-simtec.h"
9d529c6e	66	#include "nor-simtec.h"
1da177e4 LT	67
	68	#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
	69
	70	/* macros for virtual address mods for the io space entries */
	71	#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
	72	#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
	73	#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
	74	#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
	75
	76	/* macros to modify the physical addresses for io space */
	77
1d23b65d BD	78	#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
	79	#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
	80	#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
	81	#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
1da177e4 LT	82
	83	static struct map_desc bast_iodesc[] __initdata = {
	84	/* ISA IO areas */
1d23b65d BD	85	{
	86	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	87	.pfn = PA_CS2(BAST_PA_ISAIO),
	88	.length = SZ_16M,
	89	.type = MT_DEVICE,
	90	}, {
	91	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	92	.pfn = PA_CS3(BAST_PA_ISAIO),
	93	.length = SZ_16M,
	94	.type = MT_DEVICE,
	95	},
1da177e4	96	/* bast CPLD control registers, and external interrupt controls */
1d23b65d BD	97	{
	98	.virtual = (u32)BAST_VA_CTRL1,
	99	.pfn = __phys_to_pfn(BAST_PA_CTRL1),
	100	.length = SZ_1M,
	101	.type = MT_DEVICE,
	102	}, {
	103	.virtual = (u32)BAST_VA_CTRL2,
	104	.pfn = __phys_to_pfn(BAST_PA_CTRL2),
	105	.length = SZ_1M,
	106	.type = MT_DEVICE,
	107	}, {
	108	.virtual = (u32)BAST_VA_CTRL3,
	109	.pfn = __phys_to_pfn(BAST_PA_CTRL3),
	110	.length = SZ_1M,
	111	.type = MT_DEVICE,
	112	}, {
	113	.virtual = (u32)BAST_VA_CTRL4,
	114	.pfn = __phys_to_pfn(BAST_PA_CTRL4),
	115	.length = SZ_1M,
	116	.type = MT_DEVICE,
	117	},
1da177e4	118	/* PC104 IRQ mux */
1d23b65d BD	119	{
	120	.virtual = (u32)BAST_VA_PC104_IRQREQ,
	121	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
	122	.length = SZ_1M,
	123	.type = MT_DEVICE,
	124	}, {
	125	.virtual = (u32)BAST_VA_PC104_IRQRAW,
	126	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
	127	.length = SZ_1M,
	128	.type = MT_DEVICE,
	129	}, {
	130	.virtual = (u32)BAST_VA_PC104_IRQMASK,
	131	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
	132	.length = SZ_1M,
	133	.type = MT_DEVICE,
	134	},
1da177e4 LT	135
	136	/* peripheral space... one for each of fast/slow/byte/16bit */
	137	/* note, ide is only decoded in word space, even though some registers
	138	* are only 8bit */
	139
	140	/* slow, byte */
	141	{ VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	142	{ VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	143	{ VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	144
	145	/* slow, word */
	146	{ VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	147	{ VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	148	{ VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	149
	150	/* fast, byte */
	151	{ VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	152	{ VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	153	{ VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	154
	155	/* fast, word */
	156	{ VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	157	{ VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	158	{ VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	159	};
	160
	161	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	162	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	163	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	164
	165	static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
	166	[0] = {
	167	.name = "uclk",
	168	.divisor = 1,
	169	.min_baud = 0,
	170	.max_baud = 0,
	171	},
	172	[1] = {
	173	.name = "pclk",
	174	.divisor = 1,
	175	.min_baud = 0,
b526bf23	176	.max_baud = 0,
1da177e4 LT	177	}
	178	};
	179
	180
66a9b49a	181	static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
1da177e4 LT	182	[0] = {
	183	.hwport = 0,
	184	.flags = 0,
	185	.ucon = UCON,
	186	.ulcon = ULCON,
	187	.ufcon = UFCON,
	188	.clocks = bast_serial_clocks,
b526bf23	189	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	190	},
	191	[1] = {
	192	.hwport = 1,
	193	.flags = 0,
	194	.ucon = UCON,
	195	.ulcon = ULCON,
	196	.ufcon = UFCON,
	197	.clocks = bast_serial_clocks,
b526bf23	198	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	199	},
	200	/* port 2 is not actually used */
	201	[2] = {
	202	.hwport = 2,
	203	.flags = 0,
	204	.ucon = UCON,
	205	.ulcon = ULCON,
	206	.ufcon = UFCON,
	207	.clocks = bast_serial_clocks,
b526bf23	208	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	209	}
	210	};
	211
1da177e4 LT	212	/* NAND Flash on BAST board */
1da177e4 LT	213
6ddc4b07 BD	214	#ifdef CONFIG_PM
	215	static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
	216	{
	217	/* ensure that an nRESET is not generated on resume. */
070276d5 BD	218	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
070276d5 BD	219	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
6ddc4b07 BD	220
	221	return 0;
	222	}
	223
	224	static int bast_pm_resume(struct sys_device *sd)
	225	{
070276d5	226	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
6ddc4b07 BD	227	return 0;
	228	}
	229
	230	#else
	231	#define bast_pm_suspend NULL
	232	#define bast_pm_resume NULL
	233	#endif
	234
	235	static struct sysdev_class bast_pm_sysclass = {
140749e2	236	.name = "mach-bast",
6ddc4b07 BD	237	.suspend = bast_pm_suspend,
	238	.resume = bast_pm_resume,
	239	};
	240
	241	static struct sys_device bast_pm_sysdev = {
	242	.cls = &bast_pm_sysclass,
	243	};
1da177e4 LT	244
	245	static int smartmedia_map[] = { 0 };
	246	static int chip0_map[] = { 1 };
	247	static int chip1_map[] = { 2 };
	248	static int chip2_map[] = { 3 };
	249
9f693d7b	250	static struct mtd_partition bast_default_nand_part[] = {
1da177e4 LT	251	[0] = {
	252	.name = "Boot Agent",
	253	.size = SZ_16K,
b526bf23	254	.offset = 0,
1da177e4 LT	255	},
	256	[1] = {
	257	.name = "/boot",
	258	.size = SZ_4M - SZ_16K,
	259	.offset = SZ_16K,
	260	},
	261	[2] = {
	262	.name = "user",
	263	.offset = SZ_4M,
	264	.size = MTDPART_SIZ_FULL,
	265	}
	266	};
	267
	268	/* the bast has 4 selectable slots for nand-flash, the three
	269	* on-board chip areas, as well as the external SmartMedia
	270	* slot.
	271	*
	272	* Note, there is no current hot-plug support for the SmartMedia
	273	* socket.
	274	*/
	275
	276	static struct s3c2410_nand_set bast_nand_sets[] = {
	277	[0] = {
	278	.name = "SmartMedia",
	279	.nr_chips = 1,
	280	.nr_map = smartmedia_map,
	281	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	282	.partitions = bast_default_nand_part,
1da177e4 LT	283	},
	284	[1] = {
	285	.name = "chip0",
	286	.nr_chips = 1,
	287	.nr_map = chip0_map,
	288	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	289	.partitions = bast_default_nand_part,
1da177e4 LT	290	},
	291	[2] = {
	292	.name = "chip1",
	293	.nr_chips = 1,
	294	.nr_map = chip1_map,
	295	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	296	.partitions = bast_default_nand_part,
1da177e4 LT	297	},
	298	[3] = {
	299	.name = "chip2",
	300	.nr_chips = 1,
	301	.nr_map = chip2_map,
	302	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	303	.partitions = bast_default_nand_part,
1da177e4 LT	304	}
	305	};
	306
	307	static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
	308	{
	309	unsigned int tmp;
	310
	311	slot = set->nr_map[slot] & 3;
	312
	313	pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
	314	slot, set, set->nr_map);
	315
	316	tmp = __raw_readb(BAST_VA_CTRL2);
	317	tmp &= BAST_CPLD_CTLR2_IDERST;
	318	tmp \|= slot;
	319	tmp \|= BAST_CPLD_CTRL2_WNAND;
	320
	321	pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
	322
	323	__raw_writeb(tmp, BAST_VA_CTRL2);
	324	}
	325
	326	static struct s3c2410_platform_nand bast_nand_info = {
b048dbf4 BD	327	.tacls = 30,
	328	.twrph0 = 60,
	329	.twrph1 = 60,
1da177e4 LT	330	.nr_sets = ARRAY_SIZE(bast_nand_sets),
	331	.sets = bast_nand_sets,
	332	.select_chip = bast_nand_select,
	333	};
	334
d97a666f BD	335	/* DM9000 */
	336
	337	static struct resource bast_dm9k_resource[] = {
	338	[0] = {
	339	.start = S3C2410_CS5 + BAST_PA_DM9000,
	340	.end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
b526bf23	341	.flags = IORESOURCE_MEM,
d97a666f BD	342	},
	343	[1] = {
	344	.start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
	345	.end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
b526bf23	346	.flags = IORESOURCE_MEM,
d97a666f BD	347	},
	348	[2] = {
	349	.start = IRQ_DM9000,
	350	.end = IRQ_DM9000,
9cf345e3	351	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
d97a666f BD	352	}
	353
	354	};
	355
	356	/* for the moment we limit ourselves to 16bit IO until some
	357	* better IO routines can be written and tested
	358	*/
	359
9f693d7b	360	static struct dm9000_plat_data bast_dm9k_platdata = {
b526bf23	361	.flags = DM9000_PLATF_16BITONLY,
d97a666f BD	362	};
	363
	364	static struct platform_device bast_device_dm9k = {
	365	.name = "dm9000",
	366	.id = 0,
	367	.num_resources = ARRAY_SIZE(bast_dm9k_resource),
	368	.resource = bast_dm9k_resource,
	369	.dev = {
	370	.platform_data = &bast_dm9k_platdata,
	371	}
	372	};
	373
65cc3370 BD	374	/* serial devices */
	375
	376	#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
	377	#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF \| UPF_IOREMAP \| UPF_SHARE_IRQ)
	378	#define SERIAL_CLK (1843200)
	379
	380	static struct plat_serial8250_port bast_sio_data[] = {
	381	[0] = {
	382	.mapbase = SERIAL_BASE + 0x2f8,
	383	.irq = IRQ_PCSERIAL1,
	384	.flags = SERIAL_FLAGS,
	385	.iotype = UPIO_MEM,
	386	.regshift = 0,
	387	.uartclk = SERIAL_CLK,
	388	},
	389	[1] = {
	390	.mapbase = SERIAL_BASE + 0x3f8,
	391	.irq = IRQ_PCSERIAL2,
	392	.flags = SERIAL_FLAGS,
	393	.iotype = UPIO_MEM,
	394	.regshift = 0,
	395	.uartclk = SERIAL_CLK,
	396	},
	397	{ }
	398	};
	399
	400	static struct platform_device bast_sio = {
	401	.name = "serial8250",
6df29deb	402	.id = PLAT8250_DEV_PLATFORM,
65cc3370 BD	403	.dev = {
	404	.platform_data = &bast_sio_data,
	405	},
	406	};
1da177e4	407
1fcf8448 BD	408	/* we have devices on the bus which cannot work much over the
	409	* standard 100KHz i2c bus frequency
	410	*/
	411
3e1b776c	412	static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
1fcf8448 BD	413	.flags = 0,
1fcf8448 BD	414	.slave_addr = 0x10,
c564e6ae	415	.frequency = 100*1000,
1fcf8448 BD	416	};
1fcf8448 BD	417
5ce4b1fe BD	418	/* Asix AX88796 10/100 ethernet controller */
	419
	420	static struct ax_plat_data bast_asix_platdata = {
	421	.flags = AXFLG_MAC_FROMDEV,
	422	.wordlength = 2,
	423	.dcr_val = 0x48,
	424	.rcr_val = 0x40,
	425	};
	426
	427	static struct resource bast_asix_resource[] = {
	428	[0] = {
	429	.start = S3C2410_CS5 + BAST_PA_ASIXNET,
	430	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
	431	.flags = IORESOURCE_MEM,
	432	},
	433	[1] = {
	434	.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
	435	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
	436	.flags = IORESOURCE_MEM,
	437	},
	438	[2] = {
	439	.start = IRQ_ASIX,
	440	.end = IRQ_ASIX,
	441	.flags = IORESOURCE_IRQ
	442	}
	443	};
	444
	445	static struct platform_device bast_device_asix = {
	446	.name = "ax88796",
	447	.id = 0,
	448	.num_resources = ARRAY_SIZE(bast_asix_resource),
	449	.resource = bast_asix_resource,
	450	.dev = {
	451	.platform_data = &bast_asix_platdata
	452	}
	453	};
	454
	455	/* Asix AX88796 10/100 ethernet controller parallel port */
	456
	457	static struct resource bast_asixpp_resource[] = {
	458	[0] = {
	459	.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
	460	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
	461	.flags = IORESOURCE_MEM,
	462	}
	463	};
	464
	465	static struct platform_device bast_device_axpp = {
	466	.name = "ax88796-pp",
	467	.id = 0,
	468	.num_resources = ARRAY_SIZE(bast_asixpp_resource),
	469	.resource = bast_asixpp_resource,
	470	};
	471
	472	/* LCD/VGA controller */
58c8d570	473
09fe75f6 KH	474	static struct s3c2410fb_display __initdata bast_lcd_info[] = {
09fe75f6 KH	475	{
1f411537	476	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	477	.width = 640,
09fe75f6 KH	478	.height = 480,
5f20f69b	479
69816699	480	.pixclock = 33333,
09fe75f6 KH	481	.xres = 640,
	482	.yres = 480,
	483	.bpp = 4,
1f411537 KH	484	.left_margin = 40,
1f411537 KH	485	.right_margin = 20,
93d11f5a	486	.hsync_len = 88,
5f20f69b KH	487	.upper_margin = 30,
5f20f69b KH	488	.lower_margin = 32,
93d11f5a	489	.vsync_len = 3,
09fe75f6	490
f28ef573	491	.lcdcon5 = 0x00014b02,
58c8d570	492	},
09fe75f6	493	{
1f411537	494	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	495	.width = 640,
	496	.height = 480,
	497
69816699	498	.pixclock = 33333,
09fe75f6 KH	499	.xres = 640,
	500	.yres = 480,
	501	.bpp = 8,
1f411537 KH	502	.left_margin = 40,
1f411537 KH	503	.right_margin = 20,
93d11f5a	504	.hsync_len = 88,
5f20f69b KH	505	.upper_margin = 30,
5f20f69b KH	506	.lower_margin = 32,
93d11f5a	507	.vsync_len = 3,
09fe75f6	508
f28ef573	509	.lcdcon5 = 0x00014b02,
09fe75f6 KH	510	},
09fe75f6 KH	511	{
1f411537	512	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	513	.width = 640,
	514	.height = 480,
	515
69816699	516	.pixclock = 33333,
09fe75f6 KH	517	.xres = 640,
	518	.yres = 480,
	519	.bpp = 16,
1f411537 KH	520	.left_margin = 40,
1f411537 KH	521	.right_margin = 20,
93d11f5a	522	.hsync_len = 88,
5f20f69b KH	523	.upper_margin = 30,
5f20f69b KH	524	.lower_margin = 32,
93d11f5a	525	.vsync_len = 3,
09fe75f6	526
f28ef573	527	.lcdcon5 = 0x00014b02,
09fe75f6 KH	528	},
09fe75f6 KH	529	};
58c8d570	530
09fe75f6 KH	531	/* LCD/VGA controller */
	532
	533	static struct s3c2410fb_mach_info __initdata bast_fb_info = {
	534
	535	.displays = bast_lcd_info,
	536	.num_displays = ARRAY_SIZE(bast_lcd_info),
9cbae12c	537	.default_display = 1,
58c8d570 BD	538	};
58c8d570 BD	539
042cf0f2 BD	540	/* I2C devices fitted. */
	541
	542	static struct i2c_board_info bast_i2c_devs[] __initdata = {
	543	{
	544	I2C_BOARD_INFO("tlv320aic23", 0x1a),
	545	}, {
	546	I2C_BOARD_INFO("simtec-pmu", 0x6b),
	547	}, {
	548	I2C_BOARD_INFO("ch7013", 0x75),
	549	},
	550	};
b7a12d19	551
885f9ebe BD	552	static struct s3c_hwmon_pdata bast_hwmon_info = {
	553	/* LCD contrast (0-6.6V) */
	554	.in[0] = &(struct s3c_hwmon_chcfg) {
	555	.name = "lcd-contrast",
	556	.mult = 3300,
	557	.div = 512,
	558	},
	559	/* LED current feedback */
	560	.in[1] = &(struct s3c_hwmon_chcfg) {
	561	.name = "led-feedback",
	562	.mult = 3300,
	563	.div = 1024,
	564	},
	565	/* LCD feedback (0-6.6V) */
	566	.in[2] = &(struct s3c_hwmon_chcfg) {
	567	.name = "lcd-feedback",
	568	.mult = 3300,
	569	.div = 512,
	570	},
	571	/* Vcore (1.8-2.0V), Vref 3.3V */
	572	.in[3] = &(struct s3c_hwmon_chcfg) {
	573	.name = "vcore",
	574	.mult = 3300,
	575	.div = 1024,
	576	},
	577	};
	578
1da177e4	579	/* Standard BAST devices */
885f9ebe	580	// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
1da177e4 LT	581
	582	static struct platform_device *bast_devices[] __initdata = {
	583	&s3c_device_usb,
	584	&s3c_device_lcd,
	585	&s3c_device_wdt,
3e1b776c	586	&s3c_device_i2c0,
1da177e4 LT	587	&s3c_device_rtc,
1da177e4 LT	588	&s3c_device_nand,
885f9ebe BD	589	&s3c_device_adc,
885f9ebe BD	590	&s3c_device_hwmon,
d97a666f	591	&bast_device_dm9k,
5ce4b1fe BD	592	&bast_device_asix,
5ce4b1fe BD	593	&bast_device_axpp,
65cc3370	594	&bast_sio,
1da177e4 LT	595	};
1da177e4 LT	596
2bc7509f	597	static struct clk *bast_clocks[] __initdata = {
1da177e4 LT	598	&s3c24xx_dclk0,
	599	&s3c24xx_dclk1,
	600	&s3c24xx_clkout0,
	601	&s3c24xx_clkout1,
	602	&s3c24xx_uclk,
	603	};
	604
ca0b4901 BD	605	static struct s3c_cpufreq_board __initdata bast_cpufreq = {
	606	.refresh = 7800, /* 7.8usec */
	607	.auto_io = 1,
	608	.need_io = 1,
	609	};
	610
5fe10ab1	611	static void __init bast_map_io(void)
1da177e4 LT	612	{
	613	/* initialise the clocks */
	614
d96a9804	615	s3c24xx_dclk0.parent = &clk_upll;
1da177e4 LT	616	s3c24xx_dclk0.rate = 1210001000;
1da177e4 LT	617
d96a9804	618	s3c24xx_dclk1.parent = &clk_upll;
1da177e4 LT	619	s3c24xx_dclk1.rate = 2410001000;
	620
	621	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	622	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	623
	624	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	625
ce89c206 BD	626	s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
ce89c206 BD	627
1da177e4	628	s3c_device_nand.dev.platform_data = &bast_nand_info;
885f9ebe	629	s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
3e1b776c	630
1da177e4 LT	631	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
	632	s3c24xx_init_clocks(0);
	633	s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
1da177e4 LT	634	}
1da177e4 LT	635
58c8d570 BD	636	static void __init bast_init(void)
58c8d570 BD	637	{
6ddc4b07 BD	638	sysdev_class_register(&bast_pm_sysclass);
	639	sysdev_register(&bast_pm_sysdev);
	640
a8af6de0	641	s3c_i2c0_set_platdata(&bast_i2c_info);
09fe75f6	642	s3c24xx_fb_set_platdata(&bast_fb_info);
57e5171c	643	platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
9d529c6e	644
042cf0f2 BD	645	i2c_register_board_info(0, bast_i2c_devs,
	646	ARRAY_SIZE(bast_i2c_devs));
	647
7a05a2cb	648	usb_simtec_init();
9d529c6e	649	nor_simtec_init();
ca0b4901 BD	650
ca0b4901 BD	651	s3c_cpufreq_setboard(&bast_cpufreq);
58c8d570	652	}
1da177e4 LT	653
1da177e4 LT	654	MACHINE_START(BAST, "Simtec-BAST")
e9dea0c6	655	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
e9dea0c6 RK	656	.phys_io = S3C2410_PA_UART,
	657	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	658	.boot_params = S3C2410_SDRAM_PA + 0x100,
f705b1ae BD	659	.map_io = bast_map_io,
f705b1ae BD	660	.init_irq = s3c24xx_init_irq,
58c8d570	661	.init_machine = bast_init,
1da177e4 LT	662	.timer = &s3c24xx_timer,
1da177e4 LT	663	MACHINE_END