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Merge trivial low-risk suspend hotkey bugzilla-5918 into release
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-s3c2410 / mach-osiris.c
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110d322b
BD		 1/* linux/arch/arm/mach-s3c2410/mach-osiris.c
2 *
3 * Copyright (c) 2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/device.h>
19
20#include <asm/mach/arch.h>
21#include <asm/mach/map.h>
22#include <asm/mach/irq.h>
23
24#include <asm/arch/osiris-map.h>
25#include <asm/arch/osiris-cpld.h>
26
27#include <asm/hardware.h>
28#include <asm/io.h>
29#include <asm/irq.h>
30#include <asm/mach-types.h>
31
32#include <asm/arch/regs-serial.h>
33#include <asm/arch/regs-gpio.h>
34#include <asm/arch/regs-mem.h>
35#include <asm/arch/regs-lcd.h>
36#include <asm/arch/nand.h>
37
38#include <linux/mtd/mtd.h>
39#include <linux/mtd/nand.h>
40#include <linux/mtd/nand_ecc.h>
41#include <linux/mtd/partitions.h>
42
43#include "clock.h"
44#include "devs.h"
45#include "cpu.h"
46
47/* onboard perihpheral map */
48
49static struct map_desc osiris_iodesc[] __initdata = {
50 /* ISA IO areas (may be over-written later) */
51
52 {
53 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
54 .pfn = __phys_to_pfn(S3C2410_CS5),
55 .length = SZ_16M,
56 .type = MT_DEVICE,
57 }, {
58 .virtual = (u32)S3C24XX_VA_ISA_WORD,
59 .pfn = __phys_to_pfn(S3C2410_CS5),
60 .length = SZ_16M,
61 .type = MT_DEVICE,
62 },
63
64 /* CPLD control registers */
65
66 {
67 .virtual = (u32)OSIRIS_VA_CTRL1,
68 .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
69 .length = SZ_16K,
705630db 70 .type = MT_DEVICE,
110d322b
BD		 71 }, {
72 .virtual = (u32)OSIRIS_VA_CTRL2,
73 .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
74 .length = SZ_16K,
705630db 75 .type = MT_DEVICE,
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BD		 76 },
77};
78
79#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
80#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
81#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
82
83static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
84 [0] = {
85 .name = "uclk",
86 .divisor = 1,
87 .min_baud = 0,
88 .max_baud = 0,
89 },
90 [1] = {
91 .name = "pclk",
92 .divisor = 1,
93 .min_baud = 0,
705630db 94 .max_baud = 0,
110d322b
BD		 95 }
96};
97
66a9b49a 98static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
110d322b
BD		 99 [0] = {
100 .hwport = 0,
101 .flags = 0,
102 .ucon = UCON,
103 .ulcon = ULCON,
104 .ufcon = UFCON,
105 .clocks = osiris_serial_clocks,
705630db 106 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
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BD		 107 },
108 [1] = {
e2e5810f 109 .hwport = 1,
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BD		 110 .flags = 0,
111 .ucon = UCON,
112 .ulcon = ULCON,
113 .ufcon = UFCON,
114 .clocks = osiris_serial_clocks,
705630db 115 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
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BD		 116 },
117};
118
119/* NAND Flash on Osiris board */
120
121static int external_map[] = { 2 };
122static int chip0_map[] = { 0 };
123static int chip1_map[] = { 1 };
124
da956fd6 125static struct mtd_partition osiris_default_nand_part[] = {
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BD		 126 [0] = {
127 .name = "Boot Agent",
128 .size = SZ_16K,
705630db 129 .offset = 0,
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BD		 130 },
131 [1] = {
132 .name = "/boot",
133 .size = SZ_4M - SZ_16K,
134 .offset = SZ_16K,
135 },
136 [2] = {
137 .name = "user1",
138 .offset = SZ_4M,
139 .size = SZ_32M - SZ_4M,
140 },
141 [3] = {
142 .name = "user2",
143 .offset = SZ_32M,
144 .size = MTDPART_SIZ_FULL,
145 }
146};
147
148/* the Osiris has 3 selectable slots for nand-flash, the two
149 * on-board chip areas, as well as the external slot.
150 *
151 * Note, there is no current hot-plug support for the External
152 * socket.
153*/
154
155static struct s3c2410_nand_set osiris_nand_sets[] = {
156 [1] = {
157 .name = "External",
158 .nr_chips = 1,
159 .nr_map = external_map,
160 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db 161 .partitions = osiris_default_nand_part,
110d322b
BD		 162 },
163 [0] = {
164 .name = "chip0",
165 .nr_chips = 1,
166 .nr_map = chip0_map,
167 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db 168 .partitions = osiris_default_nand_part,
110d322b
BD		 169 },
170 [2] = {
171 .name = "chip1",
172 .nr_chips = 1,
173 .nr_map = chip1_map,
174 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db 175 .partitions = osiris_default_nand_part,
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BD		 176 },
177};
178
179static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
180{
181 unsigned int tmp;
182
183 slot = set->nr_map[slot] & 3;
184
185 pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
186 slot, set, set->nr_map);
187
188 tmp = __raw_readb(OSIRIS_VA_CTRL1);
189 tmp &= ~OSIRIS_CTRL1_NANDSEL;
190 tmp |= slot;
191
192 pr_debug("osiris_nand: ctrl1 now %02x\n", tmp);
193
194 __raw_writeb(tmp, OSIRIS_VA_CTRL1);
195}
196
197static struct s3c2410_platform_nand osiris_nand_info = {
198 .tacls = 25,
199 .twrph0 = 60,
200 .twrph1 = 60,
201 .nr_sets = ARRAY_SIZE(osiris_nand_sets),
202 .sets = osiris_nand_sets,
203 .select_chip = osiris_nand_select,
204};
205
206/* PCMCIA control and configuration */
207
208static struct resource osiris_pcmcia_resource[] = {
209 [0] = {
210 .start = 0x0f000000,
211 .end = 0x0f100000,
212 .flags = IORESOURCE_MEM,
213 },
214 [1] = {
215 .start = 0x0c000000,
216 .end = 0x0c100000,
217 .flags = IORESOURCE_MEM,
218 }
219};
220
221static struct platform_device osiris_pcmcia = {
222 .name = "osiris-pcmcia",
223 .id = -1,
224 .num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
225 .resource = osiris_pcmcia_resource,
226};
227
228/* Standard Osiris devices */
229
230static struct platform_device *osiris_devices[] __initdata = {
231 &s3c_device_i2c,
232 &s3c_device_nand,
233 &osiris_pcmcia,
234};
235
236static struct clk *osiris_clocks[] = {
237 &s3c24xx_dclk0,
238 &s3c24xx_dclk1,
239 &s3c24xx_clkout0,
240 &s3c24xx_clkout1,
241 &s3c24xx_uclk,
242};
243
244static struct s3c24xx_board osiris_board __initdata = {
245 .devices = osiris_devices,
246 .devices_count = ARRAY_SIZE(osiris_devices),
247 .clocks = osiris_clocks,
705630db 248 .clocks_count = ARRAY_SIZE(osiris_clocks),
110d322b
BD		 249};
250
da956fd6 251static void __init osiris_map_io(void)
110d322b 252{
da956fd6
BD		 253 unsigned long flags;
254
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BD		 255 /* initialise the clocks */
256
257 s3c24xx_dclk0.parent = NULL;
258 s3c24xx_dclk0.rate = 12*1000*1000;
259
260 s3c24xx_dclk1.parent = NULL;
261 s3c24xx_dclk1.rate = 24*1000*1000;
262
263 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
264 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
265
266 s3c24xx_uclk.parent = &s3c24xx_clkout1;
267
268 s3c_device_nand.dev.platform_data = &osiris_nand_info;
269
270 s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
271 s3c24xx_init_clocks(0);
272 s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
273 s3c24xx_set_board(&osiris_board);
274
275 /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
da956fd6
BD		 276
277 local_irq_save(flags);
110d322b 278 __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
da956fd6 279 local_irq_restore(flags);
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BD		 280
281 /* write-protect line to the NAND */
282 s3c2410_gpio_setpin(S3C2410_GPA0, 1);
283}
284
285MACHINE_START(OSIRIS, "Simtec-OSIRIS")
286 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
110d322b
BD		 287 .phys_io = S3C2410_PA_UART,
288 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
289 .boot_params = S3C2410_SDRAM_PA + 0x100,
290 .map_io = osiris_map_io,
291 .init_irq = s3c24xx_init_irq,
292 .timer = &s3c24xx_timer,
293MACHINE_END
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