[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-s3c2410 / mach-qt2410.c

/* linux/arch/arm/mach-s3c2410/mach-qt2410.c
 *
 * Copyright (C) 2006 by OpenMoko, Inc.
 * Author: Harald Welte <laforge@openmoko.org>
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/sysdev.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_gpio.h>
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <mach/regs-gpio.h>
#include <mach/leds-gpio.h>
#include <mach/regs-lcd.h>
#include <plat/regs-serial.h>
#include <mach/fb.h>
#include <plat/nand.h>
#include <plat/udc.h>
#include <plat/iic.h>

#include <plat/common-smdk.h>
#include <plat/gpio-cfg.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pm.h>

#include "common.h"

static struct map_desc qt2410_iodesc[] __initdata = {
	{ 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
};

#define UCON S3C2410_UCON_DEFAULT
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	}
};

/* LCD driver info */

static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
	{
		/* Configuration for 640x480 SHARP LQ080V3DG01 */
		.lcdcon5 = S3C2410_LCDCON5_FRM565 |
			   S3C2410_LCDCON5_INVVLINE |
			   S3C2410_LCDCON5_INVVFRAME |
			   S3C2410_LCDCON5_PWREN |
			   S3C2410_LCDCON5_HWSWP,

		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 40000, /* HCLK/4 */
		.xres		= 640,
		.yres		= 480,
		.bpp		= 16,
		.left_margin	= 44,
		.right_margin	= 116,
		.hsync_len	= 96,
		.upper_margin	= 19,
		.lower_margin	= 11,
		.vsync_len	= 15,
	},
	{
		/* Configuration for 480x640 toppoly TD028TTEC1 */
		.lcdcon5 = S3C2410_LCDCON5_FRM565 |
			   S3C2410_LCDCON5_INVVLINE |
			   S3C2410_LCDCON5_INVVFRAME |
			   S3C2410_LCDCON5_PWREN |
			   S3C2410_LCDCON5_HWSWP,

		.type		= S3C2410_LCDCON1_TFT,
		.width		= 480,
		.height		= 640,
		.pixclock	= 40000, /* HCLK/4 */
		.xres		= 480,
		.yres		= 640,
		.bpp		= 16,
		.left_margin	= 8,
		.right_margin	= 24,
		.hsync_len	= 8,
		.upper_margin	= 2,
		.lower_margin	= 4,
		.vsync_len	= 2,
	},
	{
		/* Config for 240x320 LCD */
		.lcdcon5 = S3C2410_LCDCON5_FRM565 |
			   S3C2410_LCDCON5_INVVLINE |
			   S3C2410_LCDCON5_INVVFRAME |
			   S3C2410_LCDCON5_PWREN |
			   S3C2410_LCDCON5_HWSWP,

		.type		= S3C2410_LCDCON1_TFT,
		.width		= 240,
		.height		= 320,
		.pixclock	= 100000, /* HCLK/10 */
		.xres		= 240,
		.yres		= 320,
		.bpp		= 16,
		.left_margin	= 13,
		.right_margin	= 8,
		.hsync_len	= 4,
		.upper_margin	= 2,
		.lower_margin	= 7,
		.vsync_len	= 4,
	},
};


static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
	.displays 	= qt2410_lcd_cfg,
	.num_displays 	= ARRAY_SIZE(qt2410_lcd_cfg),
	.default_display = 0,

	.lpcsel		= ((0xCE6) & ~7) | 1<<4,
};

/* CS8900 */

static struct resource qt2410_cs89x0_resources[] = {
	[0] = {
		.start	= 0x19000000,
		.end	= 0x19000000 + 16,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_EINT9,
		.end	= IRQ_EINT9,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device qt2410_cs89x0 = {
	.name		= "cirrus-cs89x0",
	.num_resources	= ARRAY_SIZE(qt2410_cs89x0_resources),
	.resource	= qt2410_cs89x0_resources,
};

/* LED */

static struct s3c24xx_led_platdata qt2410_pdata_led = {
	.gpio		= S3C2410_GPB(0),
	.flags		= S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
	.name		= "led",
	.def_trigger	= "timer",
};

static struct platform_device qt2410_led = {
	.name		= "s3c24xx_led",
	.id		= 0,
	.dev		= {
		.platform_data = &qt2410_pdata_led,
	},
};

/* SPI */

static struct spi_gpio_platform_data spi_gpio_cfg = {
	.sck		= S3C2410_GPG(7),
	.mosi		= S3C2410_GPG(6),
	.miso		= S3C2410_GPG(5),
};

static struct platform_device qt2410_spi = {
	.name		= "spi-gpio",
	.id		= 1,
	.dev.platform_data = &spi_gpio_cfg,
};

/* Board devices */

static struct platform_device *qt2410_devices[] __initdata = {
	&s3c_device_ohci,
	&s3c_device_lcd,
	&s3c_device_wdt,
	&s3c_device_i2c0,
	&s3c_device_iis,
	&s3c_device_sdi,
	&s3c_device_usbgadget,
	&qt2410_spi,
	&qt2410_cs89x0,
	&qt2410_led,
};

static struct mtd_partition __initdata qt2410_nand_part[] = {
	[0] = {
		.name	= "U-Boot",
		.size	= 0x30000,
		.offset	= 0,
	},
	[1] = {
		.name	= "U-Boot environment",
		.offset = 0x30000,
		.size	= 0x4000,
	},
	[2] = {
		.name	= "kernel",
		.offset = 0x34000,
		.size	= SZ_2M,
	},
	[3] = {
		.name	= "initrd",
		.offset	= 0x234000,
		.size	= SZ_4M,
	},
	[4] = {
		.name	= "jffs2",
		.offset = 0x634000,
		.size	= 0x39cc000,
	},
};

static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = {
	[0] = {
		.name		= "NAND",
		.nr_chips	= 1,
		.nr_partitions	= ARRAY_SIZE(qt2410_nand_part),
		.partitions	= qt2410_nand_part,
	},
};

/* choose a set of timings which should suit most 512Mbit
 * chips and beyond.
 */

static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
	.tacls		= 20,
	.twrph0		= 60,
	.twrph1		= 20,
	.nr_sets	= ARRAY_SIZE(qt2410_nand_sets),
	.sets		= qt2410_nand_sets,
};

/* UDC */

static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
};

static char tft_type = 's';

static int __init qt2410_tft_setup(char *str)
{
	tft_type = str[0];
	return 1;
}

__setup("tft=", qt2410_tft_setup);

static void __init qt2410_map_io(void)
{
	s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
	s3c24xx_init_clocks(12*1000*1000);
	s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
}

static void __init qt2410_machine_init(void)
{
	s3c_nand_set_platdata(&qt2410_nand_info);

	switch (tft_type) {
	case 'p': /* production */
		qt2410_fb_info.default_display = 1;
		break;
	case 'b': /* big */
		qt2410_fb_info.default_display = 0;
		break;
	case 's': /* small */
	default:
		qt2410_fb_info.default_display = 2;
		break;
	}
	s3c24xx_fb_set_platdata(&qt2410_fb_info);

	s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
	s3c2410_gpio_setpin(S3C2410_GPB(0), 1);

	s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
	s3c_i2c0_set_platdata(NULL);

	WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs"));
	gpio_direction_output(S3C2410_GPB(5), 1);

	platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
	s3c_pm_init();
}

MACHINE_START(QT2410, "QT2410")
	.atag_offset	= 0x100,
	.map_io		= qt2410_map_io,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= qt2410_machine_init,
	.timer		= &s3c24xx_timer,
	.restart	= s3c2410_restart,
MACHINE_END
Commit	Line	Data
c6184e27 BD	1	/* linux/arch/arm/mach-s3c2410/mach-qt2410.c
	2	*
	3	* Copyright (C) 2006 by OpenMoko, Inc.
	4	* Author: Harald Welte <laforge@openmoko.org>
	5	* All rights reserved.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*
	22	*/
	23
	24	#include <linux/kernel.h>
	25	#include <linux/types.h>
	26	#include <linux/interrupt.h>
	27	#include <linux/list.h>
	28	#include <linux/timer.h>
	29	#include <linux/init.h>
ec976d6e	30	#include <linux/gpio.h>
333a42e1	31	#include <linux/sysdev.h>
c6184e27 BD	32	#include <linux/platform_device.h>
c6184e27 BD	33	#include <linux/serial_core.h>
c6184e27	34	#include <linux/spi/spi.h>
aa353169	35	#include <linux/spi/spi_gpio.h>
fced80c7	36	#include <linux/io.h>
c6184e27 BD	37	#include <linux/mtd/mtd.h>
	38	#include <linux/mtd/nand.h>
	39	#include <linux/mtd/nand_ecc.h>
	40	#include <linux/mtd/partitions.h>
	41
	42	#include <asm/mach/arch.h>
	43	#include <asm/mach/map.h>
	44	#include <asm/mach/irq.h>
	45
a09e64fb	46	#include <mach/hardware.h>
c6184e27 BD	47	#include <asm/irq.h>
	48	#include <asm/mach-types.h>
	49
a09e64fb RK	50	#include <mach/regs-gpio.h>
a09e64fb RK	51	#include <mach/leds-gpio.h>
61c542bf	52	#include <mach/regs-lcd.h>
a2b7ba9c	53	#include <plat/regs-serial.h>
a09e64fb	54	#include <mach/fb.h>
7926b5a3	55	#include <plat/nand.h>
57bd4b91	56	#include <plat/udc.h>
3e1b776c	57	#include <plat/iic.h>
c6184e27	58
d5120ae7	59	#include <plat/common-smdk.h>
40b956f0	60	#include <plat/gpio-cfg.h>
a2b7ba9c BD	61	#include <plat/devs.h>
	62	#include <plat/cpu.h>
	63	#include <plat/pm.h>
c6184e27	64
b27b0727 KK	65	#include "common.h"
b27b0727 KK	66
c6184e27 BD	67	static struct map_desc qt2410_iodesc[] __initdata = {
	68	{ 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
	69	};
	70
	71	#define UCON S3C2410_UCON_DEFAULT
	72	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	73	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	74
	75	static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
	76	[0] = {
	77	.hwport = 0,
	78	.flags = 0,
	79	.ucon = UCON,
	80	.ulcon = ULCON,
	81	.ufcon = UFCON,
	82	},
	83	[1] = {
	84	.hwport = 1,
	85	.flags = 0,
	86	.ucon = UCON,
	87	.ulcon = ULCON,
	88	.ufcon = UFCON,
	89	},
	90	[2] = {
	91	.hwport = 2,
	92	.flags = 0,
	93	.ucon = UCON,
	94	.ulcon = ULCON,
	95	.ufcon = UFCON,
	96	}
	97	};
	98
	99	/* LCD driver info */
	100
09fe75f6 KH	101	static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
	102	{
	103	/* Configuration for 640x480 SHARP LQ080V3DG01 */
f28ef573 KH	104	.lcdcon5 = S3C2410_LCDCON5_FRM565 \|
	105	S3C2410_LCDCON5_INVVLINE \|
	106	S3C2410_LCDCON5_INVVFRAME \|
	107	S3C2410_LCDCON5_PWREN \|
	108	S3C2410_LCDCON5_HWSWP,
09fe75f6	109
1f411537	110	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	111	.width = 640,
	112	.height = 480,
	113
69816699	114	.pixclock = 40000, /* HCLK/4 */
09fe75f6 KH	115	.xres = 640,
	116	.yres = 480,
	117	.bpp = 16,
1f411537 KH	118	.left_margin = 44,
1f411537 KH	119	.right_margin = 116,
93d11f5a	120	.hsync_len = 96,
5f20f69b KH	121	.upper_margin = 19,
5f20f69b KH	122	.lower_margin = 11,
93d11f5a	123	.vsync_len = 15,
c6184e27	124	},
09fe75f6 KH	125	{
09fe75f6 KH	126	/* Configuration for 480x640 toppoly TD028TTEC1 */
f28ef573 KH	127	.lcdcon5 = S3C2410_LCDCON5_FRM565 \|
	128	S3C2410_LCDCON5_INVVLINE \|
	129	S3C2410_LCDCON5_INVVFRAME \|
	130	S3C2410_LCDCON5_PWREN \|
	131	S3C2410_LCDCON5_HWSWP,
09fe75f6	132
1f411537	133	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	134	.width = 480,
09fe75f6 KH	135	.height = 640,
69816699	136	.pixclock = 40000, /* HCLK/4 */
09fe75f6 KH	137	.xres = 480,
	138	.yres = 640,
	139	.bpp = 16,
1f411537 KH	140	.left_margin = 8,
1f411537 KH	141	.right_margin = 24,
93d11f5a	142	.hsync_len = 8,
5f20f69b KH	143	.upper_margin = 2,
5f20f69b KH	144	.lower_margin = 4,
93d11f5a	145	.vsync_len = 2,
c6184e27	146	},
09fe75f6 KH	147	{
09fe75f6 KH	148	/* Config for 240x320 LCD */
f28ef573 KH	149	.lcdcon5 = S3C2410_LCDCON5_FRM565 \|
	150	S3C2410_LCDCON5_INVVLINE \|
	151	S3C2410_LCDCON5_INVVFRAME \|
	152	S3C2410_LCDCON5_PWREN \|
	153	S3C2410_LCDCON5_HWSWP,
09fe75f6	154
1f411537	155	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	156	.width = 240,
09fe75f6 KH	157	.height = 320,
69816699	158	.pixclock = 100000, /* HCLK/10 */
09fe75f6 KH	159	.xres = 240,
	160	.yres = 320,
	161	.bpp = 16,
1f411537 KH	162	.left_margin = 13,
1f411537 KH	163	.right_margin = 8,
93d11f5a	164	.hsync_len = 4,
5f20f69b KH	165	.upper_margin = 2,
5f20f69b KH	166	.lower_margin = 7,
93d11f5a	167	.vsync_len = 4,
c6184e27 BD	168	},
	169	};
	170
c6184e27	171
09fe75f6 KH	172	static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
	173	.displays = qt2410_lcd_cfg,
	174	.num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
	175	.default_display = 0,
c6184e27 BD	176
c6184e27 BD	177	.lpcsel = ((0xCE6) & ~7) \| 1<<4,
c6184e27 BD	178	};
	179
	180	/* CS8900 */
	181
	182	static struct resource qt2410_cs89x0_resources[] = {
	183	[0] = {
	184	.start = 0x19000000,
	185	.end = 0x19000000 + 16,
	186	.flags = IORESOURCE_MEM,
	187	},
	188	[1] = {
	189	.start = IRQ_EINT9,
	190	.end = IRQ_EINT9,
	191	.flags = IORESOURCE_IRQ,
	192	},
	193	};
	194
	195	static struct platform_device qt2410_cs89x0 = {
	196	.name = "cirrus-cs89x0",
	197	.num_resources = ARRAY_SIZE(qt2410_cs89x0_resources),
	198	.resource = qt2410_cs89x0_resources,
	199	};
	200
	201	/* LED */
	202
	203	static struct s3c24xx_led_platdata qt2410_pdata_led = {
070276d5	204	.gpio = S3C2410_GPB(0),
c6184e27 BD	205	.flags = S3C24XX_LEDF_ACTLOW \| S3C24XX_LEDF_TRISTATE,
	206	.name = "led",
	207	.def_trigger = "timer",
	208	};
	209
	210	static struct platform_device qt2410_led = {
	211	.name = "s3c24xx_led",
	212	.id = 0,
	213	.dev = {
	214	.platform_data = &qt2410_pdata_led,
	215	},
	216	};
	217
	218	/* SPI */
	219
aa353169 PK	220	static struct spi_gpio_platform_data spi_gpio_cfg = {
	221	.sck = S3C2410_GPG(7),
	222	.mosi = S3C2410_GPG(6),
	223	.miso = S3C2410_GPG(5),
c6184e27 BD	224	};
c6184e27 BD	225
c6184e27	226	static struct platform_device qt2410_spi = {
aa353169 PK	227	.name = "spi-gpio",
	228	.id = 1,
	229	.dev.platform_data = &spi_gpio_cfg,
c6184e27 BD	230	};
	231
	232	/* Board devices */
	233
	234	static struct platform_device *qt2410_devices[] __initdata = {
b813248c	235	&s3c_device_ohci,
c6184e27 BD	236	&s3c_device_lcd,
c6184e27 BD	237	&s3c_device_wdt,
3e1b776c	238	&s3c_device_i2c0,
c6184e27 BD	239	&s3c_device_iis,
	240	&s3c_device_sdi,
	241	&s3c_device_usbgadget,
	242	&qt2410_spi,
	243	&qt2410_cs89x0,
	244	&qt2410_led,
	245	};
	246
2a3a1804	247	static struct mtd_partition __initdata qt2410_nand_part[] = {
c6184e27 BD	248	[0] = {
	249	.name = "U-Boot",
	250	.size = 0x30000,
	251	.offset = 0,
	252	},
	253	[1] = {
	254	.name = "U-Boot environment",
	255	.offset = 0x30000,
	256	.size = 0x4000,
	257	},
	258	[2] = {
	259	.name = "kernel",
	260	.offset = 0x34000,
	261	.size = SZ_2M,
	262	},
	263	[3] = {
	264	.name = "initrd",
	265	.offset = 0x234000,
	266	.size = SZ_4M,
	267	},
	268	[4] = {
	269	.name = "jffs2",
	270	.offset = 0x634000,
	271	.size = 0x39cc000,
	272	},
	273	};
	274
2a3a1804	275	static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = {
c6184e27 BD	276	[0] = {
	277	.name = "NAND",
	278	.nr_chips = 1,
	279	.nr_partitions = ARRAY_SIZE(qt2410_nand_part),
	280	.partitions = qt2410_nand_part,
	281	},
	282	};
	283
	284	/* choose a set of timings which should suit most 512Mbit
	285	* chips and beyond.
	286	*/
	287
2a3a1804	288	static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
c6184e27 BD	289	.tacls = 20,
	290	.twrph0 = 60,
	291	.twrph1 = 20,
	292	.nr_sets = ARRAY_SIZE(qt2410_nand_sets),
	293	.sets = qt2410_nand_sets,
	294	};
	295
	296	/* UDC */
	297
	298	static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
	299	};
	300
	301	static char tft_type = 's';
	302
	303	static int __init qt2410_tft_setup(char *str)
	304	{
	305	tft_type = str[0];
	306	return 1;
	307	}
	308
	309	__setup("tft=", qt2410_tft_setup);
	310
	311	static void __init qt2410_map_io(void)
	312	{
	313	s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
	314	s3c24xx_init_clocks(1210001000);
	315	s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
c6184e27 BD	316	}
	317
	318	static void __init qt2410_machine_init(void)
	319	{
2a3a1804	320	s3c_nand_set_platdata(&qt2410_nand_info);
c6184e27 BD	321
	322	switch (tft_type) {
	323	case 'p': /* production */
09fe75f6	324	qt2410_fb_info.default_display = 1;
c6184e27 BD	325	break;
c6184e27 BD	326	case 'b': /* big */
09fe75f6	327	qt2410_fb_info.default_display = 0;
c6184e27 BD	328	break;
	329	case 's': /* small */
	330	default:
09fe75f6	331	qt2410_fb_info.default_display = 2;
c6184e27 BD	332	break;
c6184e27 BD	333	}
09fe75f6	334	s3c24xx_fb_set_platdata(&qt2410_fb_info);
c6184e27	335
40b956f0	336	s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
070276d5	337	s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
c6184e27 BD	338
c6184e27 BD	339	s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
3e1b776c	340	s3c_i2c0_set_platdata(NULL);
c6184e27	341
2d2e0c89 BD	342	WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs"));
2d2e0c89 BD	343	gpio_direction_output(S3C2410_GPB(5), 1);
c6184e27	344
57e5171c	345	platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
4e59c25d	346	s3c_pm_init();
c6184e27 BD	347	}
	348
	349	MACHINE_START(QT2410, "QT2410")
69d50710	350	.atag_offset = 0x100,
c6184e27 BD	351	.map_io = qt2410_map_io,
	352	.init_irq = s3c24xx_init_irq,
	353	.init_machine = qt2410_machine_init,
	354	.timer = &s3c24xx_timer,
b27b0727	355	.restart = s3c2410_restart,
c6184e27	356	MACHINE_END