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1da177e4 LT |
1 | /* linux/arch/arm/mach-s3c2410/mach-vr1000.c |
2 | * | |
3 | * Copyright (c) 2003-2005 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * Machine support for Thorcom VR1000 board. Designed for Thorcom by | |
7 | * Simtec Electronics, http://www.simtec.co.uk/ | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * Modifications: | |
14 | * 14-Sep-2004 BJD USB Power control | |
15 | * 04-Sep-2004 BJD Added new uart init, and io init | |
16 | * 21-Aug-2004 BJD Added struct s3c2410_board | |
17 | * 06-Aug-2004 BJD Fixed call to time initialisation | |
18 | * 05-Apr-2004 BJD Copied to make mach-vr1000.c | |
19 | * 18-Oct-2004 BJD Updated board struct | |
20 | * 04-Nov-2004 BJD Clock and serial configuration update | |
21 | * | |
22 | * 04-Jan-2005 BJD Updated uart init call | |
23 | * 10-Jan-2005 BJD Removed include of s3c2410.h | |
24 | * 14-Jan-2005 BJD Added clock init | |
25 | * 15-Jan-2005 BJD Add serial port device definition | |
26 | * 20-Jan-2005 BJD Use UPF_IOREMAP for ports | |
27 | * 10-Feb-2005 BJD Added power-off capability | |
28 | * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA | |
29 | * 14-Mar-2006 BJD void __iomem fixes | |
d97a666f | 30 | * 22-Jun-2006 BJD Added DM9000 platform information |
1da177e4 LT |
31 | */ |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/types.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/list.h> | |
37 | #include <linux/timer.h> | |
38 | #include <linux/init.h> | |
d97a666f | 39 | #include <linux/dm9000.h> |
1da177e4 LT |
40 | |
41 | #include <linux/serial.h> | |
42 | #include <linux/tty.h> | |
43 | #include <linux/serial_8250.h> | |
44 | #include <linux/serial_reg.h> | |
45 | ||
46 | #include <asm/mach/arch.h> | |
47 | #include <asm/mach/map.h> | |
48 | #include <asm/mach/irq.h> | |
49 | ||
50 | #include <asm/arch/bast-map.h> | |
51 | #include <asm/arch/vr1000-map.h> | |
52 | #include <asm/arch/vr1000-irq.h> | |
53 | #include <asm/arch/vr1000-cpld.h> | |
54 | ||
55 | #include <asm/hardware.h> | |
56 | #include <asm/io.h> | |
57 | #include <asm/irq.h> | |
58 | #include <asm/mach-types.h> | |
59 | ||
60 | #include <asm/arch/regs-serial.h> | |
61 | #include <asm/arch/regs-gpio.h> | |
62 | ||
63 | #include "clock.h" | |
64 | #include "devs.h" | |
65 | #include "cpu.h" | |
66 | #include "usb-simtec.h" | |
67 | ||
68 | /* macros for virtual address mods for the io space entries */ | |
69 | #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5) | |
70 | #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4) | |
71 | #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3) | |
72 | #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2) | |
73 | ||
74 | /* macros to modify the physical addresses for io space */ | |
75 | ||
76 | #define PA_CS2(item) ((item) + S3C2410_CS2) | |
77 | #define PA_CS3(item) ((item) + S3C2410_CS3) | |
78 | #define PA_CS4(item) ((item) + S3C2410_CS4) | |
79 | #define PA_CS5(item) ((item) + S3C2410_CS5) | |
80 | ||
81 | static struct map_desc vr1000_iodesc[] __initdata = { | |
82 | /* ISA IO areas */ | |
83 | ||
84 | { (u32)S3C24XX_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
85 | { (u32)S3C24XX_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
86 | ||
87 | /* we could possibly compress the next set down into a set of smaller tables | |
88 | * pagetables, but that would mean using an L2 section, and it still means | |
89 | * we cannot actually feed the same register to an LDR due to 16K spacing | |
90 | */ | |
91 | ||
92 | /* bast CPLD control registers, and external interrupt controls */ | |
93 | { (u32)VR1000_VA_CTRL1, VR1000_PA_CTRL1, SZ_1M, MT_DEVICE }, | |
94 | { (u32)VR1000_VA_CTRL2, VR1000_PA_CTRL2, SZ_1M, MT_DEVICE }, | |
95 | { (u32)VR1000_VA_CTRL3, VR1000_PA_CTRL3, SZ_1M, MT_DEVICE }, | |
96 | { (u32)VR1000_VA_CTRL4, VR1000_PA_CTRL4, SZ_1M, MT_DEVICE }, | |
97 | ||
98 | /* peripheral space... one for each of fast/slow/byte/16bit */ | |
99 | /* note, ide is only decoded in word space, even though some registers | |
100 | * are only 8bit */ | |
101 | ||
102 | /* slow, byte */ | |
1da177e4 LT |
103 | { VA_C2(VR1000_VA_IDEPRI), PA_CS3(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE }, |
104 | { VA_C2(VR1000_VA_IDESEC), PA_CS3(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE }, | |
105 | { VA_C2(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE }, | |
106 | { VA_C2(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE }, | |
107 | ||
108 | /* slow, word */ | |
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109 | { VA_C3(VR1000_VA_IDEPRI), PA_CS3(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE }, |
110 | { VA_C3(VR1000_VA_IDESEC), PA_CS3(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE }, | |
111 | { VA_C3(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE }, | |
112 | { VA_C3(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE }, | |
113 | ||
114 | /* fast, byte */ | |
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115 | { VA_C4(VR1000_VA_IDEPRI), PA_CS5(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE }, |
116 | { VA_C4(VR1000_VA_IDESEC), PA_CS5(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE }, | |
117 | { VA_C4(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE }, | |
118 | { VA_C4(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE }, | |
119 | ||
120 | /* fast, word */ | |
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121 | { VA_C5(VR1000_VA_IDEPRI), PA_CS5(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE }, |
122 | { VA_C5(VR1000_VA_IDESEC), PA_CS5(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE }, | |
123 | { VA_C5(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE }, | |
124 | { VA_C5(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE }, | |
125 | }; | |
126 | ||
127 | #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK | |
128 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | |
129 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE | |
130 | ||
131 | /* uart clock source(s) */ | |
132 | ||
133 | static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = { | |
134 | [0] = { | |
135 | .name = "uclk", | |
136 | .divisor = 1, | |
137 | .min_baud = 0, | |
138 | .max_baud = 0, | |
139 | }, | |
140 | [1] = { | |
141 | .name = "pclk", | |
142 | .divisor = 1, | |
143 | .min_baud = 0, | |
144 | .max_baud = 0. | |
145 | } | |
146 | }; | |
147 | ||
148 | static struct s3c2410_uartcfg vr1000_uartcfgs[] = { | |
149 | [0] = { | |
150 | .hwport = 0, | |
151 | .flags = 0, | |
152 | .ucon = UCON, | |
153 | .ulcon = ULCON, | |
154 | .ufcon = UFCON, | |
155 | .clocks = vr1000_serial_clocks, | |
156 | .clocks_size = ARRAY_SIZE(vr1000_serial_clocks), | |
157 | }, | |
158 | [1] = { | |
159 | .hwport = 1, | |
160 | .flags = 0, | |
161 | .ucon = UCON, | |
162 | .ulcon = ULCON, | |
163 | .ufcon = UFCON, | |
164 | .clocks = vr1000_serial_clocks, | |
165 | .clocks_size = ARRAY_SIZE(vr1000_serial_clocks), | |
166 | }, | |
167 | /* port 2 is not actually used */ | |
168 | [2] = { | |
169 | .hwport = 2, | |
170 | .flags = 0, | |
171 | .ucon = UCON, | |
172 | .ulcon = ULCON, | |
173 | .ufcon = UFCON, | |
174 | .clocks = vr1000_serial_clocks, | |
175 | .clocks_size = ARRAY_SIZE(vr1000_serial_clocks), | |
176 | ||
177 | } | |
178 | }; | |
179 | ||
180 | /* definitions for the vr1000 extra 16550 serial ports */ | |
181 | ||
182 | #define VR1000_BAUDBASE (3692307) | |
183 | ||
184 | #define VR1000_SERIAL_MAPBASE(x) (VR1000_PA_SERIAL + 0x80 + ((x) << 5)) | |
185 | ||
186 | static struct plat_serial8250_port serial_platform_data[] = { | |
187 | [0] = { | |
188 | .mapbase = VR1000_SERIAL_MAPBASE(0), | |
189 | .irq = IRQ_VR1000_SERIAL + 0, | |
190 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | |
191 | .iotype = UPIO_MEM, | |
192 | .regshift = 0, | |
193 | .uartclk = VR1000_BAUDBASE, | |
194 | }, | |
195 | [1] = { | |
196 | .mapbase = VR1000_SERIAL_MAPBASE(1), | |
197 | .irq = IRQ_VR1000_SERIAL + 1, | |
198 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | |
199 | .iotype = UPIO_MEM, | |
200 | .regshift = 0, | |
201 | .uartclk = VR1000_BAUDBASE, | |
202 | }, | |
203 | [2] = { | |
204 | .mapbase = VR1000_SERIAL_MAPBASE(2), | |
205 | .irq = IRQ_VR1000_SERIAL + 2, | |
206 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | |
207 | .iotype = UPIO_MEM, | |
208 | .regshift = 0, | |
209 | .uartclk = VR1000_BAUDBASE, | |
210 | }, | |
211 | [3] = { | |
212 | .mapbase = VR1000_SERIAL_MAPBASE(3), | |
213 | .irq = IRQ_VR1000_SERIAL + 3, | |
214 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | |
215 | .iotype = UPIO_MEM, | |
216 | .regshift = 0, | |
217 | .uartclk = VR1000_BAUDBASE, | |
218 | }, | |
219 | { }, | |
220 | }; | |
221 | ||
222 | static struct platform_device serial_device = { | |
223 | .name = "serial8250", | |
6df29deb | 224 | .id = PLAT8250_DEV_PLATFORM, |
1da177e4 LT |
225 | .dev = { |
226 | .platform_data = serial_platform_data, | |
227 | }, | |
228 | }; | |
229 | ||
230 | /* MTD NOR Flash */ | |
231 | ||
232 | static struct resource vr1000_nor_resource[] = { | |
233 | [0] = { | |
234 | .start = S3C2410_CS1 + 0x4000000, | |
235 | .end = S3C2410_CS1 + 0x4000000 + SZ_16M - 1, | |
236 | .flags = IORESOURCE_MEM, | |
237 | } | |
238 | }; | |
239 | ||
240 | static struct platform_device vr1000_nor = { | |
241 | .name = "bast-nor", | |
242 | .id = -1, | |
243 | .num_resources = ARRAY_SIZE(vr1000_nor_resource), | |
244 | .resource = vr1000_nor_resource, | |
245 | }; | |
246 | ||
d97a666f BD |
247 | /* DM9000 ethernet devices */ |
248 | ||
249 | static struct resource vr1000_dm9k0_resource[] = { | |
250 | [0] = { | |
251 | .start = S3C2410_CS5 + VR1000_PA_DM9000, | |
252 | .end = S3C2410_CS5 + VR1000_PA_DM9000 + 3, | |
253 | .flags = IORESOURCE_MEM | |
254 | }, | |
255 | [1] = { | |
256 | .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x40, | |
257 | .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0x7f, | |
258 | .flags = IORESOURCE_MEM | |
259 | }, | |
260 | [2] = { | |
261 | .start = IRQ_VR1000_DM9000A, | |
262 | .end = IRQ_VR1000_DM9000A, | |
263 | .flags = IORESOURCE_IRQ | |
264 | } | |
265 | ||
266 | }; | |
267 | ||
268 | static struct resource vr1000_dm9k1_resource[] = { | |
269 | [0] = { | |
270 | .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x80, | |
271 | .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0x83, | |
272 | .flags = IORESOURCE_MEM | |
273 | }, | |
274 | [1] = { | |
275 | .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0, | |
276 | .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0xFF, | |
277 | .flags = IORESOURCE_MEM | |
278 | }, | |
279 | [2] = { | |
280 | .start = IRQ_VR1000_DM9000N, | |
281 | .end = IRQ_VR1000_DM9000N, | |
282 | .flags = IORESOURCE_IRQ | |
283 | } | |
284 | }; | |
285 | ||
286 | /* for the moment we limit ourselves to 16bit IO until some | |
287 | * better IO routines can be written and tested | |
288 | */ | |
289 | ||
290 | struct dm9000_plat_data vr1000_dm9k_platdata = { | |
291 | .flags = DM9000_PLATF_16BITONLY, | |
292 | }; | |
293 | ||
294 | static struct platform_device vr1000_dm9k0 = { | |
295 | .name = "dm9000", | |
296 | .id = 0, | |
297 | .num_resources = ARRAY_SIZE(vr1000_dm9k0_resource), | |
298 | .resource = vr1000_dm9k0_resource, | |
299 | .dev = { | |
300 | .platform_data = &vr1000_dm9k_platdata, | |
301 | } | |
302 | }; | |
303 | ||
304 | static struct platform_device vr1000_dm9k1 = { | |
305 | .name = "dm9000", | |
306 | .id = 1, | |
307 | .num_resources = ARRAY_SIZE(vr1000_dm9k1_resource), | |
308 | .resource = vr1000_dm9k1_resource, | |
309 | .dev = { | |
310 | .platform_data = &vr1000_dm9k_platdata, | |
311 | } | |
312 | }; | |
313 | ||
314 | /* devices for this board */ | |
1da177e4 LT |
315 | |
316 | static struct platform_device *vr1000_devices[] __initdata = { | |
317 | &s3c_device_usb, | |
318 | &s3c_device_lcd, | |
319 | &s3c_device_wdt, | |
320 | &s3c_device_i2c, | |
321 | &s3c_device_iis, | |
d97a666f | 322 | &s3c_device_adc, |
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323 | &serial_device, |
324 | &vr1000_nor, | |
d97a666f BD |
325 | &vr1000_dm9k0, |
326 | &vr1000_dm9k1 | |
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327 | }; |
328 | ||
329 | static struct clk *vr1000_clocks[] = { | |
330 | &s3c24xx_dclk0, | |
331 | &s3c24xx_dclk1, | |
332 | &s3c24xx_clkout0, | |
333 | &s3c24xx_clkout1, | |
334 | &s3c24xx_uclk, | |
335 | }; | |
336 | ||
337 | static struct s3c24xx_board vr1000_board __initdata = { | |
338 | .devices = vr1000_devices, | |
339 | .devices_count = ARRAY_SIZE(vr1000_devices), | |
340 | .clocks = vr1000_clocks, | |
341 | .clocks_count = ARRAY_SIZE(vr1000_clocks), | |
342 | }; | |
343 | ||
344 | static void vr1000_power_off(void) | |
345 | { | |
346 | s3c2410_gpio_cfgpin(S3C2410_GPB9, S3C2410_GPB9_OUTP); | |
347 | s3c2410_gpio_setpin(S3C2410_GPB9, 1); | |
348 | } | |
349 | ||
350 | void __init vr1000_map_io(void) | |
351 | { | |
352 | /* initialise clock sources */ | |
353 | ||
354 | s3c24xx_dclk0.parent = NULL; | |
355 | s3c24xx_dclk0.rate = 12*1000*1000; | |
356 | ||
357 | s3c24xx_dclk1.parent = NULL; | |
358 | s3c24xx_dclk1.rate = 3692307; | |
359 | ||
360 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; | |
361 | s3c24xx_clkout1.parent = &s3c24xx_dclk1; | |
362 | ||
363 | s3c24xx_uclk.parent = &s3c24xx_clkout1; | |
364 | ||
365 | pm_power_off = vr1000_power_off; | |
366 | ||
367 | s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc)); | |
368 | s3c24xx_init_clocks(0); | |
369 | s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs)); | |
370 | s3c24xx_set_board(&vr1000_board); | |
371 | usb_simtec_init(); | |
372 | } | |
373 | ||
1da177e4 LT |
374 | |
375 | MACHINE_START(VR1000, "Thorcom-VR1000") | |
e9dea0c6 RK |
376 | /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ |
377 | .phys_ram = S3C2410_SDRAM_PA, | |
378 | .phys_io = S3C2410_PA_UART, | |
379 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | |
380 | .boot_params = S3C2410_SDRAM_PA + 0x100, | |
6904b246 BD |
381 | .map_io = vr1000_map_io, |
382 | .init_irq = s3c24xx_init_irq, | |
1da177e4 LT |
383 | .timer = &s3c24xx_timer, |
384 | MACHINE_END |