[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-s3c2440 / mach-osiris.c

/* linux/arch/arm/mach-s3c2440/mach-osiris.c
 *
 * Copyright (c) 2005-2008 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/io.h>

#include <linux/i2c/tps65010.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/osiris-map.h>
#include <mach/osiris-cpld.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <plat/gpio-cfg.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>

/* onboard perihperal map */

static struct map_desc osiris_iodesc[] __initdata = {
  /* ISA IO areas (may be over-written later) */

  {
	  .virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	  .pfn		= __phys_to_pfn(S3C2410_CS5),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)S3C24XX_VA_ISA_WORD,
	  .pfn		= __phys_to_pfn(S3C2410_CS5),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  },

  /* CPLD control registers */

  {
	  .virtual	= (u32)OSIRIS_VA_CTRL0,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL0),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_CTRL1,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL1),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_CTRL2,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL2),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_IDREG,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_IDREG),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
	[0] = {
		.name		= "uclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	},
	[1] = {
		.name		= "pclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};

static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = osiris_serial_clocks,
		.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = osiris_serial_clocks,
		.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	},
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = osiris_serial_clocks,
		.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	}
};

/* NAND Flash on Osiris board */

static int external_map[]   = { 2 };
static int chip0_map[]      = { 0 };
static int chip1_map[]      = { 1 };

static struct mtd_partition __initdata osiris_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_128K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_128K,
		.offset	= SZ_128K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the Osiris has 3 selectable slots for nand-flash, the two
 * on-board chip areas, as well as the external slot.
 *
 * Note, there is no current hot-plug support for the External
 * socket.
*/

static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
	[1] = {
		.name		= "External",
		.nr_chips	= 1,
		.nr_map		= external_map,
		.options	= NAND_SCAN_SILENT_NODEV,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
	[0] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.options	= NAND_SCAN_SILENT_NODEV,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
};

static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(OSIRIS_VA_CTRL0);
	tmp &= ~OSIRIS_CTRL0_NANDSEL;
	tmp |= slot;

	pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);

	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
}

static struct s3c2410_platform_nand __initdata osiris_nand_info = {
	.tacls		= 25,
	.twrph0		= 60,
	.twrph1		= 60,
	.nr_sets	= ARRAY_SIZE(osiris_nand_sets),
	.sets		= osiris_nand_sets,
	.select_chip	= osiris_nand_select,
};

/* PCMCIA control and configuration */

static struct resource osiris_pcmcia_resource[] = {
	[0] = {
		.start	= 0x0f000000,
		.end	= 0x0f100000,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 0x0c000000,
		.end	= 0x0c100000,
		.flags	= IORESOURCE_MEM,
	}
};

static struct platform_device osiris_pcmcia = {
	.name		= "osiris-pcmcia",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(osiris_pcmcia_resource),
	.resource	= osiris_pcmcia_resource,
};

/* Osiris power management device */

#ifdef CONFIG_PM
static unsigned char pm_osiris_ctrl0;

static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
{
	unsigned int tmp;

	pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
	tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;

	/* ensure correct NAND slot is selected on resume */
	if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
	        tmp |= 2;

	__raw_writeb(tmp, OSIRIS_VA_CTRL0);

	/* ensure that an nRESET is not generated on resume. */
	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);

	return 0;
}

static int osiris_pm_resume(struct sys_device *sd)
{
	if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
		__raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);

	__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);

	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);

	return 0;
}

#else
#define osiris_pm_suspend NULL
#define osiris_pm_resume NULL
#endif

static struct sysdev_class osiris_pm_sysclass = {
	.name		= "mach-osiris",
	.suspend	= osiris_pm_suspend,
	.resume		= osiris_pm_resume,
};

static struct sys_device osiris_pm_sysdev = {
	.cls		= &osiris_pm_sysclass,
};

/* Link for DVS driver to TPS65011 */

static void osiris_tps_release(struct device *dev)
{
	/* static device, do not need to release anything */
}

static struct platform_device osiris_tps_device = {
	.name	= "osiris-dvs",
	.id	= -1,
	.dev.release = osiris_tps_release,
};

static int osiris_tps_setup(struct i2c_client *client, void *context)
{
	osiris_tps_device.dev.parent = &client->dev;
	return platform_device_register(&osiris_tps_device);
}

static int osiris_tps_remove(struct i2c_client *client, void *context)
{
	platform_device_unregister(&osiris_tps_device);
	return 0;
}

static struct tps65010_board osiris_tps_board = {
	.base		= -1,	/* GPIO can go anywhere at the moment */
	.setup		= osiris_tps_setup,
	.teardown	= osiris_tps_remove,
};

/* I2C devices fitted. */

static struct i2c_board_info osiris_i2c_devs[] __initdata = {
	{
		I2C_BOARD_INFO("tps65011", 0x48),
		.irq	= IRQ_EINT20,
		.platform_data = &osiris_tps_board,
	},
};

/* Standard Osiris devices */

static struct platform_device *osiris_devices[] __initdata = {
	&s3c_device_i2c0,
	&s3c_device_wdt,
	&s3c_device_nand,
	&osiris_pcmcia,
};

static struct clk *osiris_clocks[] __initdata = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
	.refresh	= 7800, /* refresh period is 7.8usec */
	.auto_io	= 1,
	.need_io	= 1,
};

static void __init osiris_map_io(void)
{
	unsigned long flags;

	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));

	s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));

	/* check for the newer revision boards with large page nand */

	if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
		printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
		       __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
		osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
		osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
	} else {
		/* write-protect line to the NAND */
		s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
	}

	/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */

	local_irq_save(flags);
	__raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
	local_irq_restore(flags);
}

static void __init osiris_init(void)
{
	sysdev_class_register(&osiris_pm_sysclass);
	sysdev_register(&osiris_pm_sysdev);

	s3c_i2c0_set_platdata(NULL);
	s3c_nand_set_platdata(&osiris_nand_info);

	s3c_cpufreq_setboard(&osiris_cpufreq);

	i2c_register_board_info(0, osiris_i2c_devs,
				ARRAY_SIZE(osiris_i2c_devs));

	platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
};

MACHINE_START(OSIRIS, "Simtec-OSIRIS")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= osiris_map_io,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= osiris_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/mach-osiris.c
110d322b	2	*
ccae941e	3	* Copyright (c) 2005-2008 Simtec Electronics
110d322b BD	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/list.h>
	16	#include <linux/timer.h>
	17	#include <linux/init.h>
ec976d6e	18	#include <linux/gpio.h>
110d322b	19	#include <linux/device.h>
5698bd28	20	#include <linux/sysdev.h>
b6d1f542	21	#include <linux/serial_core.h>
d96a9804	22	#include <linux/clk.h>
f3374221	23	#include <linux/i2c.h>
fced80c7	24	#include <linux/io.h>
110d322b	25
4fa084af BD	26	#include <linux/i2c/tps65010.h>
4fa084af BD	27
110d322b BD	28	#include <asm/mach/arch.h>
	29	#include <asm/mach/map.h>
	30	#include <asm/mach/irq.h>
	31
a09e64fb RK	32	#include <mach/osiris-map.h>
a09e64fb RK	33	#include <mach/osiris-cpld.h>
110d322b	34
a09e64fb	35	#include <mach/hardware.h>
110d322b BD	36	#include <asm/irq.h>
	37	#include <asm/mach-types.h>
	38
baf6b281	39	#include <plat/cpu-freq.h>
a2b7ba9c	40	#include <plat/regs-serial.h>
a09e64fb RK	41	#include <mach/regs-gpio.h>
	42	#include <mach/regs-mem.h>
	43	#include <mach/regs-lcd.h>
7926b5a3	44	#include <plat/nand.h>
3e1b776c	45	#include <plat/iic.h>
110d322b BD	46
	47	#include <linux/mtd/mtd.h>
	48	#include <linux/mtd/nand.h>
	49	#include <linux/mtd/nand_ecc.h>
	50	#include <linux/mtd/partitions.h>
	51
40b956f0	52	#include <plat/gpio-cfg.h>
d5120ae7	53	#include <plat/clock.h>
a2b7ba9c BD	54	#include <plat/devs.h>
a2b7ba9c BD	55	#include <plat/cpu.h>
110d322b	56
6cbdc8c5	57	/* onboard perihperal map */
110d322b BD	58
	59	static struct map_desc osiris_iodesc[] __initdata = {
	60	/* ISA IO areas (may be over-written later) */
	61
	62	{
	63	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	64	.pfn = __phys_to_pfn(S3C2410_CS5),
	65	.length = SZ_16M,
	66	.type = MT_DEVICE,
	67	}, {
	68	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	69	.pfn = __phys_to_pfn(S3C2410_CS5),
	70	.length = SZ_16M,
	71	.type = MT_DEVICE,
	72	},
	73
	74	/* CPLD control registers */
	75
	76	{
c362aecd BD	77	.virtual = (u32)OSIRIS_VA_CTRL0,
	78	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL0),
	79	.length = SZ_16K,
	80	.type = MT_DEVICE,
	81	}, {
110d322b BD	82	.virtual = (u32)OSIRIS_VA_CTRL1,
	83	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
	84	.length = SZ_16K,
705630db	85	.type = MT_DEVICE,
110d322b BD	86	}, {
	87	.virtual = (u32)OSIRIS_VA_CTRL2,
	88	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
	89	.length = SZ_16K,
705630db	90	.type = MT_DEVICE,
c362aecd BD	91	}, {
	92	.virtual = (u32)OSIRIS_VA_IDREG,
	93	.pfn = __phys_to_pfn(OSIRIS_PA_IDREG),
	94	.length = SZ_16K,
	95	.type = MT_DEVICE,
110d322b BD	96	},
	97	};
	98
	99	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	100	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	101	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	102
	103	static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
	104	[0] = {
	105	.name = "uclk",
	106	.divisor = 1,
	107	.min_baud = 0,
	108	.max_baud = 0,
	109	},
	110	[1] = {
	111	.name = "pclk",
	112	.divisor = 1,
	113	.min_baud = 0,
705630db	114	.max_baud = 0,
110d322b BD	115	}
	116	};
	117
66a9b49a	118	static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
110d322b BD	119	[0] = {
	120	.hwport = 0,
	121	.flags = 0,
	122	.ucon = UCON,
	123	.ulcon = ULCON,
	124	.ufcon = UFCON,
	125	.clocks = osiris_serial_clocks,
705630db	126	.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
110d322b BD	127	},
110d322b BD	128	[1] = {
e2e5810f	129	.hwport = 1,
110d322b BD	130	.flags = 0,
	131	.ucon = UCON,
	132	.ulcon = ULCON,
	133	.ufcon = UFCON,
	134	.clocks = osiris_serial_clocks,
705630db	135	.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
110d322b	136	},
ca7aa4de BD	137	[2] = {
	138	.hwport = 2,
	139	.flags = 0,
	140	.ucon = UCON,
	141	.ulcon = ULCON,
	142	.ufcon = UFCON,
	143	.clocks = osiris_serial_clocks,
	144	.clocks_size = ARRAY_SIZE(osiris_serial_clocks),
	145	}
110d322b BD	146	};
	147
	148	/* NAND Flash on Osiris board */
	149
	150	static int external_map[] = { 2 };
	151	static int chip0_map[] = { 0 };
	152	static int chip1_map[] = { 1 };
	153
2a3a1804	154	static struct mtd_partition __initdata osiris_default_nand_part[] = {
110d322b BD	155	[0] = {
	156	.name = "Boot Agent",
	157	.size = SZ_16K,
705630db	158	.offset = 0,
110d322b BD	159	},
	160	[1] = {
	161	.name = "/boot",
	162	.size = SZ_4M - SZ_16K,
	163	.offset = SZ_16K,
	164	},
	165	[2] = {
	166	.name = "user1",
	167	.offset = SZ_4M,
	168	.size = SZ_32M - SZ_4M,
	169	},
	170	[3] = {
	171	.name = "user2",
	172	.offset = SZ_32M,
	173	.size = MTDPART_SIZ_FULL,
	174	}
	175	};
	176
2a3a1804	177	static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
3c3e69cd BD	178	[0] = {
	179	.name = "Boot Agent",
	180	.size = SZ_128K,
	181	.offset = 0,
	182	},
	183	[1] = {
	184	.name = "/boot",
	185	.size = SZ_4M - SZ_128K,
	186	.offset = SZ_128K,
	187	},
	188	[2] = {
	189	.name = "user1",
	190	.offset = SZ_4M,
	191	.size = SZ_32M - SZ_4M,
	192	},
	193	[3] = {
	194	.name = "user2",
	195	.offset = SZ_32M,
	196	.size = MTDPART_SIZ_FULL,
	197	}
	198	};
	199
110d322b BD	200	/* the Osiris has 3 selectable slots for nand-flash, the two
	201	* on-board chip areas, as well as the external slot.
	202	*
	203	* Note, there is no current hot-plug support for the External
	204	* socket.
	205	*/
	206
2a3a1804	207	static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
110d322b BD	208	[1] = {
	209	.name = "External",
	210	.nr_chips = 1,
	211	.nr_map = external_map,
d9237380	212	.options = NAND_SCAN_SILENT_NODEV,
110d322b	213	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	214	.partitions = osiris_default_nand_part,
110d322b BD	215	},
	216	[0] = {
	217	.name = "chip0",
	218	.nr_chips = 1,
	219	.nr_map = chip0_map,
	220	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	221	.partitions = osiris_default_nand_part,
110d322b BD	222	},
	223	[2] = {
	224	.name = "chip1",
	225	.nr_chips = 1,
	226	.nr_map = chip1_map,
d9237380	227	.options = NAND_SCAN_SILENT_NODEV,
110d322b	228	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	229	.partitions = osiris_default_nand_part,
110d322b BD	230	},
	231	};
	232
	233	static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
	234	{
	235	unsigned int tmp;
	236
	237	slot = set->nr_map[slot] & 3;
	238
	239	pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
	240	slot, set, set->nr_map);
	241
c362aecd BD	242	tmp = __raw_readb(OSIRIS_VA_CTRL0);
c362aecd BD	243	tmp &= ~OSIRIS_CTRL0_NANDSEL;
110d322b BD	244	tmp \|= slot;
110d322b BD	245
c362aecd	246	pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
110d322b	247
c362aecd	248	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
110d322b BD	249	}
110d322b BD	250
2a3a1804	251	static struct s3c2410_platform_nand __initdata osiris_nand_info = {
110d322b BD	252	.tacls = 25,
	253	.twrph0 = 60,
	254	.twrph1 = 60,
	255	.nr_sets = ARRAY_SIZE(osiris_nand_sets),
	256	.sets = osiris_nand_sets,
	257	.select_chip = osiris_nand_select,
	258	};
	259
	260	/* PCMCIA control and configuration */
	261
	262	static struct resource osiris_pcmcia_resource[] = {
	263	[0] = {
	264	.start = 0x0f000000,
	265	.end = 0x0f100000,
	266	.flags = IORESOURCE_MEM,
	267	},
	268	[1] = {
	269	.start = 0x0c000000,
	270	.end = 0x0c100000,
	271	.flags = IORESOURCE_MEM,
	272	}
	273	};
	274
	275	static struct platform_device osiris_pcmcia = {
	276	.name = "osiris-pcmcia",
	277	.id = -1,
	278	.num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
	279	.resource = osiris_pcmcia_resource,
	280	};
	281
5698bd28 BD	282	/* Osiris power management device */
	283
	284	#ifdef CONFIG_PM
	285	static unsigned char pm_osiris_ctrl0;
	286
	287	static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
	288	{
28047ece BD	289	unsigned int tmp;
28047ece BD	290
5698bd28	291	pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
28047ece BD	292	tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
	293
	294	/* ensure correct NAND slot is selected on resume */
	295	if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
	296	tmp \|= 2;
	297
	298	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
	299
4afcddae	300	/* ensure that an nRESET is not generated on resume. */
070276d5	301	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
40b956f0	302	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
4afcddae	303
5698bd28 BD	304	return 0;
	305	}
	306
	307	static int osiris_pm_resume(struct sys_device *sd)
	308	{
	309	if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
	310	__raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
	311
28047ece BD	312	__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
28047ece BD	313
40b956f0	314	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
4afcddae	315
5698bd28 BD	316	return 0;
	317	}
	318
	319	#else
	320	#define osiris_pm_suspend NULL
	321	#define osiris_pm_resume NULL
	322	#endif
	323
	324	static struct sysdev_class osiris_pm_sysclass = {
af5ca3f4	325	.name = "mach-osiris",
5698bd28 BD	326	.suspend = osiris_pm_suspend,
	327	.resume = osiris_pm_resume,
	328	};
	329
	330	static struct sys_device osiris_pm_sysdev = {
	331	.cls = &osiris_pm_sysclass,
	332	};
	333
4fa084af BD	334	/* Link for DVS driver to TPS65011 */
	335
	336	static void osiris_tps_release(struct device *dev)
	337	{
	338	/* static device, do not need to release anything */
	339	}
	340
	341	static struct platform_device osiris_tps_device = {
	342	.name = "osiris-dvs",
	343	.id = -1,
	344	.dev.release = osiris_tps_release,
	345	};
	346
	347	static int osiris_tps_setup(struct i2c_client client, void context)
	348	{
	349	osiris_tps_device.dev.parent = &client->dev;
	350	return platform_device_register(&osiris_tps_device);
	351	}
	352
	353	static int osiris_tps_remove(struct i2c_client client, void context)
	354	{
	355	platform_device_unregister(&osiris_tps_device);
	356	return 0;
	357	}
	358
	359	static struct tps65010_board osiris_tps_board = {
	360	.base = -1, /* GPIO can go anywhere at the moment */
	361	.setup = osiris_tps_setup,
	362	.teardown = osiris_tps_remove,
	363	};
	364
f3374221 BD	365	/* I2C devices fitted. */
	366
	367	static struct i2c_board_info osiris_i2c_devs[] __initdata = {
	368	{
	369	I2C_BOARD_INFO("tps65011", 0x48),
	370	.irq = IRQ_EINT20,
4fa084af	371	.platform_data = &osiris_tps_board,
f3374221 BD	372	},
	373	};
	374
110d322b BD	375	/* Standard Osiris devices */
	376
	377	static struct platform_device *osiris_devices[] __initdata = {
3e1b776c	378	&s3c_device_i2c0,
55ba86bc	379	&s3c_device_wdt,
110d322b BD	380	&s3c_device_nand,
	381	&osiris_pcmcia,
	382	};
	383
2bc7509f	384	static struct clk *osiris_clocks[] __initdata = {
110d322b BD	385	&s3c24xx_dclk0,
	386	&s3c24xx_dclk1,
	387	&s3c24xx_clkout0,
	388	&s3c24xx_clkout1,
	389	&s3c24xx_uclk,
	390	};
	391
baf6b281 BD	392	static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
	393	.refresh = 7800, /* refresh period is 7.8usec */
	394	.auto_io = 1,
	395	.need_io = 1,
	396	};
	397
da956fd6	398	static void __init osiris_map_io(void)
110d322b	399	{
da956fd6 BD	400	unsigned long flags;
da956fd6 BD	401
110d322b BD	402	/* initialise the clocks */
110d322b BD	403
d96a9804	404	s3c24xx_dclk0.parent = &clk_upll;
110d322b BD	405	s3c24xx_dclk0.rate = 1210001000;
110d322b BD	406
d96a9804	407	s3c24xx_dclk1.parent = &clk_upll;
110d322b BD	408	s3c24xx_dclk1.rate = 2410001000;
	409
	410	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	411	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	412
	413	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	414
ce89c206 BD	415	s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
ce89c206 BD	416
110d322b BD	417	s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
	418	s3c24xx_init_clocks(0);
	419	s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
110d322b	420
3c3e69cd BD	421	/* check for the newer revision boards with large page nand */
	422
	423	if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
	424	printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
	425	__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
	426	osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
	427	osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
	428	} else {
	429	/* write-protect line to the NAND */
070276d5	430	s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
3c3e69cd BD	431	}
3c3e69cd BD	432
110d322b	433	/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
da956fd6 BD	434
da956fd6 BD	435	local_irq_save(flags);
110d322b	436	__raw_writel(__raw_readl(S3C2410_BWSCON) \| S3C2410_BWSCON_ST1 \| S3C2410_BWSCON_ST2 \| S3C2410_BWSCON_ST3 \| S3C2410_BWSCON_ST4 \| S3C2410_BWSCON_ST5, S3C2410_BWSCON);
da956fd6	437	local_irq_restore(flags);
110d322b BD	438	}
110d322b BD	439
57e5171c BD	440	static void __init osiris_init(void)
57e5171c BD	441	{
5698bd28 BD	442	sysdev_class_register(&osiris_pm_sysclass);
	443	sysdev_register(&osiris_pm_sysdev);
	444
3e1b776c	445	s3c_i2c0_set_platdata(NULL);
2a3a1804	446	s3c_nand_set_platdata(&osiris_nand_info);
3e1b776c	447
baf6b281 BD	448	s3c_cpufreq_setboard(&osiris_cpufreq);
baf6b281 BD	449
f3374221 BD	450	i2c_register_board_info(0, osiris_i2c_devs,
	451	ARRAY_SIZE(osiris_i2c_devs));
	452
57e5171c BD	453	platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
	454	};
	455
110d322b BD	456	MACHINE_START(OSIRIS, "Simtec-OSIRIS")
110d322b BD	457	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
110d322b BD	458	.phys_io = S3C2410_PA_UART,
	459	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	460	.boot_params = S3C2410_SDRAM_PA + 0x100,
	461	.map_io = osiris_map_io,
	462	.init_irq = s3c24xx_init_irq,
5698bd28	463	.init_machine = osiris_init,
110d322b BD	464	.timer = &s3c24xx_timer,
110d322b BD	465	MACHINE_END