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a21765a7 | 1 | /* linux/arch/arm/mach-s3c2440/mach-rx3715.c |
1da177e4 LT |
2 | * |
3 | * Copyright (c) 2003,2004 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * http://www.handhelds.org/projects/rx3715.html | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
1da177e4 LT |
12 | */ |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/timer.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/tty.h> | |
21 | #include <linux/console.h> | |
333a42e1 | 22 | #include <linux/sysdev.h> |
d052d1be | 23 | #include <linux/platform_device.h> |
1da177e4 LT |
24 | #include <linux/serial_core.h> |
25 | #include <linux/serial.h> | |
26 | ||
272eb575 BD |
27 | #include <linux/mtd/mtd.h> |
28 | #include <linux/mtd/nand.h> | |
29 | #include <linux/mtd/nand_ecc.h> | |
30 | #include <linux/mtd/partitions.h> | |
31 | ||
1da177e4 LT |
32 | #include <asm/mach/arch.h> |
33 | #include <asm/mach/map.h> | |
34 | #include <asm/mach/irq.h> | |
35 | ||
a09e64fb | 36 | #include <mach/hardware.h> |
1da177e4 LT |
37 | #include <asm/io.h> |
38 | #include <asm/irq.h> | |
39 | #include <asm/mach-types.h> | |
40 | ||
531b617c | 41 | #include <asm/plat-s3c/regs-serial.h> |
a09e64fb RK |
42 | #include <mach/regs-gpio.h> |
43 | #include <mach/regs-lcd.h> | |
e838ffc2 | 44 | |
a09e64fb | 45 | #include <mach/h1940.h> |
531b617c | 46 | #include <asm/plat-s3c/nand.h> |
a09e64fb | 47 | #include <mach/fb.h> |
1da177e4 | 48 | |
a21765a7 BD |
49 | #include <asm/plat-s3c24xx/clock.h> |
50 | #include <asm/plat-s3c24xx/devs.h> | |
51 | #include <asm/plat-s3c24xx/cpu.h> | |
52 | #include <asm/plat-s3c24xx/pm.h> | |
1da177e4 LT |
53 | |
54 | static struct map_desc rx3715_iodesc[] __initdata = { | |
55 | /* dump ISA space somewhere unused */ | |
56 | ||
ff6ffa82 BD |
57 | { |
58 | .virtual = (u32)S3C24XX_VA_ISA_WORD, | |
59 | .pfn = __phys_to_pfn(S3C2410_CS3), | |
60 | .length = SZ_1M, | |
61 | .type = MT_DEVICE, | |
62 | }, { | |
63 | .virtual = (u32)S3C24XX_VA_ISA_BYTE, | |
64 | .pfn = __phys_to_pfn(S3C2410_CS3), | |
65 | .length = SZ_1M, | |
66 | .type = MT_DEVICE, | |
67 | }, | |
1da177e4 LT |
68 | }; |
69 | ||
70 | ||
71 | static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = { | |
72 | [0] = { | |
73 | .name = "fclk", | |
74 | .divisor = 0, | |
75 | .min_baud = 0, | |
76 | .max_baud = 0, | |
77 | } | |
78 | }; | |
79 | ||
80 | static struct s3c2410_uartcfg rx3715_uartcfgs[] = { | |
81 | [0] = { | |
82 | .hwport = 0, | |
83 | .flags = 0, | |
84 | .ucon = 0x3c5, | |
85 | .ulcon = 0x03, | |
86 | .ufcon = 0x51, | |
87 | .clocks = rx3715_serial_clocks, | |
88 | .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), | |
89 | }, | |
90 | [1] = { | |
91 | .hwport = 1, | |
92 | .flags = 0, | |
93 | .ucon = 0x3c5, | |
94 | .ulcon = 0x03, | |
95 | .ufcon = 0x00, | |
96 | .clocks = rx3715_serial_clocks, | |
97 | .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), | |
98 | }, | |
99 | /* IR port */ | |
100 | [2] = { | |
101 | .hwport = 2, | |
102 | .uart_flags = UPF_CONS_FLOW, | |
103 | .ucon = 0x3c5, | |
104 | .ulcon = 0x43, | |
105 | .ufcon = 0x51, | |
106 | .clocks = rx3715_serial_clocks, | |
107 | .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), | |
108 | } | |
109 | }; | |
110 | ||
e838ffc2 BD |
111 | /* framebuffer lcd controller information */ |
112 | ||
09fe75f6 | 113 | static struct s3c2410fb_display rx3715_lcdcfg __initdata = { |
f28ef573 KH |
114 | .lcdcon5 = S3C2410_LCDCON5_INVVLINE | |
115 | S3C2410_LCDCON5_FRM565 | | |
116 | S3C2410_LCDCON5_HWSWP, | |
e838ffc2 | 117 | |
1f411537 KH |
118 | .type = S3C2410_LCDCON1_TFT, |
119 | .width = 240, | |
120 | .height = 320, | |
121 | ||
69816699 | 122 | .pixclock = 260000, |
1f411537 KH |
123 | .xres = 240, |
124 | .yres = 320, | |
125 | .bpp = 16, | |
126 | .left_margin = 36, | |
127 | .right_margin = 36, | |
93d11f5a | 128 | .hsync_len = 8, |
5f20f69b KH |
129 | .upper_margin = 6, |
130 | .lower_margin = 7, | |
93d11f5a | 131 | .vsync_len = 3, |
09fe75f6 KH |
132 | }; |
133 | ||
134 | static struct s3c2410fb_mach_info rx3715_fb_info __initdata = { | |
135 | ||
136 | .displays = &rx3715_lcdcfg, | |
137 | .num_displays = 1, | |
138 | .default_display = 0, | |
139 | ||
e838ffc2 BD |
140 | .lpcsel = 0xf82, |
141 | ||
142 | .gpccon = 0xaa955699, | |
143 | .gpccon_mask = 0xffc003cc, | |
144 | .gpcup = 0x0000ffff, | |
145 | .gpcup_mask = 0xffffffff, | |
146 | ||
147 | .gpdcon = 0xaa95aaa1, | |
148 | .gpdcon_mask = 0xffc0fff0, | |
149 | .gpdup = 0x0000faff, | |
150 | .gpdup_mask = 0xffffffff, | |
e838ffc2 BD |
151 | }; |
152 | ||
272eb575 BD |
153 | static struct mtd_partition rx3715_nand_part[] = { |
154 | [0] = { | |
155 | .name = "Whole Flash", | |
156 | .offset = 0, | |
157 | .size = MTDPART_SIZ_FULL, | |
158 | .mask_flags = MTD_WRITEABLE, | |
159 | } | |
160 | }; | |
161 | ||
162 | static struct s3c2410_nand_set rx3715_nand_sets[] = { | |
163 | [0] = { | |
164 | .name = "Internal", | |
165 | .nr_chips = 1, | |
166 | .nr_partitions = ARRAY_SIZE(rx3715_nand_part), | |
167 | .partitions = rx3715_nand_part, | |
168 | }, | |
169 | }; | |
170 | ||
171 | static struct s3c2410_platform_nand rx3715_nand_info = { | |
172 | .tacls = 25, | |
173 | .twrph0 = 50, | |
174 | .twrph1 = 15, | |
175 | .nr_sets = ARRAY_SIZE(rx3715_nand_sets), | |
176 | .sets = rx3715_nand_sets, | |
177 | }; | |
178 | ||
1da177e4 LT |
179 | static struct platform_device *rx3715_devices[] __initdata = { |
180 | &s3c_device_usb, | |
181 | &s3c_device_lcd, | |
182 | &s3c_device_wdt, | |
183 | &s3c_device_i2c, | |
184 | &s3c_device_iis, | |
272eb575 | 185 | &s3c_device_nand, |
1da177e4 LT |
186 | }; |
187 | ||
5fe10ab1 | 188 | static void __init rx3715_map_io(void) |
1da177e4 | 189 | { |
272eb575 BD |
190 | s3c_device_nand.dev.platform_data = &rx3715_nand_info; |
191 | ||
1da177e4 LT |
192 | s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); |
193 | s3c24xx_init_clocks(16934000); | |
194 | s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); | |
1da177e4 LT |
195 | } |
196 | ||
5fe10ab1 | 197 | static void __init rx3715_init_irq(void) |
1da177e4 LT |
198 | { |
199 | s3c24xx_init_irq(); | |
200 | } | |
201 | ||
1da177e4 LT |
202 | static void __init rx3715_init_machine(void) |
203 | { | |
b1dfe1f1 | 204 | #ifdef CONFIG_PM_H1940 |
bbf6f280 | 205 | memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); |
b1dfe1f1 | 206 | #endif |
1da177e4 | 207 | s3c2410_pm_init(); |
bbf6f280 | 208 | |
09fe75f6 | 209 | s3c24xx_fb_set_platdata(&rx3715_fb_info); |
57e5171c | 210 | platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices)); |
1da177e4 | 211 | } |
e838ffc2 | 212 | |
1da177e4 | 213 | MACHINE_START(RX3715, "IPAQ-RX3715") |
e9dea0c6 | 214 | /* Maintainer: Ben Dooks <ben@fluff.org> */ |
e9dea0c6 RK |
215 | .phys_io = S3C2410_PA_UART, |
216 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | |
217 | .boot_params = S3C2410_SDRAM_PA + 0x100, | |
218 | .map_io = rx3715_map_io, | |
219 | .init_irq = rx3715_init_irq, | |
220 | .init_machine = rx3715_init_machine, | |
1da177e4 LT |
221 | .timer = &s3c24xx_timer, |
222 | MACHINE_END |