[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-s3c24xx / clock-s3c244x.c

/* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c
 *
 * Copyright (c) 2004-2008 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2440/S3C2442 Common clock support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <linux/atomic.h>
#include <asm/irq.h>

#include <mach/regs-clock.h>

#include <plat/clock.h>
#include <plat/cpu.h>

static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent)
{
	unsigned long camdivn;
	unsigned long dvs;

	if (parent == &clk_f)
		dvs = 0;
	else if (parent == &clk_h)
		dvs = S3C2440_CAMDIVN_DVSEN;
	else
		return -EINVAL;

	clk->parent = parent;

	camdivn  = __raw_readl(S3C2440_CAMDIVN);
	camdivn &= ~S3C2440_CAMDIVN_DVSEN;
	camdivn |= dvs;
	__raw_writel(camdivn, S3C2440_CAMDIVN);

	return 0;
}

static struct clk clk_arm = {
	.name		= "armclk",
	.id		= -1,
	.ops		= &(struct clk_ops) {
		.set_parent	= s3c2440_setparent_armclk,
	},
};

static int s3c244x_clk_add(struct device *dev, struct subsys_interface *sif)
{
	unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
	unsigned long clkdivn;
	struct clk *clock_upll;
	int ret;

	printk("S3C244X: Clock Support, DVS %s\n",
	       (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");

	clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f;

	ret = s3c24xx_register_clock(&clk_arm);
	if (ret < 0) {
		printk(KERN_ERR "S3C24XX: Failed to add armclk (%d)\n", ret);
		return ret;
	}

	clock_upll = clk_get(NULL, "upll");
	if (IS_ERR(clock_upll)) {
		printk(KERN_ERR "S3C244X: Failed to get upll clock\n");
		return -ENOENT;
	}

	/* check rate of UPLL, and if it is near 96MHz, then change
	 * to using half the UPLL rate for the system */

	if (clk_get_rate(clock_upll) > (94 * MHZ)) {
		clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;

		spin_lock(&clocks_lock);

		clkdivn = __raw_readl(S3C2410_CLKDIVN);
		clkdivn |= S3C2440_CLKDIVN_UCLK;
		__raw_writel(clkdivn, S3C2410_CLKDIVN);

		spin_unlock(&clocks_lock);
	}

	return 0;
}

static struct subsys_interface s3c2440_clk_interface = {
	.name		= "s3c2440_clk",
	.subsys		= &s3c2440_subsys,
	.add_dev	= s3c244x_clk_add,
};

static int s3c2440_clk_init(void)
{
	return subsys_interface_register(&s3c2440_clk_interface);
}

arch_initcall(s3c2440_clk_init);

static struct subsys_interface s3c2442_clk_interface = {
	.name		= "s3c2442_clk",
	.subsys		= &s3c2442_subsys,
	.add_dev	= s3c244x_clk_add,
};

static int s3c2442_clk_init(void)
{
	return subsys_interface_register(&s3c2442_clk_interface);
}

arch_initcall(s3c2442_clk_init);
Commit	Line	Data
3a38e4be BD	1	/* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c
3a38e4be BD	2	*
ccae941e	3	* Copyright (c) 2004-2008 Simtec Electronics
3a38e4be BD	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* S3C2440/S3C2442 Common clock support
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*/
	23
	24	#include <linux/init.h>
	25	#include <linux/module.h>
	26	#include <linux/kernel.h>
	27	#include <linux/list.h>
	28	#include <linux/errno.h>
	29	#include <linux/err.h>
	30	#include <linux/device.h>
3a38e4be BD	31	#include <linux/interrupt.h>
3a38e4be BD	32	#include <linux/ioport.h>
3a38e4be	33	#include <linux/clk.h>
fced80c7	34	#include <linux/io.h>
3a38e4be	35
a09e64fb	36	#include <mach/hardware.h>
60063497	37	#include <linux/atomic.h>
3a38e4be	38	#include <asm/irq.h>
3a38e4be	39
a09e64fb	40	#include <mach/regs-clock.h>
3a38e4be	41
d5120ae7	42	#include <plat/clock.h>
a2b7ba9c	43	#include <plat/cpu.h>
3a38e4be	44
06dbbd69 BD	45	static int s3c2440_setparent_armclk(struct clk clk, struct clk parent)
	46	{
	47	unsigned long camdivn;
	48	unsigned long dvs;
	49
	50	if (parent == &clk_f)
	51	dvs = 0;
	52	else if (parent == &clk_h)
	53	dvs = S3C2440_CAMDIVN_DVSEN;
	54	else
	55	return -EINVAL;
	56
	57	clk->parent = parent;
	58
	59	camdivn = __raw_readl(S3C2440_CAMDIVN);
	60	camdivn &= ~S3C2440_CAMDIVN_DVSEN;
	61	camdivn \|= dvs;
	62	__raw_writel(camdivn, S3C2440_CAMDIVN);
	63
	64	return 0;
	65	}
	66
	67	static struct clk clk_arm = {
	68	.name = "armclk",
	69	.id = -1,
b3bf41be BD	70	.ops = &(struct clk_ops) {
	71	.set_parent = s3c2440_setparent_armclk,
	72	},
06dbbd69 BD	73	};
06dbbd69 BD	74
04511a6f	75	static int s3c244x_clk_add(struct device dev, struct subsys_interface sif)
3a38e4be BD	76	{
	77	unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
	78	unsigned long clkdivn;
	79	struct clk *clock_upll;
06dbbd69	80	int ret;
3a38e4be BD	81
	82	printk("S3C244X: Clock Support, DVS %s\n",
	83	(camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
	84
06dbbd69 BD	85	clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f;
	86
	87	ret = s3c24xx_register_clock(&clk_arm);
	88	if (ret < 0) {
	89	printk(KERN_ERR "S3C24XX: Failed to add armclk (%d)\n", ret);
	90	return ret;
	91	}
	92
3a38e4be BD	93	clock_upll = clk_get(NULL, "upll");
	94	if (IS_ERR(clock_upll)) {
	95	printk(KERN_ERR "S3C244X: Failed to get upll clock\n");
	96	return -ENOENT;
	97	}
	98
	99	/* check rate of UPLL, and if it is near 96MHz, then change
	100	* to using half the UPLL rate for the system */
	101
	102	if (clk_get_rate(clock_upll) > (94 * MHZ)) {
	103	clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
	104
c3391e36	105	spin_lock(&clocks_lock);
3a38e4be BD	106
	107	clkdivn = __raw_readl(S3C2410_CLKDIVN);
	108	clkdivn \|= S3C2440_CLKDIVN_UCLK;
	109	__raw_writel(clkdivn, S3C2410_CLKDIVN);
	110
c3391e36	111	spin_unlock(&clocks_lock);
3a38e4be BD	112	}
	113
	114	return 0;
	115	}
	116
4a858cfc KS	117	static struct subsys_interface s3c2440_clk_interface = {
	118	.name = "s3c2440_clk",
	119	.subsys = &s3c2440_subsys,
	120	.add_dev = s3c244x_clk_add,
3a38e4be BD	121	};
	122
	123	static int s3c2440_clk_init(void)
	124	{
4a858cfc	125	return subsys_interface_register(&s3c2440_clk_interface);
3a38e4be BD	126	}
	127
	128	arch_initcall(s3c2440_clk_init);
	129
4a858cfc KS	130	static struct subsys_interface s3c2442_clk_interface = {
	131	.name = "s3c2442_clk",
	132	.subsys = &s3c2442_subsys,
	133	.add_dev = s3c244x_clk_add,
3a38e4be BD	134	};
	135
	136	static int s3c2442_clk_init(void)
	137	{
4a858cfc	138	return subsys_interface_register(&s3c2442_clk_interface);
3a38e4be BD	139	}
	140
	141	arch_initcall(s3c2442_clk_init);