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a21765a7 | 1 | /* linux/arch/arm/plat-s3c24xx/cpu.c |
1da177e4 LT |
2 | * |
3 | * Copyright (c) 2004-2005 Simtec Electronics | |
4 | * http://www.simtec.co.uk/products/SWLINUX/ | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * | |
4a9f52fd | 7 | * Common code for S3C24XX machines |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | ||
25 | #include <linux/init.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/ioport.h> | |
b6d1f542 | 29 | #include <linux/serial_core.h> |
334a1c70 | 30 | #include <linux/serial_s3c.h> |
1c161fd0 | 31 | #include <clocksource/samsung_pwm.h> |
d052d1be | 32 | #include <linux/platform_device.h> |
3c7d9c81 | 33 | #include <linux/delay.h> |
fced80c7 | 34 | #include <linux/io.h> |
f2dda07d | 35 | #include <linux/platform_data/dma-s3c24xx.h> |
1da177e4 | 36 | |
a09e64fb | 37 | #include <mach/hardware.h> |
92311272 | 38 | #include <mach/regs-clock.h> |
1da177e4 | 39 | #include <asm/irq.h> |
3c7d9c81 | 40 | #include <asm/cacheflush.h> |
9f97da78 | 41 | #include <asm/system_info.h> |
86dfe446 | 42 | #include <asm/system_misc.h> |
1da177e4 LT |
43 | |
44 | #include <asm/mach/arch.h> | |
45 | #include <asm/mach/map.h> | |
46 | ||
a09e64fb | 47 | #include <mach/regs-gpio.h> |
f2dda07d | 48 | #include <mach/dma.h> |
1da177e4 | 49 | |
a2b7ba9c BD |
50 | #include <plat/cpu.h> |
51 | #include <plat/devs.h> | |
d5120ae7 | 52 | #include <plat/clock.h> |
2473f713 HS |
53 | #include <plat/cpu-freq.h> |
54 | #include <plat/pll.h> | |
1c161fd0 | 55 | #include <plat/pwm-core.h> |
4659c534 | 56 | #include <plat/watchdog-reset.h> |
1da177e4 | 57 | |
e1a621da HS |
58 | #include "common.h" |
59 | ||
1da177e4 LT |
60 | /* table of supported CPUs */ |
61 | ||
62 | static const char name_s3c2410[] = "S3C2410"; | |
68d9ab39 | 63 | static const char name_s3c2412[] = "S3C2412"; |
63b1f51b | 64 | static const char name_s3c2416[] = "S3C2416/S3C2450"; |
1da177e4 | 65 | static const char name_s3c2440[] = "S3C2440"; |
96ce2385 | 66 | static const char name_s3c2442[] = "S3C2442"; |
f5fb9b1a | 67 | static const char name_s3c2442b[] = "S3C2442B"; |
e4d06e39 | 68 | static const char name_s3c2443[] = "S3C2443"; |
1da177e4 LT |
69 | static const char name_s3c2410a[] = "S3C2410A"; |
70 | static const char name_s3c2440a[] = "S3C2440A"; | |
71 | ||
72 | static struct cpu_table cpu_ids[] __initdata = { | |
73 | { | |
74 | .idcode = 0x32410000, | |
75 | .idmask = 0xffffffff, | |
76 | .map_io = s3c2410_map_io, | |
1da177e4 LT |
77 | .init_uarts = s3c2410_init_uarts, |
78 | .init = s3c2410_init, | |
79 | .name = name_s3c2410 | |
80 | }, | |
81 | { | |
82 | .idcode = 0x32410002, | |
83 | .idmask = 0xffffffff, | |
84 | .map_io = s3c2410_map_io, | |
1da177e4 | 85 | .init_uarts = s3c2410_init_uarts, |
f0176794 | 86 | .init = s3c2410a_init, |
1da177e4 LT |
87 | .name = name_s3c2410a |
88 | }, | |
89 | { | |
90 | .idcode = 0x32440000, | |
91 | .idmask = 0xffffffff, | |
812c4e40 | 92 | .map_io = s3c2440_map_io, |
96ce2385 | 93 | .init_uarts = s3c244x_init_uarts, |
1da177e4 LT |
94 | .init = s3c2440_init, |
95 | .name = name_s3c2440 | |
96 | }, | |
97 | { | |
98 | .idcode = 0x32440001, | |
99 | .idmask = 0xffffffff, | |
812c4e40 | 100 | .map_io = s3c2440_map_io, |
96ce2385 | 101 | .init_uarts = s3c244x_init_uarts, |
1da177e4 LT |
102 | .init = s3c2440_init, |
103 | .name = name_s3c2440a | |
83f755f5 | 104 | }, |
96ce2385 BD |
105 | { |
106 | .idcode = 0x32440aaa, | |
107 | .idmask = 0xffffffff, | |
812c4e40 | 108 | .map_io = s3c2442_map_io, |
96ce2385 BD |
109 | .init_uarts = s3c244x_init_uarts, |
110 | .init = s3c2442_init, | |
111 | .name = name_s3c2442 | |
112 | }, | |
f5fb9b1a HW |
113 | { |
114 | .idcode = 0x32440aab, | |
115 | .idmask = 0xffffffff, | |
812c4e40 | 116 | .map_io = s3c2442_map_io, |
f5fb9b1a HW |
117 | .init_uarts = s3c244x_init_uarts, |
118 | .init = s3c2442_init, | |
119 | .name = name_s3c2442b | |
120 | }, | |
68d9ab39 BD |
121 | { |
122 | .idcode = 0x32412001, | |
123 | .idmask = 0xffffffff, | |
124 | .map_io = s3c2412_map_io, | |
68d9ab39 BD |
125 | .init_uarts = s3c2412_init_uarts, |
126 | .init = s3c2412_init, | |
127 | .name = name_s3c2412, | |
128 | }, | |
d9bc55fa BD |
129 | { /* a newer version of the s3c2412 */ |
130 | .idcode = 0x32412003, | |
131 | .idmask = 0xffffffff, | |
132 | .map_io = s3c2412_map_io, | |
d9bc55fa BD |
133 | .init_uarts = s3c2412_init_uarts, |
134 | .init = s3c2412_init, | |
135 | .name = name_s3c2412, | |
136 | }, | |
f1290a49 YK |
137 | { /* a strange version of the s3c2416 */ |
138 | .idcode = 0x32450003, | |
139 | .idmask = 0xffffffff, | |
140 | .map_io = s3c2416_map_io, | |
f1290a49 YK |
141 | .init_uarts = s3c2416_init_uarts, |
142 | .init = s3c2416_init, | |
143 | .name = name_s3c2416, | |
144 | }, | |
e4d06e39 BD |
145 | { |
146 | .idcode = 0x32443001, | |
147 | .idmask = 0xffffffff, | |
148 | .map_io = s3c2443_map_io, | |
e4d06e39 BD |
149 | .init_uarts = s3c2443_init_uarts, |
150 | .init = s3c2443_init, | |
151 | .name = name_s3c2443, | |
152 | }, | |
1da177e4 LT |
153 | }; |
154 | ||
155 | /* minimal IO mapping */ | |
156 | ||
157 | static struct map_desc s3c_iodesc[] __initdata = { | |
158 | IODESC_ENT(GPIO), | |
159 | IODESC_ENT(IRQ), | |
160 | IODESC_ENT(MEMCTRL), | |
161 | IODESC_ENT(UART) | |
162 | }; | |
163 | ||
74b265d4 | 164 | /* read cpu identificaiton code */ |
1da177e4 | 165 | |
68d9ab39 BD |
166 | static unsigned long s3c24xx_read_idcode_v5(void) |
167 | { | |
d11a7d71 BD |
168 | #if defined(CONFIG_CPU_S3C2416) |
169 | /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */ | |
170 | ||
171 | u32 gs = __raw_readl(S3C24XX_GSTATUS1); | |
172 | ||
173 | /* test for s3c2416 or similar device */ | |
174 | if ((gs >> 16) == 0x3245) | |
175 | return gs; | |
176 | #endif | |
177 | ||
68d9ab39 BD |
178 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) |
179 | return __raw_readl(S3C2412_GSTATUS1); | |
180 | #else | |
181 | return 1UL; /* don't look like an 2400 */ | |
182 | #endif | |
183 | } | |
184 | ||
185 | static unsigned long s3c24xx_read_idcode_v4(void) | |
186 | { | |
68d9ab39 | 187 | return __raw_readl(S3C2410_GSTATUS1); |
68d9ab39 BD |
188 | } |
189 | ||
92311272 NP |
190 | static void s3c24xx_default_idle(void) |
191 | { | |
813f13e7 | 192 | unsigned long tmp = 0; |
92311272 NP |
193 | int i; |
194 | ||
195 | /* idle the system by using the idle mode which will wait for an | |
196 | * interrupt to happen before restarting the system. | |
197 | */ | |
198 | ||
199 | /* Warning: going into idle state upsets jtag scanning */ | |
200 | ||
201 | __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE, | |
202 | S3C2410_CLKCON); | |
203 | ||
204 | /* the samsung port seems to do a loop and then unset idle.. */ | |
205 | for (i = 0; i < 50; i++) | |
206 | tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */ | |
207 | ||
208 | /* this bit is not cleared on re-start... */ | |
209 | ||
210 | __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE, | |
211 | S3C2410_CLKCON); | |
212 | } | |
213 | ||
1c161fd0 TF |
214 | static struct samsung_pwm_variant s3c24xx_pwm_variant = { |
215 | .bits = 16, | |
216 | .div_base = 1, | |
217 | .has_tint_cstat = false, | |
218 | .tclk_mask = (1 << 4), | |
219 | }; | |
220 | ||
1da177e4 LT |
221 | void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) |
222 | { | |
92311272 NP |
223 | arm_pm_idle = s3c24xx_default_idle; |
224 | ||
1da177e4 | 225 | /* initialise the io descriptors we need for initialisation */ |
74b265d4 | 226 | iotable_init(mach_desc, size); |
1da177e4 LT |
227 | iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); |
228 | ||
68d9ab39 | 229 | if (cpu_architecture() >= CPU_ARCH_ARMv5) { |
c06af3cc | 230 | samsung_cpu_id = s3c24xx_read_idcode_v5(); |
68d9ab39 | 231 | } else { |
c06af3cc | 232 | samsung_cpu_id = s3c24xx_read_idcode_v4(); |
68d9ab39 | 233 | } |
83f755f5 | 234 | |
c06af3cc | 235 | s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); |
1c161fd0 TF |
236 | |
237 | samsung_pwm_set_platdata(&s3c24xx_pwm_variant); | |
66a9b49a | 238 | } |
618ae08a | 239 | |
4280506a TF |
240 | void __init samsung_set_timer_source(unsigned int event, unsigned int source) |
241 | { | |
242 | s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; | |
243 | s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); | |
244 | } | |
245 | ||
246 | void __init samsung_timer_init(void) | |
247 | { | |
248 | unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { | |
249 | IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4, | |
250 | }; | |
251 | ||
252 | samsung_pwm_clocksource_init(S3C_VA_TIMER, | |
253 | timer_irqs, &s3c24xx_pwm_variant); | |
254 | } | |
255 | ||
618ae08a HS |
256 | /* Serial port registrations */ |
257 | ||
9ee51f01 AB |
258 | #define S3C2410_PA_UART0 (S3C24XX_PA_UART) |
259 | #define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 ) | |
260 | #define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 ) | |
261 | #define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 ) | |
262 | ||
618ae08a | 263 | static struct resource s3c2410_uart0_resource[] = { |
99dbdd98 TB |
264 | [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K), |
265 | [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \ | |
266 | IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \ | |
267 | NULL, IORESOURCE_IRQ) | |
618ae08a HS |
268 | }; |
269 | ||
270 | static struct resource s3c2410_uart1_resource[] = { | |
99dbdd98 TB |
271 | [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K), |
272 | [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \ | |
273 | IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \ | |
274 | NULL, IORESOURCE_IRQ) | |
618ae08a HS |
275 | }; |
276 | ||
277 | static struct resource s3c2410_uart2_resource[] = { | |
99dbdd98 TB |
278 | [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K), |
279 | [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \ | |
280 | IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \ | |
281 | NULL, IORESOURCE_IRQ) | |
618ae08a HS |
282 | }; |
283 | ||
284 | static struct resource s3c2410_uart3_resource[] = { | |
99dbdd98 TB |
285 | [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K), |
286 | [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \ | |
287 | IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \ | |
288 | NULL, IORESOURCE_IRQ) | |
618ae08a HS |
289 | }; |
290 | ||
291 | struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { | |
292 | [0] = { | |
293 | .resources = s3c2410_uart0_resource, | |
294 | .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource), | |
295 | }, | |
296 | [1] = { | |
297 | .resources = s3c2410_uart1_resource, | |
298 | .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource), | |
299 | }, | |
300 | [2] = { | |
301 | .resources = s3c2410_uart2_resource, | |
302 | .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource), | |
303 | }, | |
304 | [3] = { | |
305 | .resources = s3c2410_uart3_resource, | |
306 | .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource), | |
307 | }, | |
308 | }; | |
2473f713 HS |
309 | |
310 | /* initialise all the clocks */ | |
311 | ||
5ab9a428 | 312 | #ifdef CONFIG_SAMSUNG_CLOCK |
2473f713 HS |
313 | void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, |
314 | unsigned long hclk, | |
315 | unsigned long pclk) | |
316 | { | |
317 | clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), | |
318 | clk_xtal.rate); | |
319 | ||
320 | clk_mpll.rate = fclk; | |
321 | clk_h.rate = hclk; | |
322 | clk_p.rate = pclk; | |
323 | clk_f.rate = fclk; | |
324 | } | |
5ab9a428 | 325 | #endif |
f2dda07d HS |
326 | |
327 | #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ | |
328 | defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) | |
329 | static struct resource s3c2410_dma_resource[] = { | |
330 | [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA), | |
331 | [1] = DEFINE_RES_IRQ(IRQ_DMA0), | |
332 | [2] = DEFINE_RES_IRQ(IRQ_DMA1), | |
333 | [3] = DEFINE_RES_IRQ(IRQ_DMA2), | |
334 | [4] = DEFINE_RES_IRQ(IRQ_DMA3), | |
335 | }; | |
336 | #endif | |
337 | ||
1fecf895 HS |
338 | #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442) |
339 | static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = { | |
340 | [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), }, | |
341 | [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), }, | |
342 | [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) | | |
343 | S3C24XX_DMA_CHANREQ(2, 2) | | |
344 | S3C24XX_DMA_CHANREQ(1, 3), | |
345 | }, | |
346 | [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), }, | |
347 | [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), }, | |
348 | [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), }, | |
349 | [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), }, | |
350 | [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), }, | |
351 | [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) | | |
352 | S3C24XX_DMA_CHANREQ(3, 2) | | |
353 | S3C24XX_DMA_CHANREQ(3, 3), | |
354 | }, | |
355 | [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) | | |
356 | S3C24XX_DMA_CHANREQ(1, 2), | |
357 | }, | |
358 | [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), }, | |
359 | [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), }, | |
360 | [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), }, | |
361 | [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), }, | |
362 | [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), }, | |
363 | }; | |
364 | ||
365 | static struct s3c24xx_dma_platdata s3c2410_dma_platdata = { | |
366 | .num_phy_channels = 4, | |
367 | .channels = s3c2410_dma_channels, | |
368 | .num_channels = DMACH_MAX, | |
369 | }; | |
370 | ||
371 | struct platform_device s3c2410_device_dma = { | |
372 | .name = "s3c2410-dma", | |
373 | .id = 0, | |
374 | .num_resources = ARRAY_SIZE(s3c2410_dma_resource), | |
375 | .resource = s3c2410_dma_resource, | |
376 | .dev = { | |
377 | .platform_data = &s3c2410_dma_platdata, | |
378 | }, | |
379 | }; | |
380 | #endif | |
381 | ||
f2dda07d HS |
382 | #ifdef CONFIG_CPU_S3C2412 |
383 | static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = { | |
384 | [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 }, | |
385 | [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 }, | |
386 | [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 }, | |
387 | [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 }, | |
388 | [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 }, | |
389 | [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 }, | |
390 | [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 }, | |
391 | [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 }, | |
392 | [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 }, | |
393 | [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 }, | |
394 | [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 }, | |
395 | [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 }, | |
396 | [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 }, | |
397 | [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 }, | |
398 | [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 }, | |
399 | [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 }, | |
400 | [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 }, | |
401 | [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 }, | |
402 | [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 }, | |
403 | [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 }, | |
404 | }; | |
405 | ||
406 | static struct s3c24xx_dma_platdata s3c2412_dma_platdata = { | |
407 | .num_phy_channels = 4, | |
408 | .channels = s3c2412_dma_channels, | |
409 | .num_channels = DMACH_MAX, | |
410 | }; | |
411 | ||
412 | struct platform_device s3c2412_device_dma = { | |
413 | .name = "s3c2412-dma", | |
414 | .id = 0, | |
415 | .num_resources = ARRAY_SIZE(s3c2410_dma_resource), | |
416 | .resource = s3c2410_dma_resource, | |
417 | .dev = { | |
418 | .platform_data = &s3c2412_dma_platdata, | |
419 | }, | |
420 | }; | |
421 | #endif | |
422 | ||
1fecf895 HS |
423 | #if defined(CONFIG_CPU_S3C2440) |
424 | static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = { | |
425 | [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), }, | |
426 | [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), }, | |
427 | [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) | | |
428 | S3C24XX_DMA_CHANREQ(6, 1) | | |
429 | S3C24XX_DMA_CHANREQ(2, 2) | | |
430 | S3C24XX_DMA_CHANREQ(1, 3), | |
431 | }, | |
432 | [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), }, | |
433 | [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), }, | |
434 | [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), }, | |
435 | [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), }, | |
436 | [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), }, | |
437 | [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) | | |
438 | S3C24XX_DMA_CHANREQ(3, 2) | | |
439 | S3C24XX_DMA_CHANREQ(3, 3), | |
440 | }, | |
441 | [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) | | |
442 | S3C24XX_DMA_CHANREQ(1, 2), | |
443 | }, | |
444 | [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) | | |
445 | S3C24XX_DMA_CHANREQ(0, 2), | |
446 | }, | |
447 | [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) | | |
448 | S3C24XX_DMA_CHANREQ(5, 2), | |
449 | }, | |
450 | [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) | | |
451 | S3C24XX_DMA_CHANREQ(6, 3), | |
452 | }, | |
453 | [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) | | |
454 | S3C24XX_DMA_CHANREQ(5, 3), | |
455 | }, | |
456 | [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), }, | |
457 | [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), }, | |
458 | [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), }, | |
459 | [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), }, | |
460 | }; | |
461 | ||
462 | static struct s3c24xx_dma_platdata s3c2440_dma_platdata = { | |
463 | .num_phy_channels = 4, | |
464 | .channels = s3c2440_dma_channels, | |
465 | .num_channels = DMACH_MAX, | |
466 | }; | |
467 | ||
468 | struct platform_device s3c2440_device_dma = { | |
469 | .name = "s3c2410-dma", | |
470 | .id = 0, | |
471 | .num_resources = ARRAY_SIZE(s3c2410_dma_resource), | |
472 | .resource = s3c2410_dma_resource, | |
473 | .dev = { | |
474 | .platform_data = &s3c2440_dma_platdata, | |
475 | }, | |
476 | }; | |
477 | #endif | |
478 | ||
469641ca | 479 | #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) |
f2dda07d HS |
480 | static struct resource s3c2443_dma_resource[] = { |
481 | [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA), | |
482 | [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0), | |
483 | [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1), | |
484 | [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2), | |
485 | [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3), | |
486 | [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4), | |
487 | [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5), | |
488 | }; | |
489 | ||
490 | static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = { | |
491 | [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 }, | |
492 | [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 }, | |
493 | [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 }, | |
494 | [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 }, | |
495 | [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 }, | |
496 | [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 }, | |
497 | [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 }, | |
498 | [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 }, | |
499 | [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 }, | |
500 | [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 }, | |
501 | [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 }, | |
502 | [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 }, | |
503 | [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 }, | |
504 | [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 }, | |
505 | [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 }, | |
506 | [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 }, | |
507 | [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 }, | |
508 | [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 }, | |
509 | [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 }, | |
510 | [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 }, | |
511 | [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 }, | |
512 | }; | |
513 | ||
514 | static struct s3c24xx_dma_platdata s3c2443_dma_platdata = { | |
515 | .num_phy_channels = 6, | |
516 | .channels = s3c2443_dma_channels, | |
517 | .num_channels = DMACH_MAX, | |
518 | }; | |
519 | ||
520 | struct platform_device s3c2443_device_dma = { | |
521 | .name = "s3c2443-dma", | |
522 | .id = 0, | |
523 | .num_resources = ARRAY_SIZE(s3c2443_dma_resource), | |
524 | .resource = s3c2443_dma_resource, | |
525 | .dev = { | |
526 | .platform_data = &s3c2443_dma_platdata, | |
527 | }, | |
528 | }; | |
529 | #endif | |
dfc0f509 | 530 | |
4659c534 HS |
531 | #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410) |
532 | void __init s3c2410_init_clocks(int xtal) | |
533 | { | |
534 | s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); | |
535 | samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG); | |
536 | } | |
537 | #endif | |
538 | ||
3c27f314 HS |
539 | #ifdef CONFIG_CPU_S3C2412 |
540 | void __init s3c2412_init_clocks(int xtal) | |
541 | { | |
542 | s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); | |
543 | } | |
544 | #endif | |
545 | ||
dfc0f509 HS |
546 | #ifdef CONFIG_CPU_S3C2416 |
547 | void __init s3c2416_init_clocks(int xtal) | |
548 | { | |
549 | s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); | |
550 | } | |
551 | #endif | |
552 | ||
4659c534 HS |
553 | #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440) |
554 | void __init s3c2440_init_clocks(int xtal) | |
555 | { | |
556 | s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR); | |
557 | samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG); | |
558 | } | |
559 | #endif | |
560 | ||
561 | #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442) | |
562 | void __init s3c2442_init_clocks(int xtal) | |
563 | { | |
564 | s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR); | |
565 | samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG); | |
566 | } | |
567 | #endif | |
568 | ||
dfc0f509 HS |
569 | #ifdef CONFIG_CPU_S3C2443 |
570 | void __init s3c2443_init_clocks(int xtal) | |
571 | { | |
572 | s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR); | |
573 | } | |
574 | #endif | |
51cb1289 HS |
575 | |
576 | #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \ | |
577 | defined(CONFIG_CPU_S3C2442) | |
578 | static struct resource s3c2410_dclk_resource[] = { | |
579 | [0] = DEFINE_RES_MEM(0x56000084, 0x4), | |
580 | }; | |
581 | ||
582 | struct platform_device s3c2410_device_dclk = { | |
583 | .name = "s3c2410-dclk", | |
584 | .id = 0, | |
585 | .num_resources = ARRAY_SIZE(s3c2410_dclk_resource), | |
586 | .resource = s3c2410_dclk_resource, | |
587 | }; | |
588 | #endif |