[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-s3c24xx / mach-anubis.c

/* linux/arch/arm/mach-s3c2440/mach-anubis.c
 *
 * Copyright 2003-2009 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/sm501.h>
#include <linux/sm501-regs.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
#include <mach/gpio-samsung.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <net/ax88796.h>

#include <plat/devs.h>
#include <plat/cpu.h>
#include <linux/platform_data/asoc-s3c24xx_simtec.h>
#include <plat/samsung-time.h>

#include "anubis.h"
#include "common.h"
#include "simtec.h"

#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"

static struct map_desc anubis_iodesc[] __initdata = {
  /* ISA IO areas */

  {
	.virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	.pfn		= __phys_to_pfn(0x0),
	.length		= SZ_4M,
	.type		= MT_DEVICE,
  }, {
	.virtual	= (u32)S3C24XX_VA_ISA_WORD,
	.pfn		= __phys_to_pfn(0x0),
	.length 	= SZ_4M,
	.type		= MT_DEVICE,
  },

  /* we could possibly compress the next set down into a set of smaller tables
   * pagetables, but that would mean using an L2 section, and it still means
   * we cannot actually feed the same register to an LDR due to 16K spacing
   */

  /* CPLD control registers */

  {
	.virtual	= (u32)ANUBIS_VA_CTRL1,
	.pfn		= __phys_to_pfn(ANUBIS_PA_CTRL1),
	.length		= SZ_4K,
	.type		= MT_DEVICE,
  }, {
	.virtual	= (u32)ANUBIS_VA_IDREG,
	.pfn		= __phys_to_pfn(ANUBIS_PA_IDREG),
	.length		= SZ_4K,
	.type		= MT_DEVICE,
  },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
	},
	[1] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
	},
};

/* NAND Flash on Anubis board */

static int external_map[]   = { 2 };
static int chip0_map[]      = { 0 };
static int chip1_map[]      = { 1 };

static struct mtd_partition __initdata anubis_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_128K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_128K,
		.offset	= SZ_128K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the Anubis has 3 selectable slots for nand-flash, the two
 * on-board chip areas, as well as the external slot.
 *
 * Note, there is no current hot-plug support for the External
 * socket.
*/

static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
	[1] = {
		.name		= "External",
		.nr_chips	= 1,
		.nr_map		= external_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
	[0] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
};

static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(ANUBIS_VA_CTRL1);
	tmp &= ~ANUBIS_CTRL1_NANDSEL;
	tmp |= slot;

	pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);

	__raw_writeb(tmp, ANUBIS_VA_CTRL1);
}

static struct s3c2410_platform_nand __initdata anubis_nand_info = {
	.tacls		= 25,
	.twrph0		= 55,
	.twrph1		= 40,
	.nr_sets	= ARRAY_SIZE(anubis_nand_sets),
	.sets		= anubis_nand_sets,
	.select_chip	= anubis_nand_select,
};

/* IDE channels */

static struct pata_platform_info anubis_ide_platdata = {
	.ioport_shift	= 5,
};

static struct resource anubis_ide0_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32),
	[2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32),
	[3] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
};

static struct platform_device anubis_device_ide0 = {
	.name		= "pata_platform",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_ide0_resource),
	.resource	= anubis_ide0_resource,
	.dev	= {
		.platform_data = &anubis_ide_platdata,
		.coherent_dma_mask = ~0,
	},
};

static struct resource anubis_ide1_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32),
	[1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32),
	[2] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
};

static struct platform_device anubis_device_ide1 = {
	.name		= "pata_platform",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(anubis_ide1_resource),
	.resource	= anubis_ide1_resource,
	.dev	= {
		.platform_data = &anubis_ide_platdata,
		.coherent_dma_mask = ~0,
	},
};

/* Asix AX88796 10/100 ethernet controller */

static struct ax_plat_data anubis_asix_platdata = {
	.flags		= AXFLG_MAC_FROMDEV,
	.wordlength	= 2,
	.dcr_val	= 0x48,
	.rcr_val	= 0x40,
};

static struct resource anubis_asix_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20),
	[1] = DEFINE_RES_IRQ(ANUBIS_IRQ_ASIX),
};

static struct platform_device anubis_device_asix = {
	.name		= "ax88796",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_asix_resource),
	.resource	= anubis_asix_resource,
	.dev		= {
		.platform_data = &anubis_asix_platdata,
	}
};

/* SM501 */

static struct resource anubis_sm501_resource[] = {
	[0] = DEFINE_RES_MEM(S3C2410_CS2, SZ_8M),
	[1] = DEFINE_RES_MEM(S3C2410_CS2 + SZ_64M - SZ_2M, SZ_2M),
	[2] = DEFINE_RES_IRQ(IRQ_EINT0),
};

static struct sm501_initdata anubis_sm501_initdata = {
	.gpio_high	= {
		.set	= 0x3F000000,		/* 24bit panel */
		.mask	= 0x0,
	},
	.misc_timing	= {
		.set	= 0x010100,		/* SDRAM timing */
		.mask	= 0x1F1F00,
	},
	.misc_control	= {
		.set	= SM501_MISC_PNL_24BIT,
		.mask	= 0,
	},

	.devices	= SM501_USE_GPIO,

	/* set the SDRAM and bus clocks */
	.mclk		= 72 * MHZ,
	.m1xclk		= 144 * MHZ,
};

static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
	[0] = {
		.bus_num	= 1,
		.pin_scl	= 44,
		.pin_sda	= 45,
	},
	[1] = {
		.bus_num	= 2,
		.pin_scl	= 40,
		.pin_sda	= 41,
	},
};

static struct sm501_platdata anubis_sm501_platdata = {
	.init		= &anubis_sm501_initdata,
	.gpio_base	= -1,
	.gpio_i2c	= anubis_sm501_gpio_i2c,
	.gpio_i2c_nr	= ARRAY_SIZE(anubis_sm501_gpio_i2c),
};

static struct platform_device anubis_device_sm501 = {
	.name		= "sm501",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_sm501_resource),
	.resource	= anubis_sm501_resource,
	.dev		= {
		.platform_data = &anubis_sm501_platdata,
	},
};

/* Standard Anubis devices */

static struct platform_device *anubis_devices[] __initdata = {
	&s3c2410_device_dclk,
	&s3c_device_ohci,
	&s3c_device_wdt,
	&s3c_device_adc,
	&s3c_device_i2c0,
 	&s3c_device_rtc,
	&s3c_device_nand,
	&anubis_device_ide0,
	&anubis_device_ide1,
	&anubis_device_asix,
	&anubis_device_sm501,
};

/* I2C devices. */

static struct i2c_board_info anubis_i2c_devs[] __initdata = {
	{
		I2C_BOARD_INFO("tps65011", 0x48),
		.irq	= IRQ_EINT20,
	}
};

/* Audio setup */
static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
	.have_mic	= 1,
	.have_lout	= 1,
	.output_cdclk	= 1,
	.use_mpllin	= 1,
	.amp_gpio	= S3C2410_GPB(2),
	.amp_gain[0]	= S3C2410_GPD(10),
	.amp_gain[1]	= S3C2410_GPD(11),
};

static void __init anubis_map_io(void)
{
	s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
	s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
	samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);

	/* check for the newer revision boards with large page nand */

	if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
		printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
		       __raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
		anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
		anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
	} else {
		/* ensure that the GPIO is setup */
		gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
		gpio_free(S3C2410_GPA(0));
	}
}

static void __init anubis_init_time(void)
{
	s3c2440_init_clocks(12000000);
	samsung_timer_init();
}

static void __init anubis_init(void)
{
	s3c_i2c0_set_platdata(NULL);
	s3c_nand_set_platdata(&anubis_nand_info);
	simtec_audio_add(NULL, false, &anubis_audio);

	platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));

	i2c_register_board_info(0, anubis_i2c_devs,
				ARRAY_SIZE(anubis_i2c_devs));
}


MACHINE_START(ANUBIS, "Simtec-Anubis")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.atag_offset	= 0x100,
	.map_io		= anubis_map_io,
	.init_machine	= anubis_init,
	.init_irq	= s3c2440_init_irq,
	.init_time	= anubis_init_time,
MACHINE_END
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/mach-anubis.c
7efb833d	2	*
50f430e3	3	* Copyright 2003-2009 Simtec Electronics
7efb833d BD	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
7efb833d BD	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
7efb833d BD	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/list.h>
	16	#include <linux/timer.h>
	17	#include <linux/init.h>
ec976d6e	18	#include <linux/gpio.h>
b6d1f542	19	#include <linux/serial_core.h>
334a1c70	20	#include <linux/serial_s3c.h>
d052d1be	21	#include <linux/platform_device.h>
b9db83af	22	#include <linux/ata_platform.h>
7a28db61	23	#include <linux/i2c.h>
fced80c7	24	#include <linux/io.h>
8a9ccb7f BD	25	#include <linux/sm501.h>
	26	#include <linux/sm501-regs.h>
	27
7efb833d BD	28	#include <asm/mach/arch.h>
	29	#include <asm/mach/map.h>
	30	#include <asm/mach/irq.h>
	31
a09e64fb	32	#include <mach/hardware.h>
7efb833d BD	33	#include <asm/irq.h>
	34	#include <asm/mach-types.h>
	35
a09e64fb	36	#include <mach/regs-gpio.h>
a09e64fb	37	#include <mach/regs-lcd.h>
b0161caa	38	#include <mach/gpio-samsung.h>
436d42c6 AB	39	#include <linux/platform_data/mtd-nand-s3c2410.h>
436d42c6 AB	40	#include <linux/platform_data/i2c-s3c2410.h>
7efb833d BD	41
	42	#include <linux/mtd/mtd.h>
	43	#include <linux/mtd/nand.h>
	44	#include <linux/mtd/nand_ecc.h>
	45	#include <linux/mtd/partitions.h>
	46
eac1d8da BD	47	#include <net/ax88796.h>
eac1d8da BD	48
a2b7ba9c BD	49	#include <plat/devs.h>
a2b7ba9c BD	50	#include <plat/cpu.h>
436d42c6	51	#include <linux/platform_data/asoc-s3c24xx_simtec.h>
7f78b6eb	52	#include <plat/samsung-time.h>
7efb833d	53
fc351246	54	#include "anubis.h"
b27b0727	55	#include "common.h"
fc351246	56	#include "simtec.h"
b27b0727	57
50f430e3	58	#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
7efb833d BD	59
	60	static struct map_desc anubis_iodesc[] __initdata = {
	61	/* ISA IO areas */
	62
8dd52311 BD	63	{
	64	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	65	.pfn = __phys_to_pfn(0x0),
	66	.length = SZ_4M,
705630db	67	.type = MT_DEVICE,
8dd52311 BD	68	}, {
	69	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	70	.pfn = __phys_to_pfn(0x0),
705630db BD	71	.length = SZ_4M,
705630db BD	72	.type = MT_DEVICE,
8dd52311	73	},
7efb833d BD	74
	75	/* we could possibly compress the next set down into a set of smaller tables
	76	* pagetables, but that would mean using an L2 section, and it still means
	77	* we cannot actually feed the same register to an LDR due to 16K spacing
	78	*/
	79
	80	/* CPLD control registers */
	81
8dd52311 BD	82	{
	83	.virtual = (u32)ANUBIS_VA_CTRL1,
	84	.pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
	85	.length = SZ_4K,
705630db	86	.type = MT_DEVICE,
8dd52311	87	}, {
6c1640d5 BD	88	.virtual = (u32)ANUBIS_VA_IDREG,
6c1640d5 BD	89	.pfn = __phys_to_pfn(ANUBIS_PA_IDREG),
8dd52311	90	.length = SZ_4K,
705630db	91	.type = MT_DEVICE,
8dd52311	92	},
7efb833d BD	93	};
	94
	95	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	96	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	97	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	98
66a9b49a	99	static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
7efb833d BD	100	[0] = {
	101	.hwport = 0,
	102	.flags = 0,
	103	.ucon = UCON,
	104	.ulcon = ULCON,
	105	.ufcon = UFCON,
afba7f91	106	.clk_sel = S3C2410_UCON_CLKSEL1 \| S3C2410_UCON_CLKSEL2,
7efb833d BD	107	},
	108	[1] = {
	109	.hwport = 2,
	110	.flags = 0,
	111	.ucon = UCON,
	112	.ulcon = ULCON,
	113	.ufcon = UFCON,
afba7f91	114	.clk_sel = S3C2410_UCON_CLKSEL1 \| S3C2410_UCON_CLKSEL2,
7efb833d BD	115	},
	116	};
	117
	118	/* NAND Flash on Anubis board */
	119
	120	static int external_map[] = { 2 };
	121	static int chip0_map[] = { 0 };
	122	static int chip1_map[] = { 1 };
	123
2a3a1804	124	static struct mtd_partition __initdata anubis_default_nand_part[] = {
7efb833d BD	125	[0] = {
	126	.name = "Boot Agent",
	127	.size = SZ_16K,
705630db	128	.offset = 0,
7efb833d BD	129	},
	130	[1] = {
	131	.name = "/boot",
	132	.size = SZ_4M - SZ_16K,
	133	.offset = SZ_16K,
	134	},
	135	[2] = {
	136	.name = "user1",
	137	.offset = SZ_4M,
	138	.size = SZ_32M - SZ_4M,
	139	},
	140	[3] = {
	141	.name = "user2",
	142	.offset = SZ_32M,
	143	.size = MTDPART_SIZ_FULL,
	144	}
	145	};
	146
2a3a1804	147	static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
ad3613f4 BD	148	[0] = {
	149	.name = "Boot Agent",
	150	.size = SZ_128K,
	151	.offset = 0,
	152	},
	153	[1] = {
	154	.name = "/boot",
	155	.size = SZ_4M - SZ_128K,
	156	.offset = SZ_128K,
	157	},
	158	[2] = {
	159	.name = "user1",
	160	.offset = SZ_4M,
	161	.size = SZ_32M - SZ_4M,
	162	},
	163	[3] = {
	164	.name = "user2",
	165	.offset = SZ_32M,
	166	.size = MTDPART_SIZ_FULL,
	167	}
	168	};
	169
7efb833d BD	170	/* the Anubis has 3 selectable slots for nand-flash, the two
	171	* on-board chip areas, as well as the external slot.
	172	*
	173	* Note, there is no current hot-plug support for the External
	174	* socket.
	175	*/
	176
2a3a1804	177	static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
7efb833d BD	178	[1] = {
	179	.name = "External",
	180	.nr_chips = 1,
	181	.nr_map = external_map,
	182	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	183	.partitions = anubis_default_nand_part,
7efb833d BD	184	},
	185	[0] = {
	186	.name = "chip0",
	187	.nr_chips = 1,
	188	.nr_map = chip0_map,
	189	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	190	.partitions = anubis_default_nand_part,
7efb833d BD	191	},
	192	[2] = {
	193	.name = "chip1",
	194	.nr_chips = 1,
	195	.nr_map = chip1_map,
	196	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	197	.partitions = anubis_default_nand_part,
7efb833d BD	198	},
	199	};
	200
	201	static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
	202	{
	203	unsigned int tmp;
	204
	205	slot = set->nr_map[slot] & 3;
	206
	207	pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
	208	slot, set, set->nr_map);
	209
	210	tmp = __raw_readb(ANUBIS_VA_CTRL1);
	211	tmp &= ~ANUBIS_CTRL1_NANDSEL;
	212	tmp \|= slot;
	213
	214	pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
	215
	216	__raw_writeb(tmp, ANUBIS_VA_CTRL1);
	217	}
	218
2a3a1804	219	static struct s3c2410_platform_nand __initdata anubis_nand_info = {
7efb833d	220	.tacls = 25,
661e6acf BD	221	.twrph0 = 55,
661e6acf BD	222	.twrph1 = 40,
7efb833d BD	223	.nr_sets = ARRAY_SIZE(anubis_nand_sets),
	224	.sets = anubis_nand_sets,
	225	.select_chip = anubis_nand_select,
	226	};
	227
bf1c56a3 BD	228	/* IDE channels */
bf1c56a3 BD	229
019dbaa1	230	static struct pata_platform_info anubis_ide_platdata = {
b9db83af BD	231	.ioport_shift = 5,
	232	};
	233
bf1c56a3	234	static struct resource anubis_ide0_resource[] = {
d1c14938 TB	235	[0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32),
d1c14938 TB	236	[2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32),
fc351246	237	[3] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
bf1c56a3 BD	238	};
	239
	240	static struct platform_device anubis_device_ide0 = {
b9db83af	241	.name = "pata_platform",
bf1c56a3 BD	242	.id = 0,
	243	.num_resources = ARRAY_SIZE(anubis_ide0_resource),
	244	.resource = anubis_ide0_resource,
b9db83af BD	245	.dev = {
	246	.platform_data = &anubis_ide_platdata,
	247	.coherent_dma_mask = ~0,
	248	},
bf1c56a3 BD	249	};
	250
	251	static struct resource anubis_ide1_resource[] = {
d1c14938 TB	252	[0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32),
d1c14938 TB	253	[1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32),
fc351246	254	[2] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
bf1c56a3 BD	255	};
bf1c56a3 BD	256
bf1c56a3	257	static struct platform_device anubis_device_ide1 = {
b9db83af	258	.name = "pata_platform",
bf1c56a3 BD	259	.id = 1,
	260	.num_resources = ARRAY_SIZE(anubis_ide1_resource),
	261	.resource = anubis_ide1_resource,
b9db83af BD	262	.dev = {
	263	.platform_data = &anubis_ide_platdata,
	264	.coherent_dma_mask = ~0,
	265	},
bf1c56a3	266	};
7efb833d	267
eac1d8da BD	268	/* Asix AX88796 10/100 ethernet controller */
	269
	270	static struct ax_plat_data anubis_asix_platdata = {
	271	.flags = AXFLG_MAC_FROMDEV,
	272	.wordlength = 2,
	273	.dcr_val = 0x48,
	274	.rcr_val = 0x40,
	275	};
	276
	277	static struct resource anubis_asix_resource[] = {
d1c14938	278	[0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20),
fc351246	279	[1] = DEFINE_RES_IRQ(ANUBIS_IRQ_ASIX),
eac1d8da BD	280	};
	281
	282	static struct platform_device anubis_device_asix = {
	283	.name = "ax88796",
	284	.id = 0,
	285	.num_resources = ARRAY_SIZE(anubis_asix_resource),
	286	.resource = anubis_asix_resource,
	287	.dev = {
	288	.platform_data = &anubis_asix_platdata,
	289	}
	290	};
	291
8a9ccb7f BD	292	/* SM501 */
	293
	294	static struct resource anubis_sm501_resource[] = {
d1c14938 TB	295	[0] = DEFINE_RES_MEM(S3C2410_CS2, SZ_8M),
	296	[1] = DEFINE_RES_MEM(S3C2410_CS2 + SZ_64M - SZ_2M, SZ_2M),
	297	[2] = DEFINE_RES_IRQ(IRQ_EINT0),
8a9ccb7f BD	298	};
	299
	300	static struct sm501_initdata anubis_sm501_initdata = {
	301	.gpio_high = {
	302	.set = 0x3F000000, /* 24bit panel */
	303	.mask = 0x0,
	304	},
	305	.misc_timing = {
	306	.set = 0x010100, /* SDRAM timing */
	307	.mask = 0x1F1F00,
	308	},
	309	.misc_control = {
	310	.set = SM501_MISC_PNL_24BIT,
	311	.mask = 0,
	312	},
	313
6290ce30 BD	314	.devices = SM501_USE_GPIO,
6290ce30 BD	315
8a9ccb7f BD	316	/* set the SDRAM and bus clocks */
	317	.mclk = 72 * MHZ,
	318	.m1xclk = 144 * MHZ,
	319	};
	320
	321	static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
	322	[0] = {
6290ce30	323	.bus_num = 1,
8a9ccb7f BD	324	.pin_scl = 44,
	325	.pin_sda = 45,
	326	},
	327	[1] = {
6290ce30	328	.bus_num = 2,
8a9ccb7f BD	329	.pin_scl = 40,
	330	.pin_sda = 41,
	331	},
	332	};
	333
	334	static struct sm501_platdata anubis_sm501_platdata = {
	335	.init = &anubis_sm501_initdata,
6290ce30	336	.gpio_base = -1,
8a9ccb7f BD	337	.gpio_i2c = anubis_sm501_gpio_i2c,
	338	.gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
	339	};
	340
	341	static struct platform_device anubis_device_sm501 = {
	342	.name = "sm501",
	343	.id = 0,
	344	.num_resources = ARRAY_SIZE(anubis_sm501_resource),
	345	.resource = anubis_sm501_resource,
	346	.dev = {
	347	.platform_data = &anubis_sm501_platdata,
	348	},
	349	};
	350
7efb833d BD	351	/* Standard Anubis devices */
	352
	353	static struct platform_device *anubis_devices[] __initdata = {
51cb1289	354	&s3c2410_device_dclk,
b813248c	355	&s3c_device_ohci,
7efb833d BD	356	&s3c_device_wdt,
7efb833d BD	357	&s3c_device_adc,
3e1b776c	358	&s3c_device_i2c0,
7efb833d BD	359	&s3c_device_rtc,
7efb833d BD	360	&s3c_device_nand,
bf1c56a3 BD	361	&anubis_device_ide0,
bf1c56a3 BD	362	&anubis_device_ide1,
eac1d8da	363	&anubis_device_asix,
8a9ccb7f	364	&anubis_device_sm501,
7efb833d BD	365	};
7efb833d BD	366
7a28db61 BD	367	/* I2C devices. */
	368
	369	static struct i2c_board_info anubis_i2c_devs[] __initdata = {
	370	{
	371	I2C_BOARD_INFO("tps65011", 0x48),
	372	.irq = IRQ_EINT20,
	373	}
	374	};
	375
4d3a3469 BD	376	/* Audio setup */
	377	static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
	378	.have_mic = 1,
	379	.have_lout = 1,
	380	.output_cdclk = 1,
	381	.use_mpllin = 1,
	382	.amp_gpio = S3C2410_GPB(2),
	383	.amp_gain[0] = S3C2410_GPD(10),
	384	.amp_gain[1] = S3C2410_GPD(11),
	385	};
	386
5fe10ab1	387	static void __init anubis_map_io(void)
7efb833d	388	{
7efb833d	389	s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
7efb833d	390	s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
7f78b6eb	391	samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
7efb833d	392
ad3613f4 BD	393	/* check for the newer revision boards with large page nand */
	394
	395	if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
	396	printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
	397	__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
	398	anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
	399	anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
	400	} else {
	401	/* ensure that the GPIO is setup */
42aa322c SN	402	gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
42aa322c SN	403	gpio_free(S3C2410_GPA(0));
ad3613f4	404	}
7efb833d BD	405	}
7efb833d BD	406
a28d618e HS	407	static void __init anubis_init_time(void)
	408	{
	409	s3c2440_init_clocks(12000000);
	410	samsung_timer_init();
	411	}
	412
57e5171c BD	413	static void __init anubis_init(void)
57e5171c BD	414	{
3e1b776c	415	s3c_i2c0_set_platdata(NULL);
2a3a1804	416	s3c_nand_set_platdata(&anubis_nand_info);
4d3a3469	417	simtec_audio_add(NULL, false, &anubis_audio);
2a3a1804	418
57e5171c	419	platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
7a28db61 BD	420
	421	i2c_register_board_info(0, anubis_i2c_devs,
	422	ARRAY_SIZE(anubis_i2c_devs));
57e5171c BD	423	}
	424
	425
7efb833d BD	426	MACHINE_START(ANUBIS, "Simtec-Anubis")
7efb833d BD	427	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
69d50710	428	.atag_offset = 0x100,
7efb833d	429	.map_io = anubis_map_io,
57e5171c	430	.init_machine = anubis_init,
ce6c164b	431	.init_irq = s3c2440_init_irq,
a28d618e	432	.init_time = anubis_init_time,
7efb833d	433	MACHINE_END