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1da177e4 LT |
1 | /* linux/arch/arm/mach-s3c2410/mach-bast.c |
2 | * | |
ccae941e | 3 | * Copyright 2003-2008 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * http://www.simtec.co.uk/products/EB2410ITX/ | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
1da177e4 LT |
11 | */ |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/init.h> | |
ec976d6e | 19 | #include <linux/gpio.h> |
bb072c3c | 20 | #include <linux/syscore_ops.h> |
b6d1f542 | 21 | #include <linux/serial_core.h> |
d052d1be | 22 | #include <linux/platform_device.h> |
d97a666f | 23 | #include <linux/dm9000.h> |
b7a12d19 | 24 | #include <linux/ata_platform.h> |
042cf0f2 | 25 | #include <linux/i2c.h> |
fced80c7 | 26 | #include <linux/io.h> |
bbd7e5e1 KK |
27 | #include <linux/serial_8250.h> |
28 | ||
29 | #include <linux/mtd/mtd.h> | |
30 | #include <linux/mtd/nand.h> | |
31 | #include <linux/mtd/nand_ecc.h> | |
32 | #include <linux/mtd/partitions.h> | |
33 | ||
34 | #include <linux/platform_data/asoc-s3c24xx_simtec.h> | |
35 | #include <linux/platform_data/hwmon-s3c.h> | |
36 | #include <linux/platform_data/i2c-s3c2410.h> | |
37 | #include <linux/platform_data/mtd-nand-s3c2410.h> | |
c67d0f29 | 38 | #include <linux/platform_data/gpio-samsung-s3c24xx.h> |
1da177e4 | 39 | |
5ce4b1fe BD |
40 | #include <net/ax88796.h> |
41 | ||
bbd7e5e1 | 42 | #include <asm/irq.h> |
1da177e4 LT |
43 | #include <asm/mach/arch.h> |
44 | #include <asm/mach/map.h> | |
45 | #include <asm/mach/irq.h> | |
1da177e4 LT |
46 | #include <asm/mach-types.h> |
47 | ||
bbd7e5e1 KK |
48 | #include <mach/fb.h> |
49 | #include <mach/hardware.h> | |
a09e64fb | 50 | #include <mach/regs-gpio.h> |
a09e64fb | 51 | #include <mach/regs-lcd.h> |
65cc3370 | 52 | |
d5120ae7 | 53 | #include <plat/clock.h> |
a2b7ba9c | 54 | #include <plat/cpu.h> |
ca0b4901 | 55 | #include <plat/cpu-freq.h> |
bbd7e5e1 | 56 | #include <plat/devs.h> |
40b956f0 | 57 | #include <plat/gpio-cfg.h> |
bbd7e5e1 | 58 | #include <plat/regs-serial.h> |
7f78b6eb | 59 | #include <plat/samsung-time.h> |
9d529c6e | 60 | |
bbd7e5e1 | 61 | #include "bast.h" |
b27b0727 | 62 | #include "common.h" |
bbd7e5e1 | 63 | #include "simtec.h" |
1da177e4 | 64 | |
ccae941e | 65 | #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics" |
1da177e4 LT |
66 | |
67 | /* macros for virtual address mods for the io space entries */ | |
68 | #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5) | |
69 | #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4) | |
70 | #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3) | |
71 | #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2) | |
72 | ||
73 | /* macros to modify the physical addresses for io space */ | |
74 | ||
1d23b65d BD |
75 | #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2)) |
76 | #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3)) | |
77 | #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4)) | |
78 | #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5)) | |
1da177e4 LT |
79 | |
80 | static struct map_desc bast_iodesc[] __initdata = { | |
81 | /* ISA IO areas */ | |
1d23b65d BD |
82 | { |
83 | .virtual = (u32)S3C24XX_VA_ISA_BYTE, | |
84 | .pfn = PA_CS2(BAST_PA_ISAIO), | |
85 | .length = SZ_16M, | |
86 | .type = MT_DEVICE, | |
87 | }, { | |
88 | .virtual = (u32)S3C24XX_VA_ISA_WORD, | |
89 | .pfn = PA_CS3(BAST_PA_ISAIO), | |
90 | .length = SZ_16M, | |
91 | .type = MT_DEVICE, | |
92 | }, | |
1da177e4 | 93 | /* bast CPLD control registers, and external interrupt controls */ |
1d23b65d BD |
94 | { |
95 | .virtual = (u32)BAST_VA_CTRL1, | |
96 | .pfn = __phys_to_pfn(BAST_PA_CTRL1), | |
97 | .length = SZ_1M, | |
98 | .type = MT_DEVICE, | |
99 | }, { | |
100 | .virtual = (u32)BAST_VA_CTRL2, | |
101 | .pfn = __phys_to_pfn(BAST_PA_CTRL2), | |
102 | .length = SZ_1M, | |
103 | .type = MT_DEVICE, | |
104 | }, { | |
105 | .virtual = (u32)BAST_VA_CTRL3, | |
106 | .pfn = __phys_to_pfn(BAST_PA_CTRL3), | |
107 | .length = SZ_1M, | |
108 | .type = MT_DEVICE, | |
109 | }, { | |
110 | .virtual = (u32)BAST_VA_CTRL4, | |
111 | .pfn = __phys_to_pfn(BAST_PA_CTRL4), | |
112 | .length = SZ_1M, | |
113 | .type = MT_DEVICE, | |
114 | }, | |
1da177e4 | 115 | /* PC104 IRQ mux */ |
1d23b65d BD |
116 | { |
117 | .virtual = (u32)BAST_VA_PC104_IRQREQ, | |
118 | .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ), | |
119 | .length = SZ_1M, | |
120 | .type = MT_DEVICE, | |
121 | }, { | |
122 | .virtual = (u32)BAST_VA_PC104_IRQRAW, | |
123 | .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW), | |
124 | .length = SZ_1M, | |
125 | .type = MT_DEVICE, | |
126 | }, { | |
127 | .virtual = (u32)BAST_VA_PC104_IRQMASK, | |
128 | .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK), | |
129 | .length = SZ_1M, | |
130 | .type = MT_DEVICE, | |
131 | }, | |
1da177e4 LT |
132 | |
133 | /* peripheral space... one for each of fast/slow/byte/16bit */ | |
134 | /* note, ide is only decoded in word space, even though some registers | |
135 | * are only 8bit */ | |
136 | ||
137 | /* slow, byte */ | |
138 | { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
139 | { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, | |
1da177e4 | 140 | { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, |
1da177e4 LT |
141 | |
142 | /* slow, word */ | |
143 | { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
144 | { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, | |
1da177e4 | 145 | { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, |
1da177e4 LT |
146 | |
147 | /* fast, byte */ | |
148 | { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
149 | { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, | |
1da177e4 | 150 | { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, |
1da177e4 LT |
151 | |
152 | /* fast, word */ | |
153 | { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, | |
154 | { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, | |
1da177e4 | 155 | { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, |
1da177e4 LT |
156 | }; |
157 | ||
158 | #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK | |
159 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | |
160 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE | |
161 | ||
66a9b49a | 162 | static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { |
1da177e4 LT |
163 | [0] = { |
164 | .hwport = 0, | |
165 | .flags = 0, | |
166 | .ucon = UCON, | |
167 | .ulcon = ULCON, | |
168 | .ufcon = UFCON, | |
1da177e4 LT |
169 | }, |
170 | [1] = { | |
171 | .hwport = 1, | |
172 | .flags = 0, | |
173 | .ucon = UCON, | |
174 | .ulcon = ULCON, | |
175 | .ufcon = UFCON, | |
1da177e4 LT |
176 | }, |
177 | /* port 2 is not actually used */ | |
178 | [2] = { | |
179 | .hwport = 2, | |
180 | .flags = 0, | |
181 | .ucon = UCON, | |
182 | .ulcon = ULCON, | |
183 | .ufcon = UFCON, | |
1da177e4 LT |
184 | } |
185 | }; | |
186 | ||
1da177e4 LT |
187 | /* NAND Flash on BAST board */ |
188 | ||
6ddc4b07 | 189 | #ifdef CONFIG_PM |
bb072c3c | 190 | static int bast_pm_suspend(void) |
6ddc4b07 BD |
191 | { |
192 | /* ensure that an nRESET is not generated on resume. */ | |
408c8b8c | 193 | gpio_direction_output(S3C2410_GPA(21), 1); |
6ddc4b07 BD |
194 | return 0; |
195 | } | |
196 | ||
bb072c3c | 197 | static void bast_pm_resume(void) |
6ddc4b07 | 198 | { |
40b956f0 | 199 | s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); |
6ddc4b07 BD |
200 | } |
201 | ||
202 | #else | |
203 | #define bast_pm_suspend NULL | |
204 | #define bast_pm_resume NULL | |
205 | #endif | |
206 | ||
bb072c3c | 207 | static struct syscore_ops bast_pm_syscore_ops = { |
6ddc4b07 BD |
208 | .suspend = bast_pm_suspend, |
209 | .resume = bast_pm_resume, | |
210 | }; | |
211 | ||
1da177e4 LT |
212 | static int smartmedia_map[] = { 0 }; |
213 | static int chip0_map[] = { 1 }; | |
214 | static int chip1_map[] = { 2 }; | |
215 | static int chip2_map[] = { 3 }; | |
216 | ||
2a3a1804 | 217 | static struct mtd_partition __initdata bast_default_nand_part[] = { |
1da177e4 LT |
218 | [0] = { |
219 | .name = "Boot Agent", | |
220 | .size = SZ_16K, | |
b526bf23 | 221 | .offset = 0, |
1da177e4 LT |
222 | }, |
223 | [1] = { | |
224 | .name = "/boot", | |
225 | .size = SZ_4M - SZ_16K, | |
226 | .offset = SZ_16K, | |
227 | }, | |
228 | [2] = { | |
229 | .name = "user", | |
230 | .offset = SZ_4M, | |
231 | .size = MTDPART_SIZ_FULL, | |
232 | } | |
233 | }; | |
234 | ||
235 | /* the bast has 4 selectable slots for nand-flash, the three | |
236 | * on-board chip areas, as well as the external SmartMedia | |
237 | * slot. | |
238 | * | |
239 | * Note, there is no current hot-plug support for the SmartMedia | |
240 | * socket. | |
241 | */ | |
242 | ||
2a3a1804 | 243 | static struct s3c2410_nand_set __initdata bast_nand_sets[] = { |
1da177e4 LT |
244 | [0] = { |
245 | .name = "SmartMedia", | |
246 | .nr_chips = 1, | |
247 | .nr_map = smartmedia_map, | |
d3ef7ee4 | 248 | .options = NAND_SCAN_SILENT_NODEV, |
1da177e4 | 249 | .nr_partitions = ARRAY_SIZE(bast_default_nand_part), |
b526bf23 | 250 | .partitions = bast_default_nand_part, |
1da177e4 LT |
251 | }, |
252 | [1] = { | |
253 | .name = "chip0", | |
254 | .nr_chips = 1, | |
255 | .nr_map = chip0_map, | |
256 | .nr_partitions = ARRAY_SIZE(bast_default_nand_part), | |
b526bf23 | 257 | .partitions = bast_default_nand_part, |
1da177e4 LT |
258 | }, |
259 | [2] = { | |
260 | .name = "chip1", | |
261 | .nr_chips = 1, | |
262 | .nr_map = chip1_map, | |
d3ef7ee4 | 263 | .options = NAND_SCAN_SILENT_NODEV, |
1da177e4 | 264 | .nr_partitions = ARRAY_SIZE(bast_default_nand_part), |
b526bf23 | 265 | .partitions = bast_default_nand_part, |
1da177e4 LT |
266 | }, |
267 | [3] = { | |
268 | .name = "chip2", | |
269 | .nr_chips = 1, | |
270 | .nr_map = chip2_map, | |
d3ef7ee4 | 271 | .options = NAND_SCAN_SILENT_NODEV, |
1da177e4 | 272 | .nr_partitions = ARRAY_SIZE(bast_default_nand_part), |
b526bf23 | 273 | .partitions = bast_default_nand_part, |
1da177e4 LT |
274 | } |
275 | }; | |
276 | ||
277 | static void bast_nand_select(struct s3c2410_nand_set *set, int slot) | |
278 | { | |
279 | unsigned int tmp; | |
280 | ||
281 | slot = set->nr_map[slot] & 3; | |
282 | ||
283 | pr_debug("bast_nand: selecting slot %d (set %p,%p)\n", | |
284 | slot, set, set->nr_map); | |
285 | ||
286 | tmp = __raw_readb(BAST_VA_CTRL2); | |
287 | tmp &= BAST_CPLD_CTLR2_IDERST; | |
288 | tmp |= slot; | |
289 | tmp |= BAST_CPLD_CTRL2_WNAND; | |
290 | ||
291 | pr_debug("bast_nand: ctrl2 now %02x\n", tmp); | |
292 | ||
293 | __raw_writeb(tmp, BAST_VA_CTRL2); | |
294 | } | |
295 | ||
2a3a1804 | 296 | static struct s3c2410_platform_nand __initdata bast_nand_info = { |
b048dbf4 BD |
297 | .tacls = 30, |
298 | .twrph0 = 60, | |
299 | .twrph1 = 60, | |
1da177e4 LT |
300 | .nr_sets = ARRAY_SIZE(bast_nand_sets), |
301 | .sets = bast_nand_sets, | |
302 | .select_chip = bast_nand_select, | |
303 | }; | |
304 | ||
d97a666f BD |
305 | /* DM9000 */ |
306 | ||
307 | static struct resource bast_dm9k_resource[] = { | |
52df44d1 TB |
308 | [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4), |
309 | [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40), | |
bbd7e5e1 | 310 | [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \ |
52df44d1 | 311 | | IORESOURCE_IRQ_HIGHLEVEL), |
d97a666f BD |
312 | }; |
313 | ||
314 | /* for the moment we limit ourselves to 16bit IO until some | |
315 | * better IO routines can be written and tested | |
316 | */ | |
317 | ||
9f693d7b | 318 | static struct dm9000_plat_data bast_dm9k_platdata = { |
b526bf23 | 319 | .flags = DM9000_PLATF_16BITONLY, |
d97a666f BD |
320 | }; |
321 | ||
322 | static struct platform_device bast_device_dm9k = { | |
323 | .name = "dm9000", | |
324 | .id = 0, | |
325 | .num_resources = ARRAY_SIZE(bast_dm9k_resource), | |
326 | .resource = bast_dm9k_resource, | |
327 | .dev = { | |
328 | .platform_data = &bast_dm9k_platdata, | |
329 | } | |
330 | }; | |
331 | ||
65cc3370 BD |
332 | /* serial devices */ |
333 | ||
334 | #define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO) | |
335 | #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ) | |
336 | #define SERIAL_CLK (1843200) | |
337 | ||
338 | static struct plat_serial8250_port bast_sio_data[] = { | |
339 | [0] = { | |
340 | .mapbase = SERIAL_BASE + 0x2f8, | |
bbd7e5e1 | 341 | .irq = BAST_IRQ_PCSERIAL1, |
65cc3370 BD |
342 | .flags = SERIAL_FLAGS, |
343 | .iotype = UPIO_MEM, | |
344 | .regshift = 0, | |
345 | .uartclk = SERIAL_CLK, | |
346 | }, | |
347 | [1] = { | |
348 | .mapbase = SERIAL_BASE + 0x3f8, | |
bbd7e5e1 | 349 | .irq = BAST_IRQ_PCSERIAL2, |
65cc3370 BD |
350 | .flags = SERIAL_FLAGS, |
351 | .iotype = UPIO_MEM, | |
352 | .regshift = 0, | |
353 | .uartclk = SERIAL_CLK, | |
354 | }, | |
355 | { } | |
356 | }; | |
357 | ||
358 | static struct platform_device bast_sio = { | |
359 | .name = "serial8250", | |
6df29deb | 360 | .id = PLAT8250_DEV_PLATFORM, |
65cc3370 BD |
361 | .dev = { |
362 | .platform_data = &bast_sio_data, | |
363 | }, | |
364 | }; | |
1da177e4 | 365 | |
1fcf8448 BD |
366 | /* we have devices on the bus which cannot work much over the |
367 | * standard 100KHz i2c bus frequency | |
368 | */ | |
369 | ||
3e1b776c | 370 | static struct s3c2410_platform_i2c __initdata bast_i2c_info = { |
1fcf8448 BD |
371 | .flags = 0, |
372 | .slave_addr = 0x10, | |
c564e6ae | 373 | .frequency = 100*1000, |
1fcf8448 BD |
374 | }; |
375 | ||
5ce4b1fe BD |
376 | /* Asix AX88796 10/100 ethernet controller */ |
377 | ||
378 | static struct ax_plat_data bast_asix_platdata = { | |
379 | .flags = AXFLG_MAC_FROMDEV, | |
380 | .wordlength = 2, | |
381 | .dcr_val = 0x48, | |
382 | .rcr_val = 0x40, | |
383 | }; | |
384 | ||
385 | static struct resource bast_asix_resource[] = { | |
52df44d1 TB |
386 | [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20), |
387 | [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1), | |
bbd7e5e1 | 388 | [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX), |
5ce4b1fe BD |
389 | }; |
390 | ||
391 | static struct platform_device bast_device_asix = { | |
392 | .name = "ax88796", | |
393 | .id = 0, | |
394 | .num_resources = ARRAY_SIZE(bast_asix_resource), | |
395 | .resource = bast_asix_resource, | |
396 | .dev = { | |
397 | .platform_data = &bast_asix_platdata | |
398 | } | |
399 | }; | |
400 | ||
401 | /* Asix AX88796 10/100 ethernet controller parallel port */ | |
402 | ||
403 | static struct resource bast_asixpp_resource[] = { | |
52df44d1 TB |
404 | [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \ |
405 | 0x30 * 0x20), | |
5ce4b1fe BD |
406 | }; |
407 | ||
408 | static struct platform_device bast_device_axpp = { | |
409 | .name = "ax88796-pp", | |
410 | .id = 0, | |
411 | .num_resources = ARRAY_SIZE(bast_asixpp_resource), | |
412 | .resource = bast_asixpp_resource, | |
413 | }; | |
414 | ||
415 | /* LCD/VGA controller */ | |
58c8d570 | 416 | |
09fe75f6 KH |
417 | static struct s3c2410fb_display __initdata bast_lcd_info[] = { |
418 | { | |
1f411537 | 419 | .type = S3C2410_LCDCON1_TFT, |
09fe75f6 KH |
420 | .width = 640, |
421 | .height = 480, | |
5f20f69b | 422 | |
69816699 | 423 | .pixclock = 33333, |
09fe75f6 KH |
424 | .xres = 640, |
425 | .yres = 480, | |
426 | .bpp = 4, | |
1f411537 KH |
427 | .left_margin = 40, |
428 | .right_margin = 20, | |
93d11f5a | 429 | .hsync_len = 88, |
5f20f69b KH |
430 | .upper_margin = 30, |
431 | .lower_margin = 32, | |
93d11f5a | 432 | .vsync_len = 3, |
09fe75f6 | 433 | |
f28ef573 | 434 | .lcdcon5 = 0x00014b02, |
58c8d570 | 435 | }, |
09fe75f6 | 436 | { |
1f411537 | 437 | .type = S3C2410_LCDCON1_TFT, |
09fe75f6 KH |
438 | .width = 640, |
439 | .height = 480, | |
440 | ||
69816699 | 441 | .pixclock = 33333, |
09fe75f6 KH |
442 | .xres = 640, |
443 | .yres = 480, | |
444 | .bpp = 8, | |
1f411537 KH |
445 | .left_margin = 40, |
446 | .right_margin = 20, | |
93d11f5a | 447 | .hsync_len = 88, |
5f20f69b KH |
448 | .upper_margin = 30, |
449 | .lower_margin = 32, | |
93d11f5a | 450 | .vsync_len = 3, |
09fe75f6 | 451 | |
f28ef573 | 452 | .lcdcon5 = 0x00014b02, |
09fe75f6 KH |
453 | }, |
454 | { | |
1f411537 | 455 | .type = S3C2410_LCDCON1_TFT, |
09fe75f6 KH |
456 | .width = 640, |
457 | .height = 480, | |
458 | ||
69816699 | 459 | .pixclock = 33333, |
09fe75f6 KH |
460 | .xres = 640, |
461 | .yres = 480, | |
462 | .bpp = 16, | |
1f411537 KH |
463 | .left_margin = 40, |
464 | .right_margin = 20, | |
93d11f5a | 465 | .hsync_len = 88, |
5f20f69b KH |
466 | .upper_margin = 30, |
467 | .lower_margin = 32, | |
93d11f5a | 468 | .vsync_len = 3, |
09fe75f6 | 469 | |
f28ef573 | 470 | .lcdcon5 = 0x00014b02, |
09fe75f6 KH |
471 | }, |
472 | }; | |
58c8d570 | 473 | |
09fe75f6 KH |
474 | /* LCD/VGA controller */ |
475 | ||
476 | static struct s3c2410fb_mach_info __initdata bast_fb_info = { | |
477 | ||
478 | .displays = bast_lcd_info, | |
479 | .num_displays = ARRAY_SIZE(bast_lcd_info), | |
9cbae12c | 480 | .default_display = 1, |
58c8d570 BD |
481 | }; |
482 | ||
042cf0f2 BD |
483 | /* I2C devices fitted. */ |
484 | ||
485 | static struct i2c_board_info bast_i2c_devs[] __initdata = { | |
486 | { | |
487 | I2C_BOARD_INFO("tlv320aic23", 0x1a), | |
488 | }, { | |
489 | I2C_BOARD_INFO("simtec-pmu", 0x6b), | |
490 | }, { | |
491 | I2C_BOARD_INFO("ch7013", 0x75), | |
492 | }, | |
493 | }; | |
b7a12d19 | 494 | |
885f9ebe BD |
495 | static struct s3c_hwmon_pdata bast_hwmon_info = { |
496 | /* LCD contrast (0-6.6V) */ | |
497 | .in[0] = &(struct s3c_hwmon_chcfg) { | |
498 | .name = "lcd-contrast", | |
499 | .mult = 3300, | |
500 | .div = 512, | |
501 | }, | |
502 | /* LED current feedback */ | |
503 | .in[1] = &(struct s3c_hwmon_chcfg) { | |
504 | .name = "led-feedback", | |
505 | .mult = 3300, | |
506 | .div = 1024, | |
507 | }, | |
508 | /* LCD feedback (0-6.6V) */ | |
509 | .in[2] = &(struct s3c_hwmon_chcfg) { | |
510 | .name = "lcd-feedback", | |
511 | .mult = 3300, | |
512 | .div = 512, | |
513 | }, | |
514 | /* Vcore (1.8-2.0V), Vref 3.3V */ | |
515 | .in[3] = &(struct s3c_hwmon_chcfg) { | |
516 | .name = "vcore", | |
517 | .mult = 3300, | |
518 | .div = 1024, | |
519 | }, | |
520 | }; | |
521 | ||
1da177e4 | 522 | /* Standard BAST devices */ |
885f9ebe | 523 | // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0 |
1da177e4 LT |
524 | |
525 | static struct platform_device *bast_devices[] __initdata = { | |
b813248c | 526 | &s3c_device_ohci, |
1da177e4 LT |
527 | &s3c_device_lcd, |
528 | &s3c_device_wdt, | |
3e1b776c | 529 | &s3c_device_i2c0, |
1da177e4 LT |
530 | &s3c_device_rtc, |
531 | &s3c_device_nand, | |
885f9ebe BD |
532 | &s3c_device_adc, |
533 | &s3c_device_hwmon, | |
d97a666f | 534 | &bast_device_dm9k, |
5ce4b1fe BD |
535 | &bast_device_asix, |
536 | &bast_device_axpp, | |
65cc3370 | 537 | &bast_sio, |
1da177e4 LT |
538 | }; |
539 | ||
2bc7509f | 540 | static struct clk *bast_clocks[] __initdata = { |
1da177e4 LT |
541 | &s3c24xx_dclk0, |
542 | &s3c24xx_dclk1, | |
543 | &s3c24xx_clkout0, | |
544 | &s3c24xx_clkout1, | |
545 | &s3c24xx_uclk, | |
546 | }; | |
547 | ||
ca0b4901 BD |
548 | static struct s3c_cpufreq_board __initdata bast_cpufreq = { |
549 | .refresh = 7800, /* 7.8usec */ | |
550 | .auto_io = 1, | |
551 | .need_io = 1, | |
552 | }; | |
553 | ||
4d3a3469 BD |
554 | static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = { |
555 | .have_mic = 1, | |
556 | .have_lout = 1, | |
557 | }; | |
558 | ||
5fe10ab1 | 559 | static void __init bast_map_io(void) |
1da177e4 LT |
560 | { |
561 | /* initialise the clocks */ | |
562 | ||
d96a9804 | 563 | s3c24xx_dclk0.parent = &clk_upll; |
1da177e4 LT |
564 | s3c24xx_dclk0.rate = 12*1000*1000; |
565 | ||
d96a9804 | 566 | s3c24xx_dclk1.parent = &clk_upll; |
1da177e4 LT |
567 | s3c24xx_dclk1.rate = 24*1000*1000; |
568 | ||
569 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; | |
570 | s3c24xx_clkout1.parent = &s3c24xx_dclk1; | |
571 | ||
572 | s3c24xx_uclk.parent = &s3c24xx_clkout1; | |
573 | ||
ce89c206 BD |
574 | s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); |
575 | ||
6cd82ffe | 576 | s3c_hwmon_set_platdata(&bast_hwmon_info); |
3e1b776c | 577 | |
1da177e4 LT |
578 | s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); |
579 | s3c24xx_init_clocks(0); | |
580 | s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); | |
7f78b6eb | 581 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); |
1da177e4 LT |
582 | } |
583 | ||
58c8d570 BD |
584 | static void __init bast_init(void) |
585 | { | |
bb072c3c | 586 | register_syscore_ops(&bast_pm_syscore_ops); |
6ddc4b07 | 587 | |
a8af6de0 | 588 | s3c_i2c0_set_platdata(&bast_i2c_info); |
2a3a1804 | 589 | s3c_nand_set_platdata(&bast_nand_info); |
09fe75f6 | 590 | s3c24xx_fb_set_platdata(&bast_fb_info); |
57e5171c | 591 | platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices)); |
9d529c6e | 592 | |
042cf0f2 BD |
593 | i2c_register_board_info(0, bast_i2c_devs, |
594 | ARRAY_SIZE(bast_i2c_devs)); | |
595 | ||
7a05a2cb | 596 | usb_simtec_init(); |
9d529c6e | 597 | nor_simtec_init(); |
4d3a3469 | 598 | simtec_audio_add(NULL, true, &bast_audio); |
ca0b4901 | 599 | |
408c8b8c BD |
600 | WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset")); |
601 | ||
ca0b4901 | 602 | s3c_cpufreq_setboard(&bast_cpufreq); |
58c8d570 | 603 | } |
1da177e4 LT |
604 | |
605 | MACHINE_START(BAST, "Simtec-BAST") | |
e9dea0c6 | 606 | /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ |
69d50710 | 607 | .atag_offset = 0x100, |
f705b1ae | 608 | .map_io = bast_map_io, |
f182aa1d | 609 | .init_irq = s3c2410_init_irq, |
58c8d570 | 610 | .init_machine = bast_init, |
7f78b6eb | 611 | .init_time = samsung_timer_init, |
b27b0727 | 612 | .restart = s3c2410_restart, |
1da177e4 | 613 | MACHINE_END |