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Commit | Line | Data |
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b024043b KK |
1 | /* |
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
80789e79 BD |
4 | * |
5 | * Copyright 2008 Openmoko, Inc. | |
6 | * Copyright 2008 Simtec Electronics | |
b024043b KK |
7 | * Ben Dooks <ben@simtec.co.uk> |
8 | * http://armlinux.simtec.co.uk/ | |
80789e79 | 9 | * |
b024043b | 10 | * Common Codes for S3C64XX machines |
80789e79 BD |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
c836c90e TF |
17 | /* |
18 | * NOTE: Code in this file is not used when booting with Device Tree support. | |
19 | */ | |
20 | ||
80789e79 | 21 | #include <linux/kernel.h> |
b024043b KK |
22 | #include <linux/init.h> |
23 | #include <linux/module.h> | |
80789e79 | 24 | #include <linux/interrupt.h> |
b024043b | 25 | #include <linux/ioport.h> |
b024043b | 26 | #include <linux/serial_core.h> |
334a1c70 | 27 | #include <linux/serial_s3c.h> |
b024043b | 28 | #include <linux/platform_device.h> |
7b6d864b | 29 | #include <linux/reboot.h> |
80789e79 | 30 | #include <linux/io.h> |
b024043b KK |
31 | #include <linux/dma-mapping.h> |
32 | #include <linux/irq.h> | |
33 | #include <linux/gpio.h> | |
9e47b8bf | 34 | #include <linux/irqchip/arm-vic.h> |
1c161fd0 | 35 | #include <clocksource/samsung_pwm.h> |
80789e79 | 36 | |
b024043b KK |
37 | #include <asm/mach/arch.h> |
38 | #include <asm/mach/map.h> | |
9f97da78 | 39 | #include <asm/system_misc.h> |
80789e79 | 40 | |
b024043b KK |
41 | #include <mach/map.h> |
42 | #include <mach/hardware.h> | |
3501c9ae | 43 | #include <mach/regs-gpio.h> |
b0161caa | 44 | #include <mach/gpio-samsung.h> |
80789e79 | 45 | |
80789e79 | 46 | #include <plat/cpu.h> |
b024043b | 47 | #include <plat/devs.h> |
bd117bd1 | 48 | #include <plat/pm.h> |
b024043b | 49 | #include <plat/gpio-cfg.h> |
1c161fd0 | 50 | #include <plat/pwm-core.h> |
b024043b | 51 | #include <plat/regs-irqtype.h> |
b024043b KK |
52 | |
53 | #include "common.h" | |
876ba9ba | 54 | #include "irq-uart.h" |
96bc024c | 55 | #include "watchdog-reset.h" |
b024043b | 56 | |
b69f460d TF |
57 | /* External clock frequency */ |
58 | static unsigned long xtal_f = 12000000, xusbxti_f = 48000000; | |
59 | ||
60 | void __init s3c64xx_set_xtal_freq(unsigned long freq) | |
61 | { | |
62 | xtal_f = freq; | |
63 | } | |
64 | ||
65 | void __init s3c64xx_set_xusbxti_freq(unsigned long freq) | |
66 | { | |
67 | xusbxti_f = freq; | |
68 | } | |
69 | ||
b024043b KK |
70 | /* uart registration process */ |
71 | ||
b7c9705c | 72 | static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) |
b024043b KK |
73 | { |
74 | s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); | |
75 | } | |
76 | ||
77 | /* table of supported CPUs */ | |
78 | ||
79 | static const char name_s3c6400[] = "S3C6400"; | |
80 | static const char name_s3c6410[] = "S3C6410"; | |
81 | ||
82 | static struct cpu_table cpu_ids[] __initdata = { | |
83 | { | |
84 | .idcode = S3C6400_CPU_ID, | |
85 | .idmask = S3C64XX_CPU_MASK, | |
86 | .map_io = s3c6400_map_io, | |
b024043b KK |
87 | .init_uarts = s3c64xx_init_uarts, |
88 | .init = s3c6400_init, | |
89 | .name = name_s3c6400, | |
90 | }, { | |
91 | .idcode = S3C6410_CPU_ID, | |
92 | .idmask = S3C64XX_CPU_MASK, | |
93 | .map_io = s3c6410_map_io, | |
b024043b KK |
94 | .init_uarts = s3c64xx_init_uarts, |
95 | .init = s3c6410_init, | |
96 | .name = name_s3c6410, | |
97 | }, | |
98 | }; | |
99 | ||
100 | /* minimal IO mapping */ | |
101 | ||
102 | /* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */ | |
103 | #define UART_OFFS (S3C_PA_UART & 0xfffff) | |
104 | ||
105 | static struct map_desc s3c_iodesc[] __initdata = { | |
106 | { | |
107 | .virtual = (unsigned long)S3C_VA_SYS, | |
108 | .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON), | |
109 | .length = SZ_4K, | |
110 | .type = MT_DEVICE, | |
111 | }, { | |
112 | .virtual = (unsigned long)S3C_VA_MEM, | |
113 | .pfn = __phys_to_pfn(S3C64XX_PA_SROM), | |
114 | .length = SZ_4K, | |
115 | .type = MT_DEVICE, | |
116 | }, { | |
117 | .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS), | |
118 | .pfn = __phys_to_pfn(S3C_PA_UART), | |
119 | .length = SZ_4K, | |
120 | .type = MT_DEVICE, | |
121 | }, { | |
122 | .virtual = (unsigned long)VA_VIC0, | |
123 | .pfn = __phys_to_pfn(S3C64XX_PA_VIC0), | |
124 | .length = SZ_16K, | |
125 | .type = MT_DEVICE, | |
126 | }, { | |
127 | .virtual = (unsigned long)VA_VIC1, | |
128 | .pfn = __phys_to_pfn(S3C64XX_PA_VIC1), | |
129 | .length = SZ_16K, | |
130 | .type = MT_DEVICE, | |
131 | }, { | |
132 | .virtual = (unsigned long)S3C_VA_TIMER, | |
133 | .pfn = __phys_to_pfn(S3C_PA_TIMER), | |
134 | .length = SZ_16K, | |
135 | .type = MT_DEVICE, | |
136 | }, { | |
137 | .virtual = (unsigned long)S3C64XX_VA_GPIO, | |
138 | .pfn = __phys_to_pfn(S3C64XX_PA_GPIO), | |
139 | .length = SZ_4K, | |
140 | .type = MT_DEVICE, | |
141 | }, { | |
142 | .virtual = (unsigned long)S3C64XX_VA_MODEM, | |
143 | .pfn = __phys_to_pfn(S3C64XX_PA_MODEM), | |
144 | .length = SZ_4K, | |
145 | .type = MT_DEVICE, | |
146 | }, { | |
147 | .virtual = (unsigned long)S3C_VA_WATCHDOG, | |
148 | .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG), | |
149 | .length = SZ_4K, | |
150 | .type = MT_DEVICE, | |
151 | }, { | |
152 | .virtual = (unsigned long)S3C_VA_USB_HSPHY, | |
153 | .pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY), | |
154 | .length = SZ_1K, | |
155 | .type = MT_DEVICE, | |
156 | }, | |
157 | }; | |
158 | ||
7affca35 LT |
159 | static struct bus_type s3c64xx_subsys = { |
160 | .name = "s3c64xx-core", | |
161 | .dev_name = "s3c64xx-core", | |
b024043b KK |
162 | }; |
163 | ||
7affca35 LT |
164 | static struct device s3c64xx_dev = { |
165 | .bus = &s3c64xx_subsys, | |
b024043b KK |
166 | }; |
167 | ||
1c161fd0 TF |
168 | static struct samsung_pwm_variant s3c64xx_pwm_variant = { |
169 | .bits = 32, | |
170 | .div_base = 0, | |
171 | .has_tint_cstat = true, | |
172 | .tclk_mask = (1 << 7) | (1 << 6) | (1 << 5), | |
173 | }; | |
174 | ||
4280506a TF |
175 | void __init samsung_set_timer_source(unsigned int event, unsigned int source) |
176 | { | |
177 | s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; | |
178 | s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); | |
179 | } | |
180 | ||
181 | void __init samsung_timer_init(void) | |
182 | { | |
183 | unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { | |
184 | IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, | |
185 | IRQ_TIMER3_VIC, IRQ_TIMER4_VIC, | |
186 | }; | |
187 | ||
188 | samsung_pwm_clocksource_init(S3C_VA_TIMER, | |
189 | timer_irqs, &s3c64xx_pwm_variant); | |
190 | } | |
191 | ||
b024043b KK |
192 | /* read cpu identification code */ |
193 | ||
194 | void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) | |
195 | { | |
196 | /* initialise the io descriptors we need for initialisation */ | |
197 | iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); | |
198 | iotable_init(mach_desc, size); | |
b024043b KK |
199 | |
200 | /* detect cpu id */ | |
201 | s3c64xx_init_cpu(); | |
202 | ||
203 | s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); | |
1c161fd0 TF |
204 | |
205 | samsung_pwm_set_platdata(&s3c64xx_pwm_variant); | |
b024043b KK |
206 | } |
207 | ||
7affca35 | 208 | static __init int s3c64xx_dev_init(void) |
b024043b | 209 | { |
c836c90e TF |
210 | /* Not applicable when using DT. */ |
211 | if (of_have_populated_dt()) | |
212 | return 0; | |
213 | ||
7affca35 LT |
214 | subsys_system_register(&s3c64xx_subsys, NULL); |
215 | return device_register(&s3c64xx_dev); | |
b024043b | 216 | } |
7affca35 | 217 | core_initcall(s3c64xx_dev_init); |
b024043b KK |
218 | |
219 | /* | |
220 | * setup the sources the vic should advertise resume | |
221 | * for, even though it is not doing the wake | |
222 | * (set_irq_wake needs to be valid) | |
223 | */ | |
224 | #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE)) | |
225 | #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \ | |
226 | 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \ | |
227 | 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \ | |
228 | 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \ | |
229 | 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE)) | |
230 | ||
231 | void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) | |
232 | { | |
88f59738 TF |
233 | /* |
234 | * FIXME: there is no better place to put this at the moment | |
b69f460d TF |
235 | * (s3c64xx_clk_init needs ioremap and must happen before init_time |
236 | * samsung_wdt_reset_init needs clocks) | |
88f59738 | 237 | */ |
b69f460d | 238 | s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS); |
88f59738 TF |
239 | samsung_wdt_reset_init(S3C_VA_WATCHDOG); |
240 | ||
b024043b KK |
241 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); |
242 | ||
243 | /* initialise the pair of VICs */ | |
244 | vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME); | |
245 | vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME); | |
b024043b | 246 | } |
80789e79 | 247 | |
80789e79 | 248 | #define eint_offset(irq) ((irq) - IRQ_EINT(0)) |
3c916975 | 249 | #define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq))) |
80789e79 | 250 | |
c35cd6ec | 251 | static inline void s3c_irq_eint_mask(struct irq_data *data) |
80789e79 BD |
252 | { |
253 | u32 mask; | |
254 | ||
255 | mask = __raw_readl(S3C64XX_EINT0MASK); | |
3c916975 | 256 | mask |= (u32)data->chip_data; |
80789e79 BD |
257 | __raw_writel(mask, S3C64XX_EINT0MASK); |
258 | } | |
259 | ||
c35cd6ec | 260 | static void s3c_irq_eint_unmask(struct irq_data *data) |
80789e79 BD |
261 | { |
262 | u32 mask; | |
263 | ||
264 | mask = __raw_readl(S3C64XX_EINT0MASK); | |
3c916975 | 265 | mask &= ~((u32)data->chip_data); |
80789e79 BD |
266 | __raw_writel(mask, S3C64XX_EINT0MASK); |
267 | } | |
268 | ||
c35cd6ec | 269 | static inline void s3c_irq_eint_ack(struct irq_data *data) |
80789e79 | 270 | { |
3c916975 | 271 | __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND); |
80789e79 BD |
272 | } |
273 | ||
c35cd6ec | 274 | static void s3c_irq_eint_maskack(struct irq_data *data) |
80789e79 BD |
275 | { |
276 | /* compiler should in-line these */ | |
c35cd6ec MB |
277 | s3c_irq_eint_mask(data); |
278 | s3c_irq_eint_ack(data); | |
80789e79 BD |
279 | } |
280 | ||
c35cd6ec | 281 | static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type) |
80789e79 | 282 | { |
c35cd6ec | 283 | int offs = eint_offset(data->irq); |
6a88e983 | 284 | int pin, pin_val; |
80789e79 BD |
285 | int shift; |
286 | u32 ctrl, mask; | |
287 | u32 newvalue = 0; | |
288 | void __iomem *reg; | |
289 | ||
290 | if (offs > 27) | |
291 | return -EINVAL; | |
292 | ||
a9c5d23a | 293 | if (offs <= 15) |
80789e79 BD |
294 | reg = S3C64XX_EINT0CON0; |
295 | else | |
296 | reg = S3C64XX_EINT0CON1; | |
297 | ||
298 | switch (type) { | |
299 | case IRQ_TYPE_NONE: | |
300 | printk(KERN_WARNING "No edge setting!\n"); | |
301 | break; | |
302 | ||
303 | case IRQ_TYPE_EDGE_RISING: | |
304 | newvalue = S3C2410_EXTINT_RISEEDGE; | |
305 | break; | |
306 | ||
307 | case IRQ_TYPE_EDGE_FALLING: | |
308 | newvalue = S3C2410_EXTINT_FALLEDGE; | |
309 | break; | |
310 | ||
311 | case IRQ_TYPE_EDGE_BOTH: | |
312 | newvalue = S3C2410_EXTINT_BOTHEDGE; | |
313 | break; | |
314 | ||
315 | case IRQ_TYPE_LEVEL_LOW: | |
316 | newvalue = S3C2410_EXTINT_LOWLEV; | |
317 | break; | |
318 | ||
319 | case IRQ_TYPE_LEVEL_HIGH: | |
320 | newvalue = S3C2410_EXTINT_HILEV; | |
321 | break; | |
322 | ||
323 | default: | |
324 | printk(KERN_ERR "No such irq type %d", type); | |
325 | return -1; | |
326 | } | |
327 | ||
6a88e983 MC |
328 | if (offs <= 15) |
329 | shift = (offs / 2) * 4; | |
330 | else | |
331 | shift = ((offs - 16) / 2) * 4; | |
80789e79 BD |
332 | mask = 0x7 << shift; |
333 | ||
334 | ctrl = __raw_readl(reg); | |
335 | ctrl &= ~mask; | |
336 | ctrl |= newvalue << shift; | |
337 | __raw_writel(ctrl, reg); | |
338 | ||
28fd2d39 BD |
339 | /* set the GPIO pin appropriately */ |
340 | ||
6a88e983 | 341 | if (offs < 16) { |
28fd2d39 | 342 | pin = S3C64XX_GPN(offs); |
6a88e983 MC |
343 | pin_val = S3C_GPIO_SFN(2); |
344 | } else if (offs < 23) { | |
345 | pin = S3C64XX_GPL(offs + 8 - 16); | |
346 | pin_val = S3C_GPIO_SFN(3); | |
347 | } else { | |
28fd2d39 | 348 | pin = S3C64XX_GPM(offs - 23); |
6a88e983 MC |
349 | pin_val = S3C_GPIO_SFN(3); |
350 | } | |
28fd2d39 | 351 | |
6a88e983 | 352 | s3c_gpio_cfgpin(pin, pin_val); |
28fd2d39 | 353 | |
80789e79 BD |
354 | return 0; |
355 | } | |
356 | ||
357 | static struct irq_chip s3c_irq_eint = { | |
358 | .name = "s3c-eint", | |
c35cd6ec MB |
359 | .irq_mask = s3c_irq_eint_mask, |
360 | .irq_unmask = s3c_irq_eint_unmask, | |
361 | .irq_mask_ack = s3c_irq_eint_maskack, | |
362 | .irq_ack = s3c_irq_eint_ack, | |
363 | .irq_set_type = s3c_irq_eint_set_type, | |
f5aeffb7 | 364 | .irq_set_wake = s3c_irqext_wake, |
80789e79 BD |
365 | }; |
366 | ||
367 | /* s3c_irq_demux_eint | |
368 | * | |
369 | * This function demuxes the IRQ from the group0 external interrupts, | |
370 | * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into | |
371 | * the specific handlers s3c_irq_demux_eintX_Y. | |
372 | */ | |
373 | static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end) | |
374 | { | |
375 | u32 status = __raw_readl(S3C64XX_EINT0PEND); | |
376 | u32 mask = __raw_readl(S3C64XX_EINT0MASK); | |
377 | unsigned int irq; | |
378 | ||
379 | status &= ~mask; | |
380 | status >>= start; | |
381 | status &= (1 << (end - start + 1)) - 1; | |
382 | ||
383 | for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { | |
384 | if (status & 1) | |
385 | generic_handle_irq(irq); | |
386 | ||
387 | status >>= 1; | |
388 | } | |
389 | } | |
390 | ||
bd0b9ac4 | 391 | static void s3c_irq_demux_eint0_3(struct irq_desc *desc) |
80789e79 BD |
392 | { |
393 | s3c_irq_demux_eint(0, 3); | |
394 | } | |
395 | ||
bd0b9ac4 | 396 | static void s3c_irq_demux_eint4_11(struct irq_desc *desc) |
80789e79 BD |
397 | { |
398 | s3c_irq_demux_eint(4, 11); | |
399 | } | |
400 | ||
bd0b9ac4 | 401 | static void s3c_irq_demux_eint12_19(struct irq_desc *desc) |
80789e79 BD |
402 | { |
403 | s3c_irq_demux_eint(12, 19); | |
404 | } | |
405 | ||
bd0b9ac4 | 406 | static void s3c_irq_demux_eint20_27(struct irq_desc *desc) |
80789e79 BD |
407 | { |
408 | s3c_irq_demux_eint(20, 27); | |
409 | } | |
410 | ||
8bd8dbdf | 411 | static int __init s3c64xx_init_irq_eint(void) |
80789e79 BD |
412 | { |
413 | int irq; | |
414 | ||
c836c90e TF |
415 | /* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */ |
416 | if (of_have_populated_dt()) | |
417 | return -ENODEV; | |
418 | ||
80789e79 | 419 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { |
f38c02f3 | 420 | irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq); |
9323f261 | 421 | irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq)); |
e8d36d5d | 422 | irq_clear_status_flags(irq, IRQ_NOREQUEST); |
80789e79 BD |
423 | } |
424 | ||
6845664a TG |
425 | irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); |
426 | irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); | |
427 | irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); | |
428 | irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); | |
80789e79 BD |
429 | |
430 | return 0; | |
431 | } | |
80789e79 | 432 | arch_initcall(s3c64xx_init_irq_eint); |
ff84ded2 | 433 | |
7b6d864b | 434 | void s3c64xx_restart(enum reboot_mode mode, const char *cmd) |
ff84ded2 | 435 | { |
7b6d864b | 436 | if (mode != REBOOT_SOFT) |
88f59738 | 437 | samsung_wdt_reset(); |
ff84ded2 KK |
438 | |
439 | /* if all else fails, or mode was for soft, jump to 0 */ | |
440 | soft_restart(0); | |
441 | } |