[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-s3c64xx / mach-mini6410.c

/* linux/arch/arm/mach-s3c64xx/mach-mini6410.c
 *
 * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
*/

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/dm9000.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/serial_core.h>
#include <linux/types.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>

#include <mach/map.h>
#include <mach/regs-fb.h>
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
#include <mach/regs-srom.h>
#include <mach/s3c6410.h>

#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/fb.h>
#include <plat/nand.h>
#include <plat/regs-serial.h>
#include <video/platform_lcd.h>

#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)

static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
	[0] = {
		.hwport	= 0,
		.flags	= 0,
		.ucon	= UCON,
		.ulcon	= ULCON,
		.ufcon	= UFCON,
	},
	[1] = {
		.hwport	= 1,
		.flags	= 0,
		.ucon	= UCON,
		.ulcon	= ULCON,
		.ufcon	= UFCON,
	},
	[2] = {
		.hwport	= 2,
		.flags	= 0,
		.ucon	= UCON,
		.ulcon	= ULCON,
		.ufcon	= UFCON,
	},
	[3] = {
		.hwport	= 3,
		.flags	= 0,
		.ucon	= UCON,
		.ulcon	= ULCON,
		.ufcon	= UFCON,
	},
};

/* DM9000AEP 10/100 ethernet controller */

static struct resource mini6410_dm9k_resource[] = {
	[0] = {
		.start	= S3C64XX_PA_XM0CSN1,
		.end	= S3C64XX_PA_XM0CSN1 + 1,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start	= S3C64XX_PA_XM0CSN1 + 4,
		.end	= S3C64XX_PA_XM0CSN1 + 5,
		.flags	= IORESOURCE_MEM
	},
	[2] = {
		.start	= S3C_EINT(7),
		.end	= S3C_EINT(7),
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
	}
};

static struct dm9000_plat_data mini6410_dm9k_pdata = {
	.flags		= (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
};

static struct platform_device mini6410_device_eth = {
	.name		= "dm9000",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(mini6410_dm9k_resource),
	.resource	= mini6410_dm9k_resource,
	.dev		= {
		.platform_data	= &mini6410_dm9k_pdata,
	},
};

static struct mtd_partition mini6410_nand_part[] = {
	[0] = {
		.name	= "uboot",
		.size	= SZ_1M,
		.offset	= 0,
	},
	[1] = {
		.name	= "kernel",
		.size	= SZ_2M,
		.offset	= SZ_1M,
	},
	[2] = {
		.name	= "rootfs",
		.size	= MTDPART_SIZ_FULL,
		.offset	= SZ_1M + SZ_2M,
	},
};

static struct s3c2410_nand_set mini6410_nand_sets[] = {
	[0] = {
		.name		= "nand",
		.nr_chips	= 1,
		.nr_partitions	= ARRAY_SIZE(mini6410_nand_part),
		.partitions	= mini6410_nand_part,
	},
};

static struct s3c2410_platform_nand mini6410_nand_info = {
	.tacls		= 25,
	.twrph0		= 55,
	.twrph1		= 40,
	.nr_sets	= ARRAY_SIZE(mini6410_nand_sets),
	.sets		= mini6410_nand_sets,
};

static struct s3c_fb_pd_win mini6410_fb_win[] = {
	{
		.win_mode	= {	/* 4.3" 480x272 */
			.left_margin	= 3,
			.right_margin	= 2,
			.upper_margin	= 1,
			.lower_margin	= 1,
			.hsync_len	= 40,
			.vsync_len	= 1,
			.xres		= 480,
			.yres		= 272,
		},
		.max_bpp	= 32,
		.default_bpp	= 16,
	}, {
		.win_mode	= {	/* 7.0" 800x480 */
			.left_margin	= 8,
			.right_margin	= 13,
			.upper_margin	= 7,
			.lower_margin	= 5,
			.hsync_len	= 3,
			.vsync_len	= 1,
			.xres		= 800,
			.yres		= 480,
		},
		.max_bpp	= 32,
		.default_bpp	= 16,
	},
};

static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
	.win[0]		= &mini6410_fb_win[0],
	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};

static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
				   unsigned int power)
{
	if (power)
		gpio_direction_output(S3C64XX_GPE(0), 1);
	else
		gpio_direction_output(S3C64XX_GPE(0), 0);
}

static struct plat_lcd_data mini6410_lcd_power_data = {
	.set_power	= mini6410_lcd_power_set,
};

static struct platform_device mini6410_lcd_powerdev = {
	.name			= "platform-lcd",
	.dev.parent		= &s3c_device_fb.dev,
	.dev.platform_data	= &mini6410_lcd_power_data,
};

static struct platform_device *mini6410_devices[] __initdata = {
	&mini6410_device_eth,
	&s3c_device_hsmmc0,
	&s3c_device_hsmmc1,
	&s3c_device_ohci,
	&s3c_device_nand,
	&s3c_device_fb,
	&mini6410_lcd_powerdev,
};

static void __init mini6410_map_io(void)
{
	u32 tmp;

	s3c64xx_init_io(NULL, 0);
	s3c24xx_init_clocks(12000000);
	s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));

	/* set the LCD type */
	tmp = __raw_readl(S3C64XX_SPCON);
	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
	tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
	__raw_writel(tmp, S3C64XX_SPCON);

	/* remove the LCD bypass */
	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
	tmp &= ~MIFPCON_LCD_BYPASS;
	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
}

/*
 * mini6410_features string
 *
 * 0-9 LCD configuration
 *
 */
static char mini6410_features_str[12] __initdata = "0";

static int __init mini6410_features_setup(char *str)
{
	if (str)
		strlcpy(mini6410_features_str, str,
			sizeof(mini6410_features_str));
	return 1;
}

__setup("mini6410=", mini6410_features_setup);

#define FEATURE_SCREEN (1 << 0)

struct mini6410_features_t {
	int done;
	int lcd_index;
};

static void mini6410_parse_features(
		struct mini6410_features_t *features,
		const char *features_str)
{
	const char *fp = features_str;

	features->done = 0;
	features->lcd_index = 0;

	while (*fp) {
		char f = *fp++;

		switch (f) {
		case '0'...'9':	/* tft screen */
			if (features->done & FEATURE_SCREEN) {
				printk(KERN_INFO "MINI6410: '%c' ignored, "
					"screen type already set\n", f);
			} else {
				int li = f - '0';
				if (li >= ARRAY_SIZE(mini6410_fb_win))
					printk(KERN_INFO "MINI6410: '%c' out "
						"of range LCD mode\n", f);
				else {
					features->lcd_index = li;
				}
			}
			features->done |= FEATURE_SCREEN;
			break;
		}
	}
}

static void __init mini6410_machine_init(void)
{
	u32 cs1;
	struct mini6410_features_t features = { 0 };

	printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
			mini6410_features_str);

	/* Parse the feature string */
	mini6410_parse_features(&features, mini6410_features_str);

	mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index];

	printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
		mini6410_lcd_pdata.win[0]->win_mode.xres,
		mini6410_lcd_pdata.win[0]->win_mode.yres);

	s3c_nand_set_platdata(&mini6410_nand_info);
	s3c_fb_set_platdata(&mini6410_lcd_pdata);

	/* configure nCS1 width to 16 bits */

	cs1 = __raw_readl(S3C64XX_SROM_BW) &
		~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
	cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
		(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
		(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
			S3C64XX_SROM_BW__NCS1__SHIFT;
	__raw_writel(cs1, S3C64XX_SROM_BW);

	/* set timing for nCS1 suitable for ethernet chip */

	__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
		(6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
		(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
		(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
		(13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
		(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
		(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);

	gpio_request(S3C64XX_GPF(15), "LCD power");
	gpio_request(S3C64XX_GPE(0), "LCD power");

	platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
}

MACHINE_START(MINI6410, "MINI6410")
	/* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
	.boot_params	= S3C64XX_PA_SDRAM + 0x100,
	.init_irq	= s3c6410_init_irq,
	.map_io		= mini6410_map_io,
	.init_machine	= mini6410_machine_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
e9debd98 DA	1	/* linux/arch/arm/mach-s3c64xx/mach-mini6410.c
	2	*
	3	* Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
	4	* Copyright 2008 Openmoko, Inc.
	5	* Copyright 2008 Simtec Electronics
	6	* Ben Dooks <ben@simtec.co.uk>
	7	* http://armlinux.simtec.co.uk/
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/interrupt.h>
2abca87c	17	#include <linux/fb.h>
e9debd98 DA	18	#include <linux/gpio.h>
	19	#include <linux/kernel.h>
	20	#include <linux/list.h>
	21	#include <linux/dm9000.h>
1c5d76ef DA	22	#include <linux/mtd/mtd.h>
1c5d76ef DA	23	#include <linux/mtd/partitions.h>
e9debd98 DA	24	#include <linux/serial_core.h>
	25	#include <linux/types.h>
	26
	27	#include <asm/mach-types.h>
	28	#include <asm/mach/arch.h>
	29	#include <asm/mach/map.h>
	30
	31	#include <mach/map.h>
2abca87c	32	#include <mach/regs-fb.h>
e9debd98	33	#include <mach/regs-gpio.h>
2abca87c	34	#include <mach/regs-modem.h>
e9debd98 DA	35	#include <mach/regs-srom.h>
	36	#include <mach/s3c6410.h>
	37
	38	#include <plat/cpu.h>
	39	#include <plat/devs.h>
2abca87c	40	#include <plat/fb.h>
1c5d76ef	41	#include <plat/nand.h>
e9debd98	42	#include <plat/regs-serial.h>
bbd7ac63	43	#include <video/platform_lcd.h>
e9debd98 DA	44
	45	#define UCON (S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK)
	46	#define ULCON (S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB)
	47	#define UFCON (S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE)
	48
	49	static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
	50	[0] = {
	51	.hwport = 0,
	52	.flags = 0,
	53	.ucon = UCON,
	54	.ulcon = ULCON,
	55	.ufcon = UFCON,
	56	},
	57	[1] = {
	58	.hwport = 1,
	59	.flags = 0,
	60	.ucon = UCON,
	61	.ulcon = ULCON,
	62	.ufcon = UFCON,
	63	},
	64	[2] = {
	65	.hwport = 2,
	66	.flags = 0,
	67	.ucon = UCON,
	68	.ulcon = ULCON,
	69	.ufcon = UFCON,
	70	},
	71	[3] = {
	72	.hwport = 3,
	73	.flags = 0,
	74	.ucon = UCON,
	75	.ulcon = ULCON,
	76	.ufcon = UFCON,
	77	},
	78	};
	79
	80	/* DM9000AEP 10/100 ethernet controller */
	81
	82	static struct resource mini6410_dm9k_resource[] = {
	83	[0] = {
	84	.start = S3C64XX_PA_XM0CSN1,
	85	.end = S3C64XX_PA_XM0CSN1 + 1,
	86	.flags = IORESOURCE_MEM
	87	},
	88	[1] = {
	89	.start = S3C64XX_PA_XM0CSN1 + 4,
	90	.end = S3C64XX_PA_XM0CSN1 + 5,
	91	.flags = IORESOURCE_MEM
	92	},
	93	[2] = {
	94	.start = S3C_EINT(7),
	95	.end = S3C_EINT(7),
	96	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL
	97	}
	98	};
	99
	100	static struct dm9000_plat_data mini6410_dm9k_pdata = {
	101	.flags = (DM9000_PLATF_16BITONLY \| DM9000_PLATF_NO_EEPROM),
	102	};
	103
	104	static struct platform_device mini6410_device_eth = {
	105	.name = "dm9000",
	106	.id = -1,
	107	.num_resources = ARRAY_SIZE(mini6410_dm9k_resource),
108	.resource = mini6410_dm9k_resource,
109	.dev = {
110	.platform_data = &mini6410_dm9k_pdata,
111	},
112	};
113
1c5d76ef DA	114	static struct mtd_partition mini6410_nand_part[] = {
	115	[0] = {
	116	.name = "uboot",
	117	.size = SZ_1M,
	118	.offset = 0,
	119	},
	120	[1] = {
	121	.name = "kernel",
	122	.size = SZ_2M,
	123	.offset = SZ_1M,
	124	},
	125	[2] = {
	126	.name = "rootfs",
	127	.size = MTDPART_SIZ_FULL,
	128	.offset = SZ_1M + SZ_2M,
	129	},
	130	};
	131
	132	static struct s3c2410_nand_set mini6410_nand_sets[] = {
	133	[0] = {
	134	.name = "nand",
	135	.nr_chips = 1,
	136	.nr_partitions = ARRAY_SIZE(mini6410_nand_part),
	137	.partitions = mini6410_nand_part,
	138	},
	139	};
	140
	141	static struct s3c2410_platform_nand mini6410_nand_info = {
	142	.tacls = 25,
	143	.twrph0 = 55,
	144	.twrph1 = 40,
	145	.nr_sets = ARRAY_SIZE(mini6410_nand_sets),
	146	.sets = mini6410_nand_sets,
	147	};
	148
2abca87c DA	149	static struct s3c_fb_pd_win mini6410_fb_win[] = {
	150	{
	151	.win_mode = { /* 4.3" 480x272 */
	152	.left_margin = 3,
	153	.right_margin = 2,
	154	.upper_margin = 1,
	155	.lower_margin = 1,
	156	.hsync_len = 40,
	157	.vsync_len = 1,
	158	.xres = 480,
	159	.yres = 272,
	160	},
	161	.max_bpp = 32,
	162	.default_bpp = 16,
	163	}, {
	164	.win_mode = { /* 7.0" 800x480 */
	165	.left_margin = 8,
	166	.right_margin = 13,
	167	.upper_margin = 7,
	168	.lower_margin = 5,
	169	.hsync_len = 3,
	170	.vsync_len = 1,
	171	.xres = 800,
	172	.yres = 480,
	173	},
	174	.max_bpp = 32,
	175	.default_bpp = 16,
	176	},
	177	};
	178
	179	static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
	180	.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
	181	.win[0] = &mini6410_fb_win[0],
	182	.vidcon0 = VIDCON0_VIDOUT_RGB \| VIDCON0_PNRMODE_RGB,
	183	.vidcon1 = VIDCON1_INV_HSYNC \| VIDCON1_INV_VSYNC,
	184	};
	185
bbd7ac63 DA	186	static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
	187	unsigned int power)
	188	{
	189	if (power)
	190	gpio_direction_output(S3C64XX_GPE(0), 1);
	191	else
	192	gpio_direction_output(S3C64XX_GPE(0), 0);
	193	}
	194
	195	static struct plat_lcd_data mini6410_lcd_power_data = {
	196	.set_power = mini6410_lcd_power_set,
	197	};
	198
	199	static struct platform_device mini6410_lcd_powerdev = {
	200	.name = "platform-lcd",
	201	.dev.parent = &s3c_device_fb.dev,
	202	.dev.platform_data = &mini6410_lcd_power_data,
	203	};
	204
e9debd98 DA	205	static struct platform_device *mini6410_devices[] __initdata = {
	206	&mini6410_device_eth,
	207	&s3c_device_hsmmc0,
	208	&s3c_device_hsmmc1,
	209	&s3c_device_ohci,
1c5d76ef	210	&s3c_device_nand,
2abca87c	211	&s3c_device_fb,
bbd7ac63	212	&mini6410_lcd_powerdev,
e9debd98 DA	213	};
	214
	215	static void __init mini6410_map_io(void)
	216	{
2abca87c DA	217	u32 tmp;
2abca87c DA	218
e9debd98 DA	219	s3c64xx_init_io(NULL, 0);
	220	s3c24xx_init_clocks(12000000);
	221	s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
2abca87c DA	222
	223	/* set the LCD type */
	224	tmp = __raw_readl(S3C64XX_SPCON);
	225	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
	226	tmp \|= S3C64XX_SPCON_LCD_SEL_RGB;
	227	__raw_writel(tmp, S3C64XX_SPCON);
	228
	229	/* remove the LCD bypass */
	230	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
	231	tmp &= ~MIFPCON_LCD_BYPASS;
	232	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
	233	}
	234
	235	/*
	236	* mini6410_features string
	237	*
	238	* 0-9 LCD configuration
	239	*
	240	*/
	241	static char mini6410_features_str[12] __initdata = "0";
	242
	243	static int __init mini6410_features_setup(char *str)
	244	{
	245	if (str)
	246	strlcpy(mini6410_features_str, str,
	247	sizeof(mini6410_features_str));
	248	return 1;
	249	}
	250
	251	__setup("mini6410=", mini6410_features_setup);
	252
	253	#define FEATURE_SCREEN (1 << 0)
	254
	255	struct mini6410_features_t {
	256	int done;
	257	int lcd_index;
	258	};
	259
	260	static void mini6410_parse_features(
	261	struct mini6410_features_t *features,
	262	const char *features_str)
	263	{
	264	const char *fp = features_str;
	265
	266	features->done = 0;
	267	features->lcd_index = 0;
	268
	269	while (*fp) {
	270	char f = *fp++;
	271
	272	switch (f) {
	273	case '0'...'9': /* tft screen */
	274	if (features->done & FEATURE_SCREEN) {
	275	printk(KERN_INFO "MINI6410: '%c' ignored, "
	276	"screen type already set\n", f);
	277	} else {
	278	int li = f - '0';
	279	if (li >= ARRAY_SIZE(mini6410_fb_win))
	280	printk(KERN_INFO "MINI6410: '%c' out "
	281	"of range LCD mode\n", f);
	282	else {
	283	features->lcd_index = li;
	284	}
	285	}
286	features->done \|= FEATURE_SCREEN;
287	break;
288	}
289	}
e9debd98 DA	290	}
	291
	292	static void __init mini6410_machine_init(void)
	293	{
	294	u32 cs1;
2abca87c DA	295	struct mini6410_features_t features = { 0 };
	296
	297	printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
	298	mini6410_features_str);
	299
	300	/* Parse the feature string */
	301	mini6410_parse_features(&features, mini6410_features_str);
	302
	303	mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index];
	304
	305	printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
	306	mini6410_lcd_pdata.win[0]->win_mode.xres,
	307	mini6410_lcd_pdata.win[0]->win_mode.yres);
e9debd98	308
1c5d76ef	309	s3c_nand_set_platdata(&mini6410_nand_info);
2abca87c	310	s3c_fb_set_platdata(&mini6410_lcd_pdata);
1c5d76ef	311
e9debd98 DA	312	/* configure nCS1 width to 16 bits */
	313
	314	cs1 = __raw_readl(S3C64XX_SROM_BW) &
	315	~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
	316	cs1 \|= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) \|
	317	(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) \|
	318	(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
	319	S3C64XX_SROM_BW__NCS1__SHIFT;
	320	__raw_writel(cs1, S3C64XX_SROM_BW);
	321
	322	/* set timing for nCS1 suitable for ethernet chip */
	323
	324	__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) \|
	325	(6 << S3C64XX_SROM_BCX__TACP__SHIFT) \|
	326	(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) \|
	327	(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) \|
	328	(13 << S3C64XX_SROM_BCX__TACC__SHIFT) \|
	329	(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) \|
	330	(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
	331
2abca87c DA	332	gpio_request(S3C64XX_GPF(15), "LCD power");
	333	gpio_request(S3C64XX_GPE(0), "LCD power");
	334
e9debd98 DA	335	platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
	336	}
	337
	338	MACHINE_START(MINI6410, "MINI6410")
	339	/* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
	340	.boot_params = S3C64XX_PA_SDRAM + 0x100,
	341	.init_irq = s3c6410_init_irq,
	342	.map_io = mini6410_map_io,
	343	.init_machine = mini6410_machine_init,
	344	.timer = &s3c24xx_timer,
	345	MACHINE_END