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431107ea | 1 | /* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c |
5718df9d BD |
2 | * |
3 | * Copyright 2008 Openmoko, Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/timer.h> | |
19 | #include <linux/init.h> | |
290d0983 | 20 | #include <linux/input.h> |
5718df9d | 21 | #include <linux/serial_core.h> |
334a1c70 | 22 | #include <linux/serial_s3c.h> |
5718df9d BD |
23 | #include <linux/platform_device.h> |
24 | #include <linux/io.h> | |
096941ed | 25 | #include <linux/i2c.h> |
a7a81d0b | 26 | #include <linux/leds.h> |
438a5d42 BD |
27 | #include <linux/fb.h> |
28 | #include <linux/gpio.h> | |
29 | #include <linux/delay.h> | |
3056ea0a | 30 | #include <linux/smsc911x.h> |
42015c13 | 31 | #include <linux/regulator/fixed.h> |
628e7eb5 | 32 | #include <linux/regulator/machine.h> |
bf0ff1cd | 33 | #include <linux/pwm.h> |
075d1089 | 34 | #include <linux/pwm_backlight.h> |
126625e1 | 35 | #include <linux/platform_data/s3c-hsotg.h> |
438a5d42 | 36 | |
ecc558ac MB |
37 | #ifdef CONFIG_SMDK6410_WM1190_EV1 |
38 | #include <linux/mfd/wm8350/core.h> | |
39 | #include <linux/mfd/wm8350/pmic.h> | |
40 | #endif | |
438a5d42 | 41 | |
60f9101a | 42 | #ifdef CONFIG_SMDK6410_WM1192_EV1 |
a7a81d0b | 43 | #include <linux/mfd/wm831x/core.h> |
60f9101a MB |
44 | #include <linux/mfd/wm831x/pdata.h> |
45 | #endif | |
46 | ||
438a5d42 | 47 | #include <video/platform_lcd.h> |
5a213a55 | 48 | #include <video/samsung_fimd.h> |
5718df9d BD |
49 | |
50 | #include <asm/mach/arch.h> | |
51 | #include <asm/mach/map.h> | |
52 | #include <asm/mach/irq.h> | |
53 | ||
54 | #include <mach/hardware.h> | |
ba279044 | 55 | #include <mach/irqs.h> |
5718df9d BD |
56 | #include <mach/map.h> |
57 | ||
58 | #include <asm/irq.h> | |
59 | #include <asm/mach-types.h> | |
60 | ||
3501c9ae | 61 | #include <mach/regs-gpio.h> |
b0161caa | 62 | #include <mach/gpio-samsung.h> |
436d42c6 AB |
63 | #include <linux/platform_data/ata-samsung_cf.h> |
64 | #include <linux/platform_data/i2c-s3c2410.h> | |
438a5d42 | 65 | #include <plat/fb.h> |
3056ea0a | 66 | #include <plat/gpio-cfg.h> |
5718df9d | 67 | |
5718df9d BD |
68 | #include <plat/devs.h> |
69 | #include <plat/cpu.h> | |
85b14a3f | 70 | #include <plat/adc.h> |
436d42c6 | 71 | #include <linux/platform_data/touchscreen-s3c2410.h> |
290d0983 | 72 | #include <plat/keypad.h> |
04a49b71 | 73 | #include <plat/samsung-time.h> |
5718df9d | 74 | |
4a7bf56f | 75 | #include "backlight.h" |
b024043b | 76 | #include "common.h" |
a81c1970 | 77 | #include "regs-modem.h" |
8eba8ea2 | 78 | #include "regs-srom.h" |
f2bfd174 | 79 | #include "regs-sys.h" |
b024043b | 80 | |
5718df9d BD |
81 | #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK |
82 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | |
83 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE | |
84 | ||
85 | static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = { | |
86 | [0] = { | |
87 | .hwport = 0, | |
88 | .flags = 0, | |
bd258e52 MH |
89 | .ucon = UCON, |
90 | .ulcon = ULCON, | |
91 | .ufcon = UFCON, | |
5718df9d BD |
92 | }, |
93 | [1] = { | |
94 | .hwport = 1, | |
95 | .flags = 0, | |
bd258e52 MH |
96 | .ucon = UCON, |
97 | .ulcon = ULCON, | |
98 | .ufcon = UFCON, | |
99 | }, | |
100 | [2] = { | |
101 | .hwport = 2, | |
102 | .flags = 0, | |
103 | .ucon = UCON, | |
104 | .ulcon = ULCON, | |
105 | .ufcon = UFCON, | |
106 | }, | |
107 | [3] = { | |
108 | .hwport = 3, | |
109 | .flags = 0, | |
110 | .ucon = UCON, | |
111 | .ulcon = ULCON, | |
112 | .ufcon = UFCON, | |
5718df9d BD |
113 | }, |
114 | }; | |
115 | ||
438a5d42 BD |
116 | /* framebuffer and LCD setup. */ |
117 | ||
118 | /* GPF15 = LCD backlight control | |
119 | * GPF13 => Panel power | |
120 | * GPN5 = LCD nRESET signal | |
121 | * PWM_TOUT1 => backlight brightness | |
122 | */ | |
123 | ||
124 | static void smdk6410_lcd_power_set(struct plat_lcd_data *pd, | |
125 | unsigned int power) | |
126 | { | |
127 | if (power) { | |
128 | gpio_direction_output(S3C64XX_GPF(13), 1); | |
438a5d42 BD |
129 | |
130 | /* fire nRESET on power up */ | |
131 | gpio_direction_output(S3C64XX_GPN(5), 0); | |
132 | msleep(10); | |
133 | gpio_direction_output(S3C64XX_GPN(5), 1); | |
134 | msleep(1); | |
135 | } else { | |
438a5d42 BD |
136 | gpio_direction_output(S3C64XX_GPF(13), 0); |
137 | } | |
138 | } | |
139 | ||
140 | static struct plat_lcd_data smdk6410_lcd_power_data = { | |
141 | .set_power = smdk6410_lcd_power_set, | |
142 | }; | |
143 | ||
144 | static struct platform_device smdk6410_lcd_powerdev = { | |
145 | .name = "platform-lcd", | |
146 | .dev.parent = &s3c_device_fb.dev, | |
147 | .dev.platform_data = &smdk6410_lcd_power_data, | |
148 | }; | |
149 | ||
150 | static struct s3c_fb_pd_win smdk6410_fb_win0 = { | |
438a5d42 BD |
151 | .max_bpp = 32, |
152 | .default_bpp = 16, | |
79d3c41a TA |
153 | .xres = 800, |
154 | .yres = 480, | |
001ca74f BD |
155 | .virtual_y = 480 * 2, |
156 | .virtual_x = 800, | |
438a5d42 BD |
157 | }; |
158 | ||
79d3c41a TA |
159 | static struct fb_videomode smdk6410_lcd_timing = { |
160 | .left_margin = 8, | |
161 | .right_margin = 13, | |
162 | .upper_margin = 7, | |
163 | .lower_margin = 5, | |
164 | .hsync_len = 3, | |
165 | .vsync_len = 1, | |
166 | .xres = 800, | |
167 | .yres = 480, | |
168 | }; | |
169 | ||
438a5d42 BD |
170 | /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */ |
171 | static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = { | |
172 | .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, | |
79d3c41a | 173 | .vtiming = &smdk6410_lcd_timing, |
438a5d42 BD |
174 | .win[0] = &smdk6410_fb_win0, |
175 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, | |
176 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, | |
177 | }; | |
178 | ||
a4e94694 AG |
179 | /* |
180 | * Configuring Ethernet on SMDK6410 | |
181 | * | |
182 | * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6. | |
183 | * The constant address below corresponds to nCS1 | |
184 | * | |
185 | * 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet" | |
186 | * 2) CFG6 needs to be switched to "LAN9115" side | |
187 | */ | |
188 | ||
3056ea0a | 189 | static struct resource smdk6410_smsc911x_resources[] = { |
c858fd5f TB |
190 | [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, SZ_64K), |
191 | [1] = DEFINE_RES_NAMED(S3C_EINT(10), 1, NULL, IORESOURCE_IRQ \ | |
192 | | IRQ_TYPE_LEVEL_LOW), | |
3056ea0a MB |
193 | }; |
194 | ||
195 | static struct smsc911x_platform_config smdk6410_smsc911x_pdata = { | |
196 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | |
197 | .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, | |
198 | .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY, | |
199 | .phy_interface = PHY_INTERFACE_MODE_MII, | |
200 | }; | |
201 | ||
202 | ||
203 | static struct platform_device smdk6410_smsc911x = { | |
204 | .name = "smsc911x", | |
205 | .id = -1, | |
206 | .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources), | |
207 | .resource = &smdk6410_smsc911x_resources[0], | |
208 | .dev = { | |
209 | .platform_data = &smdk6410_smsc911x_pdata, | |
210 | }, | |
211 | }; | |
212 | ||
42015c13 | 213 | #ifdef CONFIG_REGULATOR |
19c69daf | 214 | static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = { |
b5930b83 MB |
215 | REGULATOR_SUPPLY("PVDD", "0-001b"), |
216 | REGULATOR_SUPPLY("AVDD", "0-001b"), | |
42015c13 MB |
217 | }; |
218 | ||
a113b057 | 219 | static struct regulator_init_data __maybe_unused smdk6410_b_pwr_5v_data = { |
42015c13 MB |
220 | .constraints = { |
221 | .always_on = 1, | |
222 | }, | |
223 | .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers), | |
224 | .consumer_supplies = smdk6410_b_pwr_5v_consumers, | |
225 | }; | |
226 | ||
227 | static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = { | |
228 | .supply_name = "B_PWR_5V", | |
229 | .microvolts = 5000000, | |
230 | .init_data = &smdk6410_b_pwr_5v_data, | |
d3cf4489 | 231 | .gpio = -EINVAL, |
42015c13 MB |
232 | }; |
233 | ||
234 | static struct platform_device smdk6410_b_pwr_5v = { | |
235 | .name = "reg-fixed-voltage", | |
236 | .id = -1, | |
237 | .dev = { | |
238 | .platform_data = &smdk6410_b_pwr_5v_pdata, | |
239 | }, | |
240 | }; | |
241 | #endif | |
242 | ||
0ab0b6d2 AK |
243 | static struct s3c_ide_platdata smdk6410_ide_pdata __initdata = { |
244 | .setup_gpio = s3c64xx_ide_setup_gpio, | |
245 | }; | |
246 | ||
290d0983 NKC |
247 | static uint32_t smdk6410_keymap[] __initdata = { |
248 | /* KEY(row, col, keycode) */ | |
249 | KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3), | |
250 | KEY(0, 6, KEY_4), KEY(0, 7, KEY_5), | |
251 | KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C), | |
252 | KEY(1, 6, KEY_D), KEY(1, 7, KEY_E) | |
253 | }; | |
254 | ||
255 | static struct matrix_keymap_data smdk6410_keymap_data __initdata = { | |
256 | .keymap = smdk6410_keymap, | |
257 | .keymap_size = ARRAY_SIZE(smdk6410_keymap), | |
258 | }; | |
259 | ||
260 | static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = { | |
261 | .keymap_data = &smdk6410_keymap_data, | |
262 | .rows = 2, | |
263 | .cols = 8, | |
264 | }; | |
265 | ||
027191a8 | 266 | static struct map_desc smdk6410_iodesc[] = {}; |
5718df9d BD |
267 | |
268 | static struct platform_device *smdk6410_devices[] __initdata = { | |
b24636cf | 269 | #ifdef CONFIG_SMDK6410_SD_CH0 |
39057f23 | 270 | &s3c_device_hsmmc0, |
b24636cf BD |
271 | #endif |
272 | #ifdef CONFIG_SMDK6410_SD_CH1 | |
273 | &s3c_device_hsmmc1, | |
274 | #endif | |
d85fa24c | 275 | &s3c_device_i2c0, |
d7ea3743 | 276 | &s3c_device_i2c1, |
438a5d42 | 277 | &s3c_device_fb, |
b813248c | 278 | &s3c_device_ohci, |
7fa33bdb | 279 | &samsung_device_pwm, |
06fa1d37 | 280 | &s3c_device_usb_hsotg, |
1f100868 | 281 | &s3c64xx_device_iisv4, |
290d0983 | 282 | &samsung_device_keypad, |
42015c13 MB |
283 | |
284 | #ifdef CONFIG_REGULATOR | |
285 | &smdk6410_b_pwr_5v, | |
286 | #endif | |
438a5d42 | 287 | &smdk6410_lcd_powerdev, |
3056ea0a MB |
288 | |
289 | &smdk6410_smsc911x, | |
85b14a3f | 290 | &s3c_device_adc, |
0ab0b6d2 | 291 | &s3c_device_cfcon, |
9bbf4a63 | 292 | &s3c_device_rtc, |
b351c4a1 | 293 | &s3c_device_wdt, |
5718df9d BD |
294 | }; |
295 | ||
60f9101a MB |
296 | #ifdef CONFIG_REGULATOR |
297 | /* ARM core */ | |
298 | static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = { | |
b5930b83 | 299 | REGULATOR_SUPPLY("vddarm", NULL), |
60f9101a MB |
300 | }; |
301 | ||
302 | /* VDDARM, BUCK1 on J5 */ | |
a113b057 | 303 | static struct regulator_init_data __maybe_unused smdk6410_vddarm = { |
ecc558ac | 304 | .constraints = { |
60f9101a MB |
305 | .name = "PVDD_ARM", |
306 | .min_uV = 1000000, | |
307 | .max_uV = 1300000, | |
308 | .always_on = 1, | |
309 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | |
310 | }, | |
311 | .num_consumer_supplies = ARRAY_SIZE(smdk6410_vddarm_consumers), | |
312 | .consumer_supplies = smdk6410_vddarm_consumers, | |
313 | }; | |
314 | ||
315 | /* VDD_INT, BUCK2 on J5 */ | |
a113b057 | 316 | static struct regulator_init_data __maybe_unused smdk6410_vddint = { |
60f9101a MB |
317 | .constraints = { |
318 | .name = "PVDD_INT", | |
319 | .min_uV = 1000000, | |
ecc558ac MB |
320 | .max_uV = 1200000, |
321 | .always_on = 1, | |
60f9101a | 322 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, |
ecc558ac MB |
323 | }, |
324 | }; | |
325 | ||
60f9101a | 326 | /* VDD_HI, LDO3 on J5 */ |
a113b057 | 327 | static struct regulator_init_data __maybe_unused smdk6410_vddhi = { |
ecc558ac | 328 | .constraints = { |
60f9101a | 329 | .name = "PVDD_HI", |
ecc558ac | 330 | .always_on = 1, |
ecc558ac MB |
331 | }, |
332 | }; | |
333 | ||
60f9101a | 334 | /* VDD_PLL, LDO2 on J5 */ |
a113b057 | 335 | static struct regulator_init_data __maybe_unused smdk6410_vddpll = { |
60f9101a MB |
336 | .constraints = { |
337 | .name = "PVDD_PLL", | |
338 | .always_on = 1, | |
42015c13 MB |
339 | }, |
340 | }; | |
341 | ||
60f9101a | 342 | /* VDD_UH_MMC, LDO5 on J5 */ |
a113b057 | 343 | static struct regulator_init_data __maybe_unused smdk6410_vdduh_mmc = { |
ecc558ac | 344 | .constraints = { |
18b52ca5 | 345 | .name = "PVDD_UH+PVDD_MMC", |
ecc558ac MB |
346 | .always_on = 1, |
347 | }, | |
348 | }; | |
349 | ||
60f9101a | 350 | /* VCCM3BT, LDO8 on J5 */ |
a113b057 | 351 | static struct regulator_init_data __maybe_unused smdk6410_vccmc3bt = { |
60f9101a MB |
352 | .constraints = { |
353 | .name = "PVCCM3BT", | |
354 | .always_on = 1, | |
355 | }, | |
e3980b6a MB |
356 | }; |
357 | ||
60f9101a | 358 | /* VCCM2MTV, LDO11 on J5 */ |
a113b057 | 359 | static struct regulator_init_data __maybe_unused smdk6410_vccm2mtv = { |
ecc558ac | 360 | .constraints = { |
60f9101a MB |
361 | .name = "PVCCM2MTV", |
362 | .always_on = 1, | |
363 | }, | |
364 | }; | |
365 | ||
366 | /* VDD_LCD, LDO12 on J5 */ | |
a113b057 | 367 | static struct regulator_init_data __maybe_unused smdk6410_vddlcd = { |
60f9101a MB |
368 | .constraints = { |
369 | .name = "PVDD_LCD", | |
370 | .always_on = 1, | |
371 | }, | |
372 | }; | |
373 | ||
374 | /* VDD_OTGI, LDO9 on J5 */ | |
a113b057 | 375 | static struct regulator_init_data __maybe_unused smdk6410_vddotgi = { |
60f9101a MB |
376 | .constraints = { |
377 | .name = "PVDD_OTGI", | |
378 | .always_on = 1, | |
379 | }, | |
380 | }; | |
381 | ||
382 | /* VDD_OTG, LDO14 on J5 */ | |
a113b057 | 383 | static struct regulator_init_data __maybe_unused smdk6410_vddotg = { |
60f9101a MB |
384 | .constraints = { |
385 | .name = "PVDD_OTG", | |
ecc558ac MB |
386 | .always_on = 1, |
387 | }, | |
5718df9d BD |
388 | }; |
389 | ||
60f9101a | 390 | /* VDD_ALIVE, LDO15 on J5 */ |
a113b057 | 391 | static struct regulator_init_data __maybe_unused smdk6410_vddalive = { |
ecc558ac MB |
392 | .constraints = { |
393 | .name = "PVDD_ALIVE", | |
60f9101a MB |
394 | .always_on = 1, |
395 | }, | |
396 | }; | |
397 | ||
398 | /* VDD_AUDIO, VLDO_AUDIO on J5 */ | |
a113b057 | 399 | static struct regulator_init_data __maybe_unused smdk6410_vddaudio = { |
60f9101a MB |
400 | .constraints = { |
401 | .name = "PVDD_AUDIO", | |
402 | .always_on = 1, | |
403 | }, | |
404 | }; | |
405 | #endif | |
406 | ||
407 | #ifdef CONFIG_SMDK6410_WM1190_EV1 | |
408 | /* S3C64xx internal logic & PLL */ | |
a113b057 | 409 | static struct regulator_init_data __maybe_unused wm8350_dcdc1_data = { |
60f9101a | 410 | .constraints = { |
18b52ca5 | 411 | .name = "PVDD_INT+PVDD_PLL", |
ecc558ac MB |
412 | .min_uV = 1200000, |
413 | .max_uV = 1200000, | |
414 | .always_on = 1, | |
415 | .apply_uV = 1, | |
416 | }, | |
417 | }; | |
418 | ||
60f9101a | 419 | /* Memory */ |
a113b057 | 420 | static struct regulator_init_data __maybe_unused wm8350_dcdc3_data = { |
ecc558ac | 421 | .constraints = { |
60f9101a MB |
422 | .name = "PVDD_MEM", |
423 | .min_uV = 1800000, | |
424 | .max_uV = 1800000, | |
f53aee29 | 425 | .always_on = 1, |
60f9101a MB |
426 | .state_mem = { |
427 | .uV = 1800000, | |
428 | .mode = REGULATOR_MODE_NORMAL, | |
429 | .enabled = 1, | |
430 | }, | |
431 | .initial_state = PM_SUSPEND_MEM, | |
ecc558ac MB |
432 | }, |
433 | }; | |
434 | ||
60f9101a MB |
435 | /* USB, EXT, PCM, ADC/DAC, USB, MMC */ |
436 | static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = { | |
b5930b83 | 437 | REGULATOR_SUPPLY("DVDD", "0-001b"), |
60f9101a MB |
438 | }; |
439 | ||
a113b057 | 440 | static struct regulator_init_data __maybe_unused wm8350_dcdc4_data = { |
ecc558ac | 441 | .constraints = { |
18b52ca5 | 442 | .name = "PVDD_HI+PVDD_EXT+PVDD_SYS+PVCCM2MTV", |
ecc558ac MB |
443 | .min_uV = 3000000, |
444 | .max_uV = 3000000, | |
f53aee29 | 445 | .always_on = 1, |
ecc558ac | 446 | }, |
60f9101a MB |
447 | .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers), |
448 | .consumer_supplies = wm8350_dcdc4_consumers, | |
ecc558ac MB |
449 | }; |
450 | ||
451 | /* OTGi/1190-EV1 HPVDD & AVDD */ | |
a113b057 | 452 | static struct regulator_init_data __maybe_unused wm8350_ldo4_data = { |
ecc558ac | 453 | .constraints = { |
18b52ca5 | 454 | .name = "PVDD_OTGI+HPVDD+AVDD", |
ecc558ac MB |
455 | .min_uV = 1200000, |
456 | .max_uV = 1200000, | |
457 | .apply_uV = 1, | |
f53aee29 | 458 | .always_on = 1, |
ecc558ac MB |
459 | }, |
460 | }; | |
461 | ||
462 | static struct { | |
463 | int regulator; | |
464 | struct regulator_init_data *initdata; | |
465 | } wm1190_regulators[] = { | |
466 | { WM8350_DCDC_1, &wm8350_dcdc1_data }, | |
467 | { WM8350_DCDC_3, &wm8350_dcdc3_data }, | |
468 | { WM8350_DCDC_4, &wm8350_dcdc4_data }, | |
60f9101a MB |
469 | { WM8350_DCDC_6, &smdk6410_vddarm }, |
470 | { WM8350_LDO_1, &smdk6410_vddalive }, | |
471 | { WM8350_LDO_2, &smdk6410_vddotg }, | |
472 | { WM8350_LDO_3, &smdk6410_vddlcd }, | |
ecc558ac MB |
473 | { WM8350_LDO_4, &wm8350_ldo4_data }, |
474 | }; | |
475 | ||
476 | static int __init smdk6410_wm8350_init(struct wm8350 *wm8350) | |
477 | { | |
478 | int i; | |
479 | ||
a3323b72 MB |
480 | /* Configure the IRQ line */ |
481 | s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP); | |
482 | ||
ecc558ac MB |
483 | /* Instantiate the regulators */ |
484 | for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++) | |
485 | wm8350_register_regulator(wm8350, | |
486 | wm1190_regulators[i].regulator, | |
487 | wm1190_regulators[i].initdata); | |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
492 | static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = { | |
493 | .init = smdk6410_wm8350_init, | |
db9256f3 | 494 | .irq_high = 1, |
9fca8786 | 495 | .irq_base = IRQ_BOARD_START, |
ecc558ac MB |
496 | }; |
497 | #endif | |
498 | ||
60f9101a | 499 | #ifdef CONFIG_SMDK6410_WM1192_EV1 |
a7a81d0b MB |
500 | static struct gpio_led wm1192_pmic_leds[] = { |
501 | { | |
502 | .name = "PMIC:red:power", | |
503 | .gpio = GPIO_BOARD_START + 3, | |
504 | .default_state = LEDS_GPIO_DEFSTATE_ON, | |
505 | }, | |
506 | }; | |
507 | ||
508 | static struct gpio_led_platform_data wm1192_pmic_led = { | |
509 | .num_leds = ARRAY_SIZE(wm1192_pmic_leds), | |
510 | .leds = wm1192_pmic_leds, | |
511 | }; | |
512 | ||
513 | static struct platform_device wm1192_pmic_led_dev = { | |
514 | .name = "leds-gpio", | |
515 | .id = -1, | |
516 | .dev = { | |
517 | .platform_data = &wm1192_pmic_led, | |
518 | }, | |
519 | }; | |
520 | ||
60f9101a MB |
521 | static int wm1192_pre_init(struct wm831x *wm831x) |
522 | { | |
a7a81d0b MB |
523 | int ret; |
524 | ||
60f9101a MB |
525 | /* Configure the IRQ line */ |
526 | s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP); | |
527 | ||
a7a81d0b MB |
528 | ret = platform_device_register(&wm1192_pmic_led_dev); |
529 | if (ret != 0) | |
530 | dev_err(wm831x->dev, "Failed to add PMIC LED: %d\n", ret); | |
531 | ||
60f9101a MB |
532 | return 0; |
533 | } | |
534 | ||
535 | static struct wm831x_backlight_pdata wm1192_backlight_pdata = { | |
536 | .isink = 1, | |
537 | .max_uA = 27554, | |
538 | }; | |
539 | ||
a113b057 | 540 | static struct regulator_init_data __maybe_unused wm1192_dcdc3 = { |
60f9101a | 541 | .constraints = { |
18b52ca5 | 542 | .name = "PVDD_MEM+PVDD_GPS", |
60f9101a MB |
543 | .always_on = 1, |
544 | }, | |
545 | }; | |
546 | ||
547 | static struct regulator_consumer_supply wm1192_ldo1_consumers[] = { | |
b5930b83 | 548 | REGULATOR_SUPPLY("DVDD", "0-001b"), /* WM8580 */ |
60f9101a MB |
549 | }; |
550 | ||
a113b057 | 551 | static struct regulator_init_data __maybe_unused wm1192_ldo1 = { |
60f9101a | 552 | .constraints = { |
18b52ca5 | 553 | .name = "PVDD_LCD+PVDD_EXT", |
60f9101a MB |
554 | .always_on = 1, |
555 | }, | |
556 | .consumer_supplies = wm1192_ldo1_consumers, | |
557 | .num_consumer_supplies = ARRAY_SIZE(wm1192_ldo1_consumers), | |
558 | }; | |
559 | ||
560 | static struct wm831x_status_pdata wm1192_led7_pdata = { | |
561 | .name = "LED7:green:", | |
562 | }; | |
563 | ||
564 | static struct wm831x_status_pdata wm1192_led8_pdata = { | |
565 | .name = "LED8:green:", | |
566 | }; | |
567 | ||
568 | static struct wm831x_pdata smdk6410_wm1192_pdata = { | |
569 | .pre_init = wm1192_pre_init, | |
60f9101a MB |
570 | |
571 | .backlight = &wm1192_backlight_pdata, | |
572 | .dcdc = { | |
573 | &smdk6410_vddarm, /* DCDC1 */ | |
574 | &smdk6410_vddint, /* DCDC2 */ | |
575 | &wm1192_dcdc3, | |
576 | }, | |
a7a81d0b | 577 | .gpio_base = GPIO_BOARD_START, |
60f9101a MB |
578 | .ldo = { |
579 | &wm1192_ldo1, /* LDO1 */ | |
580 | &smdk6410_vdduh_mmc, /* LDO2 */ | |
581 | NULL, /* LDO3 NC */ | |
582 | &smdk6410_vddotgi, /* LDO4 */ | |
583 | &smdk6410_vddotg, /* LDO5 */ | |
584 | &smdk6410_vddhi, /* LDO6 */ | |
585 | &smdk6410_vddaudio, /* LDO7 */ | |
586 | &smdk6410_vccm2mtv, /* LDO8 */ | |
587 | &smdk6410_vddpll, /* LDO9 */ | |
588 | &smdk6410_vccmc3bt, /* LDO10 */ | |
589 | &smdk6410_vddalive, /* LDO11 */ | |
590 | }, | |
591 | .status = { | |
592 | &wm1192_led7_pdata, | |
593 | &wm1192_led8_pdata, | |
594 | }, | |
595 | }; | |
596 | #endif | |
597 | ||
096941ed BD |
598 | static struct i2c_board_info i2c_devs0[] __initdata = { |
599 | { I2C_BOARD_INFO("24c08", 0x50), }, | |
77897479 | 600 | { I2C_BOARD_INFO("wm8580", 0x1b), }, |
ecc558ac | 601 | |
60f9101a MB |
602 | #ifdef CONFIG_SMDK6410_WM1192_EV1 |
603 | { I2C_BOARD_INFO("wm8312", 0x34), | |
604 | .platform_data = &smdk6410_wm1192_pdata, | |
605 | .irq = S3C_EINT(12), | |
606 | }, | |
607 | #endif | |
608 | ||
ecc558ac MB |
609 | #ifdef CONFIG_SMDK6410_WM1190_EV1 |
610 | { I2C_BOARD_INFO("wm8350", 0x1a), | |
611 | .platform_data = &smdk6410_wm8350_pdata, | |
612 | .irq = S3C_EINT(12), | |
613 | }, | |
614 | #endif | |
096941ed BD |
615 | }; |
616 | ||
617 | static struct i2c_board_info i2c_devs1[] __initdata = { | |
618 | { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */ | |
5718df9d BD |
619 | }; |
620 | ||
96d78686 BG |
621 | /* LCD Backlight data */ |
622 | static struct samsung_bl_gpio_info smdk6410_bl_gpio_info = { | |
623 | .no = S3C64XX_GPF(15), | |
624 | .func = S3C_GPIO_SFN(2), | |
625 | }; | |
626 | ||
bf0ff1cd TR |
627 | static struct pwm_lookup smdk6410_pwm_lookup[] = { |
628 | PWM_LOOKUP("samsung-pwm", 1, "pwm-backlight.0", NULL, 78770, | |
629 | PWM_POLARITY_NORMAL), | |
630 | }; | |
631 | ||
96d78686 | 632 | static struct platform_pwm_backlight_data smdk6410_bl_data = { |
a63652f1 | 633 | .enable_gpio = -1, |
96d78686 BG |
634 | }; |
635 | ||
1f91b4cc | 636 | static struct dwc2_hsotg_plat smdk6410_hsotg_pdata; |
99f6e1f5 | 637 | |
5718df9d BD |
638 | static void __init smdk6410_map_io(void) |
639 | { | |
d6662c35 BD |
640 | u32 tmp; |
641 | ||
5718df9d | 642 | s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); |
b69f460d | 643 | s3c64xx_set_xtal_freq(12000000); |
5718df9d | 644 | s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); |
04a49b71 | 645 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); |
d6662c35 BD |
646 | |
647 | /* set the LCD type */ | |
648 | ||
649 | tmp = __raw_readl(S3C64XX_SPCON); | |
650 | tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK; | |
651 | tmp |= S3C64XX_SPCON_LCD_SEL_RGB; | |
652 | __raw_writel(tmp, S3C64XX_SPCON); | |
653 | ||
654 | /* remove the lcd bypass */ | |
655 | tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); | |
656 | tmp &= ~MIFPCON_LCD_BYPASS; | |
657 | __raw_writel(tmp, S3C64XX_MODEM_MIFPCON); | |
5718df9d BD |
658 | } |
659 | ||
660 | static void __init smdk6410_machine_init(void) | |
661 | { | |
f01fdac0 AG |
662 | u32 cs1; |
663 | ||
d85fa24c | 664 | s3c_i2c0_set_platdata(NULL); |
d7ea3743 | 665 | s3c_i2c1_set_platdata(NULL); |
438a5d42 | 666 | s3c_fb_set_platdata(&smdk6410_lcd_pdata); |
1f91b4cc | 667 | dwc2_hsotg_set_platdata(&smdk6410_hsotg_pdata); |
096941ed | 668 | |
290d0983 NKC |
669 | samsung_keypad_set_platdata(&smdk6410_keypad_data); |
670 | ||
a829ae57 | 671 | s3c64xx_ts_set_platdata(NULL); |
85b14a3f | 672 | |
f01fdac0 AG |
673 | /* configure nCS1 width to 16 bits */ |
674 | ||
675 | cs1 = __raw_readl(S3C64XX_SROM_BW) & | |
676 | ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT); | |
677 | cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) | | |
678 | (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) | | |
679 | (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) << | |
680 | S3C64XX_SROM_BW__NCS1__SHIFT; | |
681 | __raw_writel(cs1, S3C64XX_SROM_BW); | |
682 | ||
683 | /* set timing for nCS1 suitable for ethernet chip */ | |
684 | ||
685 | __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) | | |
686 | (6 << S3C64XX_SROM_BCX__TACP__SHIFT) | | |
687 | (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) | | |
688 | (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) | | |
689 | (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) | | |
690 | (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) | | |
691 | (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1); | |
692 | ||
b7f9a94b MB |
693 | gpio_request(S3C64XX_GPN(5), "LCD power"); |
694 | gpio_request(S3C64XX_GPF(13), "LCD power"); | |
b7f9a94b | 695 | |
096941ed BD |
696 | i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); |
697 | i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); | |
698 | ||
0ab0b6d2 AK |
699 | s3c_ide_set_platdata(&smdk6410_ide_pdata); |
700 | ||
5718df9d | 701 | platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices)); |
7fa33bdb | 702 | |
bf0ff1cd | 703 | pwm_add_table(smdk6410_pwm_lookup, ARRAY_SIZE(smdk6410_pwm_lookup)); |
7fa33bdb | 704 | samsung_bl_set(&smdk6410_bl_gpio_info, &smdk6410_bl_data); |
5718df9d BD |
705 | } |
706 | ||
707 | MACHINE_START(SMDK6410, "SMDK6410") | |
afdd225d | 708 | /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ |
170a5908 | 709 | .atag_offset = 0x100, |
ba279044 | 710 | .nr_irqs = S3C64XX_NR_IRQS, |
5718df9d BD |
711 | .init_irq = s3c6410_init_irq, |
712 | .map_io = smdk6410_map_io, | |
713 | .init_machine = smdk6410_machine_init, | |
04a49b71 | 714 | .init_time = samsung_timer_init, |
ff84ded2 | 715 | .restart = s3c64xx_restart, |
5718df9d | 716 | MACHINE_END |