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1 | /* linux/arch/arm/plat-s3c64xx/pm.c |
2 | * | |
3 | * Copyright 2008 Openmoko, Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * S3C64XX CPU PM support. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/init.h> | |
16 | #include <linux/suspend.h> | |
17 | #include <linux/serial_core.h> | |
18 | #include <linux/io.h> | |
f98d429d | 19 | #include <linux/gpio.h> |
c656c306 | 20 | #include <linux/pm_domain.h> |
bd117bd1 BD |
21 | |
22 | #include <mach/map.h> | |
fda22577 | 23 | #include <mach/irqs.h> |
bd117bd1 | 24 | |
c656c306 | 25 | #include <plat/devs.h> |
bd117bd1 | 26 | #include <plat/pm.h> |
fda22577 BD |
27 | #include <plat/wakeup-mask.h> |
28 | ||
3501c9ae BD |
29 | #include <mach/regs-gpio.h> |
30 | #include <mach/regs-clock.h> | |
bd117bd1 | 31 | |
8bb86ead | 32 | #include "regs-gpio-memport.h" |
a81c1970 | 33 | #include "regs-modem.h" |
f2bfd174 | 34 | #include "regs-sys.h" |
e8f55885 | 35 | #include "regs-syscon-power.h" |
bd117bd1 | 36 | |
c656c306 MB |
37 | struct s3c64xx_pm_domain { |
38 | char *const name; | |
39 | u32 ena; | |
40 | u32 pwr_stat; | |
41 | struct generic_pm_domain pd; | |
42 | }; | |
43 | ||
44 | static int s3c64xx_pd_off(struct generic_pm_domain *domain) | |
45 | { | |
46 | struct s3c64xx_pm_domain *pd; | |
47 | u32 val; | |
48 | ||
49 | pd = container_of(domain, struct s3c64xx_pm_domain, pd); | |
50 | ||
51 | val = __raw_readl(S3C64XX_NORMAL_CFG); | |
52 | val &= ~(pd->ena); | |
53 | __raw_writel(val, S3C64XX_NORMAL_CFG); | |
54 | ||
55 | return 0; | |
56 | } | |
57 | ||
58 | static int s3c64xx_pd_on(struct generic_pm_domain *domain) | |
59 | { | |
60 | struct s3c64xx_pm_domain *pd; | |
61 | u32 val; | |
62 | long retry = 1000000L; | |
63 | ||
64 | pd = container_of(domain, struct s3c64xx_pm_domain, pd); | |
65 | ||
66 | val = __raw_readl(S3C64XX_NORMAL_CFG); | |
67 | val |= pd->ena; | |
68 | __raw_writel(val, S3C64XX_NORMAL_CFG); | |
69 | ||
70 | /* Not all domains provide power status readback */ | |
71 | if (pd->pwr_stat) { | |
72 | do { | |
73 | cpu_relax(); | |
74 | if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat) | |
75 | break; | |
76 | } while (retry--); | |
77 | ||
78 | if (!retry) { | |
79 | pr_err("Failed to start domain %s\n", pd->name); | |
80 | return -EBUSY; | |
81 | } | |
82 | } | |
83 | ||
84 | return 0; | |
85 | } | |
86 | ||
87 | static struct s3c64xx_pm_domain s3c64xx_pm_irom = { | |
88 | .name = "IROM", | |
89 | .ena = S3C64XX_NORMALCFG_IROM_ON, | |
90 | .pd = { | |
91 | .power_off = s3c64xx_pd_off, | |
92 | .power_on = s3c64xx_pd_on, | |
93 | }, | |
94 | }; | |
95 | ||
96 | static struct s3c64xx_pm_domain s3c64xx_pm_etm = { | |
97 | .name = "ETM", | |
98 | .ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON, | |
99 | .pwr_stat = S3C64XX_BLKPWRSTAT_ETM, | |
100 | .pd = { | |
101 | .power_off = s3c64xx_pd_off, | |
102 | .power_on = s3c64xx_pd_on, | |
103 | }, | |
104 | }; | |
105 | ||
106 | static struct s3c64xx_pm_domain s3c64xx_pm_s = { | |
107 | .name = "S", | |
108 | .ena = S3C64XX_NORMALCFG_DOMAIN_S_ON, | |
109 | .pwr_stat = S3C64XX_BLKPWRSTAT_S, | |
110 | .pd = { | |
111 | .power_off = s3c64xx_pd_off, | |
112 | .power_on = s3c64xx_pd_on, | |
113 | }, | |
114 | }; | |
115 | ||
116 | static struct s3c64xx_pm_domain s3c64xx_pm_f = { | |
117 | .name = "F", | |
118 | .ena = S3C64XX_NORMALCFG_DOMAIN_F_ON, | |
119 | .pwr_stat = S3C64XX_BLKPWRSTAT_F, | |
120 | .pd = { | |
121 | .power_off = s3c64xx_pd_off, | |
122 | .power_on = s3c64xx_pd_on, | |
123 | }, | |
124 | }; | |
125 | ||
126 | static struct s3c64xx_pm_domain s3c64xx_pm_p = { | |
127 | .name = "P", | |
128 | .ena = S3C64XX_NORMALCFG_DOMAIN_P_ON, | |
129 | .pwr_stat = S3C64XX_BLKPWRSTAT_P, | |
130 | .pd = { | |
131 | .power_off = s3c64xx_pd_off, | |
132 | .power_on = s3c64xx_pd_on, | |
133 | }, | |
134 | }; | |
135 | ||
136 | static struct s3c64xx_pm_domain s3c64xx_pm_i = { | |
137 | .name = "I", | |
138 | .ena = S3C64XX_NORMALCFG_DOMAIN_I_ON, | |
139 | .pwr_stat = S3C64XX_BLKPWRSTAT_I, | |
140 | .pd = { | |
141 | .power_off = s3c64xx_pd_off, | |
142 | .power_on = s3c64xx_pd_on, | |
143 | }, | |
144 | }; | |
145 | ||
146 | static struct s3c64xx_pm_domain s3c64xx_pm_g = { | |
147 | .name = "G", | |
148 | .ena = S3C64XX_NORMALCFG_DOMAIN_G_ON, | |
149 | .pd = { | |
150 | .power_off = s3c64xx_pd_off, | |
151 | .power_on = s3c64xx_pd_on, | |
152 | }, | |
153 | }; | |
154 | ||
155 | static struct s3c64xx_pm_domain s3c64xx_pm_v = { | |
156 | .name = "V", | |
157 | .ena = S3C64XX_NORMALCFG_DOMAIN_V_ON, | |
158 | .pwr_stat = S3C64XX_BLKPWRSTAT_V, | |
159 | .pd = { | |
160 | .power_off = s3c64xx_pd_off, | |
161 | .power_on = s3c64xx_pd_on, | |
162 | }, | |
163 | }; | |
164 | ||
165 | static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = { | |
166 | &s3c64xx_pm_irom, | |
167 | }; | |
168 | ||
169 | static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = { | |
170 | &s3c64xx_pm_etm, | |
171 | &s3c64xx_pm_g, | |
172 | &s3c64xx_pm_v, | |
173 | &s3c64xx_pm_i, | |
174 | &s3c64xx_pm_p, | |
175 | &s3c64xx_pm_s, | |
176 | &s3c64xx_pm_f, | |
177 | }; | |
178 | ||
bd117bd1 | 179 | #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK |
bd117bd1 BD |
180 | void s3c_pm_debug_smdkled(u32 set, u32 clear) |
181 | { | |
182 | unsigned long flags; | |
31858479 | 183 | int i; |
bd117bd1 BD |
184 | |
185 | local_irq_save(flags); | |
31858479 JS |
186 | for (i = 0; i < 4; i++) { |
187 | if (clear & (1 << i)) | |
188 | gpio_set_value(S3C64XX_GPN(12 + i), 0); | |
189 | if (set & (1 << i)) | |
190 | gpio_set_value(S3C64XX_GPN(12 + i), 1); | |
191 | } | |
bd117bd1 BD |
192 | local_irq_restore(flags); |
193 | } | |
194 | #endif | |
195 | ||
196 | static struct sleep_save core_save[] = { | |
bd117bd1 BD |
197 | SAVE_ITEM(S3C64XX_MEM0DRVCON), |
198 | SAVE_ITEM(S3C64XX_MEM1DRVCON), | |
bd117bd1 BD |
199 | }; |
200 | ||
201 | static struct sleep_save misc_save[] = { | |
202 | SAVE_ITEM(S3C64XX_AHB_CON0), | |
203 | SAVE_ITEM(S3C64XX_AHB_CON1), | |
204 | SAVE_ITEM(S3C64XX_AHB_CON2), | |
205 | ||
206 | SAVE_ITEM(S3C64XX_SPCON), | |
207 | ||
208 | SAVE_ITEM(S3C64XX_MEM0CONSTOP), | |
209 | SAVE_ITEM(S3C64XX_MEM1CONSTOP), | |
210 | SAVE_ITEM(S3C64XX_MEM0CONSLP0), | |
211 | SAVE_ITEM(S3C64XX_MEM0CONSLP1), | |
212 | SAVE_ITEM(S3C64XX_MEM1CONSLP), | |
348276f4 TF |
213 | |
214 | SAVE_ITEM(S3C64XX_SDMA_SEL), | |
d9018df0 | 215 | SAVE_ITEM(S3C64XX_MODEM_MIFPCON), |
c656c306 MB |
216 | |
217 | SAVE_ITEM(S3C64XX_NORMAL_CFG), | |
bd117bd1 BD |
218 | }; |
219 | ||
220 | void s3c_pm_configure_extint(void) | |
221 | { | |
222 | __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK); | |
223 | } | |
224 | ||
bd117bd1 BD |
225 | void s3c_pm_restore_core(void) |
226 | { | |
227 | __raw_writel(0, S3C64XX_EINT_MASK); | |
228 | ||
229 | s3c_pm_debug_smdkled(1 << 2, 0); | |
230 | ||
231 | s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); | |
232 | s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); | |
233 | } | |
234 | ||
235 | void s3c_pm_save_core(void) | |
236 | { | |
237 | s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); | |
238 | s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); | |
239 | } | |
240 | ||
241 | /* since both s3c6400 and s3c6410 share the same sleep pm calls, we | |
242 | * put the per-cpu code in here until any new cpu comes along and changes | |
243 | * this. | |
244 | */ | |
245 | ||
29cb3cd2 | 246 | static int s3c64xx_cpu_suspend(unsigned long arg) |
bd117bd1 BD |
247 | { |
248 | unsigned long tmp; | |
249 | ||
250 | /* set our standby method to sleep */ | |
251 | ||
252 | tmp = __raw_readl(S3C64XX_PWR_CFG); | |
253 | tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK; | |
254 | tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP; | |
255 | __raw_writel(tmp, S3C64XX_PWR_CFG); | |
256 | ||
257 | /* clear any old wakeup */ | |
258 | ||
259 | __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), | |
260 | S3C64XX_WAKEUP_STAT); | |
261 | ||
262 | /* set the LED state to 0110 over sleep */ | |
263 | s3c_pm_debug_smdkled(3 << 1, 0xf); | |
264 | ||
265 | /* issue the standby signal into the pm unit. Note, we | |
266 | * issue a write-buffer drain just in case */ | |
267 | ||
268 | tmp = 0; | |
269 | ||
270 | asm("b 1f\n\t" | |
271 | ".align 5\n\t" | |
272 | "1:\n\t" | |
273 | "mcr p15, 0, %0, c7, c10, 5\n\t" | |
274 | "mcr p15, 0, %0, c7, c10, 4\n\t" | |
275 | "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp)); | |
276 | ||
277 | /* we should never get past here */ | |
278 | ||
d3fcacf5 AK |
279 | pr_info("Failed to suspend the system\n"); |
280 | return 1; /* Aborting suspend */ | |
bd117bd1 BD |
281 | } |
282 | ||
fda22577 BD |
283 | /* mapping of interrupts to parts of the wakeup mask */ |
284 | static struct samsung_wakeup_mask wake_irqs[] = { | |
285 | { .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, }, | |
286 | { .irq = IRQ_RTC_TIC, .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, }, | |
287 | { .irq = IRQ_PENDN, .bit = S3C64XX_PWRCFG_TS_DISABLE, }, | |
288 | { .irq = IRQ_HSMMC0, .bit = S3C64XX_PWRCFG_MMC0_DISABLE, }, | |
289 | { .irq = IRQ_HSMMC1, .bit = S3C64XX_PWRCFG_MMC1_DISABLE, }, | |
290 | { .irq = IRQ_HSMMC2, .bit = S3C64XX_PWRCFG_MMC2_DISABLE, }, | |
291 | { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_BATF_DISABLE}, | |
292 | { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE }, | |
293 | { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_HSI_DISABLE }, | |
294 | { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE }, | |
295 | }; | |
296 | ||
bd117bd1 BD |
297 | static void s3c64xx_pm_prepare(void) |
298 | { | |
fda22577 BD |
299 | samsung_sync_wakemask(S3C64XX_PWR_CFG, |
300 | wake_irqs, ARRAY_SIZE(wake_irqs)); | |
301 | ||
bd117bd1 BD |
302 | /* store address of resume. */ |
303 | __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0); | |
304 | ||
305 | /* ensure previous wakeup state is cleared before sleeping */ | |
306 | __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT); | |
307 | } | |
308 | ||
c656c306 MB |
309 | int __init s3c64xx_pm_init(void) |
310 | { | |
311 | int i; | |
312 | ||
313 | s3c_pm_init(); | |
314 | ||
315 | for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++) | |
316 | pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd, | |
317 | &pm_domain_always_on_gov, false); | |
318 | ||
319 | for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++) | |
320 | pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false); | |
321 | ||
c0d6cfd3 | 322 | #ifdef CONFIG_S3C_DEV_FB |
c656c306 MB |
323 | if (dev_get_platdata(&s3c_device_fb.dev)) |
324 | pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev); | |
c0d6cfd3 | 325 | #endif |
c656c306 MB |
326 | |
327 | return 0; | |
328 | } | |
329 | ||
330 | static __init int s3c64xx_pm_initcall(void) | |
bd117bd1 BD |
331 | { |
332 | pm_cpu_prep = s3c64xx_pm_prepare; | |
333 | pm_cpu_sleep = s3c64xx_cpu_suspend; | |
334 | pm_uart_udivslot = 1; | |
31858479 JS |
335 | |
336 | #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK | |
337 | gpio_request(S3C64XX_GPN(12), "DEBUG_LED0"); | |
338 | gpio_request(S3C64XX_GPN(13), "DEBUG_LED1"); | |
339 | gpio_request(S3C64XX_GPN(14), "DEBUG_LED2"); | |
340 | gpio_request(S3C64XX_GPN(15), "DEBUG_LED3"); | |
341 | gpio_direction_output(S3C64XX_GPN(12), 0); | |
342 | gpio_direction_output(S3C64XX_GPN(13), 0); | |
343 | gpio_direction_output(S3C64XX_GPN(14), 0); | |
344 | gpio_direction_output(S3C64XX_GPN(15), 0); | |
345 | #endif | |
346 | ||
bd117bd1 BD |
347 | return 0; |
348 | } | |
c656c306 MB |
349 | arch_initcall(s3c64xx_pm_initcall); |
350 | ||
cc8f252b | 351 | int __init s3c64xx_pm_late_initcall(void) |
c656c306 MB |
352 | { |
353 | pm_genpd_poweroff_unused(); | |
bd117bd1 | 354 | |
c656c306 MB |
355 | return 0; |
356 | } |